Single Chip CMOS Transmitter for UWB Impulse Radar Applications · 2016-01-29 · PLL whereas in UWB system these parts can be omitted. Fig. 1 Conventional Integrated Narrowband Transceiver.

A Thesis for the Degree of Master

Single Chip CMOS Transmitter for UWB Impulse Radar

Applications

Chang Shu

School of Engineering

Information and Communications University

2009

Single Chip CMOS Transmitter for UWB Impulse Radar

Applications

Single Chip CMOS Transmitter for UWB Impulse Radar

Applications

Advisor: Professor Sang-Gug Lee

by

Chang Shu

School of Engineering

Information and Communications University

A thesis submitted to the faculty of Information and

Communications University in partial fulfillment of the re-

quirements for the degree of Master of Science in the

School of Engineering

Daejeon, Korea

Dec. 1st, 2008

Approved by

(Signed)

Professor Sang-Gug Lee

Major Advisor

Single Chip CMOS Transmitter for UWB Impulse Radar

ApplicationsChang Shu

We certify that this work has passed the scholastic standards re-quested by the Information and Communications University as a thesisfor the degree of Master

December 1st, 2008

Approved: Chairman of the CommitteeSang-Gug Lee, ProfessorSchool of Engineering

Committee MemberHyung-Joun Yoo, ProfessorSchool of Engineering

Committee MemberSeung-Tak Ryu, Assistant ProfessorSchool of Engineering

M.S.20062560

Chang Shu

Single Chip CMOS Transmitter for UWB Impulse Radar

Applications

School of Engineering. 2008, 63p.

Major Advisor: Professor. Sang-Gug Lee.

Text in English

i

Abstract

Ultra-Wide Band (UWB) technology has been studied intensively these

years. And transmitter plays an important role in the UWB transceiver sys-

tem since it has the function of generating the UWB impulses which is used

to transmit the information through propagation channels. Among the vast

applications of UWB technology, UWB radar is a hot spot since it is widely

used in the detection of moving object in the field of radar.

This thesis presents the design of an on chip transmitter for Ultra-

Wideband (UWB) Impulse Radar application. Short pulses with duration of

4.5 ns and bandwidth of about 500 MHz are generated by up-converting the

triangular shaped envelope to the center frequency by a specially designed

energy efficient mixer.

In this UWB Impulse Radar Project, two versions of transmitter test pat-

tern chips were designed, fabricated, and measured. Both versions of the

transmitters can work at pulse repetition frequency of over 1 MHz with over

ii

-2 dBm output power at 50 ohm load. Output pulse spectrum centered at 4.3

GHz can fit FCC spectrum mask with a side-lobe suppression of 20 dB. De-

signed in 0.18-µm CMOS technology, the two circuits have a chip area of

0.45 mm 1.2 mm.

The details of architecture decision and design process are discussed in

this thesis. The improvement of second chip is also analyzed comparing with

first version chip.

iii

Contents

Abstract ................................................................................................................. i

Contents...............................................................................................................iii

I. Introduction .................................................................................................. 1

1.1 UWB Definition and UWB Radar................................................... 3

1.2 UWB FCC Mask and Regulations................................................... 7

1.3 Structure of the Thesis ...................................................................... 9

II. UWB System Architectures ..................................................................... 10

2.1 Several reported UWB system Architectures ................................ 11

2.1.1 Sampling architecture .........................................................................12

2.1.2 Non-Coherent Architecture.................................................................15

2.1.3 Coherent Architecture .........................................................................16

2.2 UWB architecture used in this Project ......................................... 18

III. UWB Transmitter and Pulse Generator............................................... 19

3.1 Pulse Shape Decision and Analysis............................................... 23

3.2 System Requirement......................................................................... 26

3.3 System Architecture of TX............................................................. 27

IV. UWB Transmitter Circuit Structure...................................................... 29

4.1 Charge Pump .................................................................................... 30

4.2 Mixer ................................................................................................. 32

4.3 Single to Differential Converter ..................................................... 36

4.4 Ring Oscillator.................................................................................. 38

4.5 Drive Amplifier (DA)...................................................................... 40

4.6 Single to Differential Converter ..................................................... 42

iv

4.7 Amplifier for Template Pulse ......................................................... 43

V. Simulation Result of Transmitter and Layout .................................... 44

5.1 Simulation Result ............................................................................. 44

5.2 Overall simulation result ................................................................. 46

5.3 Layout of TX part and test block................................................. 47

VI. Measurement Results ................................................................................ 48

6.1 First Version Transmitter measurement.......................................... 50

6.2 Second Version Transmitter measurement ..................................... 53

VII. Conclusions ............................................................................................... 56

References .......................................................................................................... 57

Acknowledgement ............................................................................................. 60

Curriculum Vitae ............................................................................................. 62

v

Lists of Tables

Table I. The comparisons between the architectures in the following........... 11

Table II. Summary of different shape window ................................................ 25

Table III. System specifications ......................................................................... 26

Table IV. Summary of Post-Simulation in Version I chip .............................. 46

Table V. Summary of Post-Simulation in Version II chip .............................. 46

Table VI. Simulation and Measurement of first chip...................................... 52

Table VII. Simulation and Measurement of second chip................................ 55

Table VIII. Comparison of UWB transmitter.................................................. 55

vi

Lists of Figures

Fig. 1 Conventional Integrated Narrowband Transceiver................................ 4

Fig. 2 UWB “digitally” Radio .............................................................................. 4

Fig. 3 Waveform of pulse train used in UWB Radar......................................... 6

Fig. 4 UWB spectrum mask and FCC part15 limit ........................................... 7

Fig. 5 UWB spectrum mask of Korea ................................................................. 8

Fig. 6 Sampling architecture UWB transceiver ............................................... 12

Fig. 7 Time-interleaved ADC in UWB receiver ............................................... 13

Fig. 8 Direct Sampling UWB Transceiver [8] .................................................. 14

Fig. 9 Direct Sampling UWB Transceiver [9] .................................................. 14

Fig. 10 Non-coherent UWB Transceiver [11] ................................................... 15

Fig. 11 Non-coherent UWB Transceiver [12] ................................................... 16

Fig. 12 Coherent transceiver used for ranging and communication [13] ...... 17

Fig. 13 UWB Impulse Radar Transceiver ........................................................ 18

Fig. 14 Burst-mode Pulse Generator [2] ........................................................... 21

Fig. 15 The operation principle of “carrier based UWB”............................... 22

Fig. 16 Gaussian shape envelope and frequency spectrum............................. 23

Fig. 17 Triangular shape envelope and frequency spectrum.......................... 24

Fig. 18 Comparison of several functions’ characteristics................................ 25

Fig. 19 Architecture of this transmitter ............................................................ 27

Fig. 20 Architecture of this transmitter in Transceiver System ..................... 28

Fig. 21 Charge Pump input clock, circuit and its output ................................ 31

Fig. 22 Charge Pump Output............................................................................. 31

vii

Fig. 23 Circuit of Mixer Proposed ..................................................................... 34

Fig. 24 Output of Mixer...................................................................................... 34

Fig. 25 With added switching pair, the outputs are “in phase”...................... 35

Fig. 26 Without added switching pair, the outputs are “differential”........... 35

Fig. 27 Differential to single converter.............................................................. 37

Fig. 28 Ring Oscillator circuit............................................................................ 39

Fig. 29 Oscillator Output.................................................................................... 39

Fig. 30 Drive Amplifier Circuit.......................................................................... 41

Fig. 31 Single to Differential Converter............................................................ 42

Fig. 32 Template Amplifier ................................................................................ 43

Fig. 33 Output of Drive Amplifier and its frequency spectrum ..................... 44

Fig. 34 Template Waveform............................................................................... 45

Fig. 35 Frequency Spectrum of Template......................................................... 45

Fig. 36 Layout of TX........................................................................................... 47

Fig. 37 Layout of TX........................................................................................... 47

Fig. 38 Die Photo of TX first version................................................................. 49

Fig. 39 Die Photo of TX second version ............................................................ 49

Fig. 40 Measured pulse time domain shape of first version chip.................... 51

Fig. 41 Measured pulse frequency spectrum of first version chip.................. 52

Fig. 42 Measured DA output of second version TX chip................................. 54

Fig. 43 Template output of second version TX chip (with buffer) ................. 54

1

I. Introduction

Ultra-Wide Band (UWB) technology has been a hot topic for a long time

since 1960s when a series of sample and hold receivers emerged and were

imported to UWB applications. Pulse generation, compression and

correlation and matched filter method has been developed since 1950s by

research centers. First UWB system for communication was built in 1970s

and it can also be used for Radar application [1]. And since late 1980s, Time

Domain Company was founded and has developed the first UWB chip used

in wireless communication, radar, and sensors. And in the new millennium

the well-known UC-Berkeley team has developed digitally UWB chipset

based on sampling after front-end amplifiers (FEA). UWB system also

evolutes from on/off keying [2] or pulse positioning modulation to more

complicate higher order modulations, such as BPSK and even FSK [3] .

Several pulse-based modulation schemes are found in literature such as

Pulse Amplitude Modulation (PAM), On–Off Keying (OOK), Pulse-Position

Modulation (PPM) or Bit-Position Modulation (BPM), Binary Phase-Shift

Keying (BPSK). However, due to the system of the UWB impulse radar,

there is no modulation involved in the transmitter part. The radar only needs

to measure the reflected pulses, so the important issue is the quality of the

pulse shape in time domain. And also, because of FCC regulation, in the

frequency domain, the FCC mask of Korea must be met as well.

2

It is somewhat interesting to look back and have some intuition of the

pulsed communication method and what is now called “Ultra-Wide Band”.

Although it seems like UWB has a short history comparing with other kind

of communication technology, it was actually used one hundred years ago

when the sparks were generated by Michael Faraday when he did the famous

experiment of discharging capacitor (transmitting pulse) and generating

sparks in another inductor (receiving the pulse). It is obvious that the sparks

are generated by manually turn on/off the switches which trigger the genera-

tion of sharp pulses and this is similar with the phenomenon of lightning

which, of course, has the voltage amplitude of millions of volts.

3

1.1 UWB Definition and UWB Radar

The UWB Signal Definition is: Fractional bandwidth is greater than 20%

of the center frequency, or the -10dB bandwidth occupies 500 MHz or more

of spectrum.

The intrinsic advantages of UWB can be seen from the famous Shannon

equation:

SNR)](1[logBW C 2 (1)

Where: C = Channel Capacity (bits/sec)

BW= Channel Bandwidth (Hz)

SNR= Signal to Noise Ratio

We can see that the channel capacity is proportional to the bandwidth and

thus, UWB has the potential to provide high data rate at moderate SNR. For

applications which face relatively large interferences or lower SNA, the

UWB can still provide enough data rate. This is the fundamental advantage

of UWB. The other advantages of UWB including: large bandwidth

potentially provides higher data transmission capability; resistance to

interference such as multi-path fading and noise; low EM environment

pollution and precise time resolution ability suitable for precise ranging and

timing [4]. Due to these tempting characteristics UWB technology has been

greatly used in RFIC tag [5], sensor networks, high data rate transceiver, etc.

From the system level comparison, UWB system has its own advantage of

4

simplicity, and low cost which can be seen from the comparison of Fig. 1

and Fig. 2. As the conventional narrowband transceiver needs mixer part and

PLL whereas in UWB system these parts can be omitted.

Fig. 1 Conventional Integrated Narrowband Transceiver.

Fig. 2 UWB “digitally” Radio.

As for the UWB Radar, which is one of the main application of UWB

technology, because of the intrinsic characteristic of UWB signal, this kind

of Radar has its advantages over other kind of radar. Such as: penetration of

absorbers because of molecular resonances; resistant to multi-path; low

probability of intercept (LPI), and resistance to jamming, because short

5

pulse implies narrow range gates and therefore not susceptible to continuous

wave (CW) jamming.

UWB radars have become popular in recent years and have a vast

application in civil engineering and industry, such as family surveillance,

medical instrument, detecting living people buried under debris, movement

sensors, microwave imaging, collision avoidance [4]. There are several types

of UWB radar such as ground or wall penetration radar, UWB synthesis

aperture radar (SAR), medical imaging radar, UWB ranging radar [6]. All of

these UWB radars are based on the radar principle. For the positioning using

UWB radar, it is straightforward and the distance can be measured by

calculating the time delay during transmission. Although the principle of

detection is almost same among various reported radars: finding the

reflected pulse and compare the time delayed between the transmitted and

received pulses.

The operation of UWB Radar is like this. Send a pulse train (Fig. 3) from

the transmitter and after the pulse reflected back from the target, the receiver

detects the pulse by amplifying, correlating and digital sampling.

6

Fig. 3 Waveform of pulse train used in UWB Radar.

7

1.2 UWB FCC Mask and Regulations

Due to the FCC rule, a large slot of unlicensed band from 3.1 GHz~10.6

GHz is given. This band is suitable for the UWB radar application which

requires wide bandwidth. According to the low spectrum power density of

this FCC mask part 15 limits (Fig. 4), the WLAN application occupies the

band between 5 GHz and 6 GHz and the band above 6 GHz are reserved for

future usage. But for Korean domestic FCC rule, the FCC mask is more

stringent, which is shown in Fig. 5.

Fig. 4 UWB spectrum mask and FCC part15 limit.

8

Fig. 5 UWB spectrum mask of Korea.

From our design requirement based on both FCC rule of Korea and part 15

limit, we decided to use the bandwidth between 3.6 ~ 5.15 GHz, with

sidelobe rejection of 20 dB. Since the band between 3.1 GHz and 3.4 GHz

and above 5.15 GHz are reserved by Korean domestic FCC regulation.

We can see that the power spectrum density for the UWB pulse should be

below -41.3 dBm/MHz between 3.6 ~ 5.15 GHz, and below -69 dBm/MHz

at the border of the selected band. However, in the really application this is

not easy to realize, since the side-lobe rejection would be about 30 dB in this

case. Thus, we decide the pulse spectrum density should be below -65

dBm/MHz, which corresponds to side-lobe rejection of about 25 dB. This

FCC mask is very important for the choosing of architecture and system

specifications which will be discussed later.

9

1.3 Structure of the Thesis

This thesis is written in the following structure. In Section II, we propose

the UWB system architectures and decide the system we are using for this

UWB radar system. In Section III, we propose various types of UWB

transmitter architecture and introduce the core block of the UWB

transmitter— pulse generator (PG). In Section IV, the proposed transmitter

individual architecture and its pulse generator are introduced in operation

principle. In Section V, we present the circuits design of transmitter

individual blocks including simulation result of each block. In Section VI,

measurement results are presented and discussed for two versions of chips.

Final conclusion is in Section VII.

10

II. UWB System Architectures

FCC rule has given nearly 7.5 GHz (from 3.1 GHz to 10.6 GHz) of

unlicensed band for the indoor and outdoor application to UWB. Such wide

bandwidth makes various design of UWB system possible based on different

applications. For communication purpose oriented UWB, wider bandwidth

makes very high data rate possible, but that also requires transmitter and

especially the UWB receiver hardware to be fast enough to deal with such

high data rate (even as high as multi-GB/s).

Several architectures are introduced these years. And they can be put into

several categories: the first category is using high speed sampling method,

another way is using frequency domain processing method to relieve the

sampling speed requirement, and another category is using more analog

processing by coherent scheme and non-coherent scheme.

For radar applications, analog correlation method is always used since

analog correlation is suitable for the ranging detection since the pulse has the

wider pulse width which is suitable for detection. And such architectures

will be introduced in detail in the following parts.

11

2.1 Several reported UWB system Architectures

From literature study, we categorize the UWB system to the following

three kinds of architectures: sampling architecture, non-coherent architecture,

and coherent architecture. The first two architectures are widely used in

UWB communications and the last architecture are used for communication

with good timing ability thus that one is suitable for Radar application. And

direct sampling method can be aided with band-selected frequency domain

processing. These architectures are briefly introduced for the understanding

of this project’s system architecture and its advantages. And their

characteristics are summarized in Table I.

Table I. The comparisons between the architectures in the following

Architectures System

Complexity

Hardware

requirement

Power

Consumption

Timing

accuracy

Direct Sampling High Very high Very high Not good

Non-coherent Low Low Low Good

Coherent Moderate Moderate Moderate Very good

12

2.1.1 Sampling architecture

Sampling architecture has been reported as “Soft-ware Defined Radio” for

the receiver architectures because the front-end part is just a LNA and

amplifier with no other analog blocks, and a high speed ADC directly

samples the amplified signal and gives it to DSP for processing. The

advantage of this architecture is the ability to reconfigurate by changing

DSP part only with software, thus it can receiver any kind of modulation

with the same hardware, which is the future of UWB and any kind of

application needs high data rate. Fig. 6 basic shows this architecture and Fig.

7 shows the detailed part of ADC block since this is the core part of the

receiver. This ADC is using interleaved technique and can do very high

speed sampling with less power consumption [7].

Fig. 6 Sampling architecture UWB transceiver.

13

Fig. 7 Time-interleaved ADC in UWB receiver.

Here we present two examples of UWB transceivers using this direct

sampling architecture. The first one is from UC-Berkeley team, the UWB

transceiver is shown in Fig. 8. It is using the time interleaved sampling

method and thus lowers the power consumption greatly. The system

complexity lies in the clock generation and ADC part.

The second example is using this similar time-interleaved sampling

method and can achieve 20 GB/s sampling rate. The digital FPGA is a

bottleneck is this case since a large amount of data needs to be processed.

14

Fig. 8 Direct Sampling UWB Transceiver [8].

Fig. 9 Direct Sampling UWB Transceiver [9].

15

2.1.2 Non-Coherent Architecture

The operation principle of non-coherent architecture is like this: in the re-

ceiver part, the incoming UWB pulse signal multiples with it self thus pro-

ducing an low frequency (near DC) signal, and this near DC signal can be

processed using analog blocks such as VGA and LPF and then fed into sam-

pling part. Since non-coherent system uses no synchronization between

transmitter and receiver, thus reduces complexity [10, 11].

Fig. 10 Non-coherent UWB Transceiver [11].

16

2.1.3 Coherent Architecture

Coherent system uses precise timing method such as delay lock loop

(DLL) to cope with the timing between the transmitter and receiver

(synchronization). It is more complex than its non-coherent counterpart but

can achieve higher data rate [12, 13]. For radar receiver, we can use both of

two schemes, but coherent scheme have better timing precision than the

Non-coherent architecture.

Fig. 11 Non-coherent UWB Transceiver [12].

17

Fig. 12 Coherent transceiver used for ranging and communication [13].

18

2.2 UWB architecture used in this Project

The basic architecture of UWB Radar is shown below, and this

presentation is about the transmitter (TX) part. Our whole radar system is

shown below which uses coherent scheme, and this work is a transmitter

which consists of the pulse generator and a drive amplifier (DA). The pulse

generator has two functions, one is to provide template for the correlator in

the receiver, and the other function is the transmitter: generate pulses to the

antenna. We will have a detailed discussion about the TX part of this

architecture shown in Fig. 13.

Fig. 13 UWB Impulse Radar Transceiver.

19

III. UWB Transmitter and Pulse Generator

From the architecture shown in Fig. 13, we can see that the main block of

the transmitter is the pulse generator (PG), thus we first introduce kinds of

PG so far and do the discussion and design own architecture.

There are many types of pulse generators so far, the earliest pulse

generator uses step recovery diode (not integrated), and other use analog or

digital method. Analog method focus on the generation of Gaussian shaped

pulses because it has good transfer ability and not much distorted during

transmission. According to the bandwidth requirement, several order of

derivative of Gaussian pulse is used, because higher derivative of Gaussian

pulse gives narrower bandwidth [14]. And these pulse generators with high

order of over seven derivatives usually have a much larger bandwidth

comparing with our 500 MHz target (barely meet the FCC mask).

In our system this derivative method is not suitable since we would need

very high order (nearly 30) of derivatives of Gaussian pulse. For the digital

generation methods, one way is to use the pulse pattern generation method

which combines many single pulses to generate desired pulse shape [15].

But the reported digitally controlled pulse generator operates in a bandwidth

of over 1 GHz and the pulse width is much smaller than 4ns so it is easier to

combine several edges into one pulse. Although the digital transmitter is

attractive in novelty, it needs about 32 edge combination cells to combine

into a single pulse which is 4 ns and center frequency is 4 GHz (similar to

20

our transmitter target), and the circuit is too complicated and power

consuming and hard to adjust each cell.

Another way for digitally generation of pulse reported in [16], which uses

very complicated architecture of using VGA to amplify each edge coming

from a register stack at different channel, and using integrator to sum up the

edge to form a single pulse. This approach is also not suitable for our target,

because we would need many channels since we have about 30 edges for

each pulse.

Another simple and intuitive way to generate a short high frequency pulse

is to using burst mode oscillator. By turn on and off the oscillator using gate

duration, the pulse which has center frequency of oscillator can be generated

[2, 17]. However, in [17] the gated pulse has the shape of rectangle and has a

high sidelobe power in spectrum which has to be filtered out, thus increasing

the system complexity and chip size. In [2], the author uses a modified way

to control the pulse and can achieve a side lobe rejection of over 20 dB by

using a burst mode LC oscillator. But the shape of pulse is fixed and not

optimal, and LC oscillator occupies large chip area. The circuit and output is

shown below in Fig. 14.

21

Fig. 14 Burst-mode Pulse Generator [2].

What we present here is a “carrier based modulated UWB pulse

generator”, which uses a triangular shaped envelope signal to modulate the

ring oscillator’s center frequency. Comparing with [18], which also uses a

triangular signal modulating with a frequency generated by PLL, this

transmitter has simplified the circuits of each individual block and proposes

a novel way of up converting the envelope to oscillator frequency. The

operation principle is illustrated in Fig. 15. The triangle envelope which has

a sidelobe rejection of over 20 dB is up-converted to the center frequency

(LO). There are several other papers using this scheme, but the envelopes

they used to modulate center frequency are different [19, 20]. In [19], a

Gaussian shaped envelope is used, but it is hard to generate a real Gaussian

envelope and the result turn out to be very different from the ideal Gaussian

shape, thus the side-lobe rejection is not good. In [20], a “tanh” shaped pulse

22

is generated as envelope, but the result is similar to the triangular shaped

envelope, although in theory the tanh does have better sidelobe rejection

ability. So, considering the system requirement and circuit complexity and

performance trade off, we decide to use the triangular shaped envelope and

use the carrier based UWB architecture, the operation principle of which is

shown in Fig. 15. And the detail discussion of pulse envelope selection is in

the following Chapter 3.1.

Fig. 15 The operation principle of “carrier based UWB”.

23

3.1 Pulse Shape Decision and Analysis

From literature study of transmitter, we find that the pulse which has a

shape of Gaussian can provide the best side-lobe rejection [20]. The time

domain function for Gaussian pulse is like below, and has the time domain

shape of Fig. 16, and the pulse has the envelope of Gaussian is our target.

2

2

2t

pGauss eVV

. (2)

Fig. 16 Gaussian shape envelope and frequency spectrum.

From [20], the frequency spectrum side-lobe rejection can be over 45 dBr,

which can fit our transmitter FCC mask. So, we decide to generate a pulse

which has the envelope similar to that of Gaussian pulse. In this TX, we use

the triangular pulse as the envelope, which is shown in Fig. 17.

24

Fig. 17 Triangular shape envelope and frequency spectrum.

We can see that the side lobe rejection can be about nearly 30 dBr.

Because of the nonlinearity of the system operation, the triangular wave will

be look like a near Gaussian shape, so it can meet our target. What’s below

is the comparison of time domain and frequency domain characteristic of

several common functions as envelope. We can see that the triangular

envelope can meet our target and can be realized by circuit easily. The

summary of most of the pulse envelope is in Table. II, we choose the

triangular shape which can provide over 25 dB of side-lobe suppression

capability.

25

Fig. 18 Comparison of several functions’ characteristics.

Table II. Summary of different shape window

Window

type

Sidelobe

(dBc)

Blackman -57

Hamming -41

Hann -31

Rectangular -13

Triangular -25

Half-sine -22

Gaussian -45

26

3.2 System Requirement

From system link budget of the UWB-IR, the specification of the TX is

shown in Table III.

Table III. System Specifications

And also, the Radar system in our project requires the TX part to provide

the template pulse for the receiver part. So, a template of 800 mV is required

also, which has the similar characteristic as the TX output.

Parameters Value

TX output 0 dBm

Template output 800 mV

Center frequency 4.30 GHz

Side lobe rejection 25 dB

bandwidth 500 MHz

Pulse width about 4 ns

27

3.3 System Architecture of TX

The architecture of our TX is shown below (Fig. 19). The clock control

the generation of triangular envelope, and the triangular envelope which has

a bandwidth of 500 MHz is up-converted to our center frequency (4.30

GHz) by the Mixer; a differential to single converter is needed to get the

triangular pulse from a differential output of the mixer. And the pulse is fed

to the drive amplifier and an external PA for the Antenna; the pulse is also

sent into another branch same as the upper part, which also fed into the

single to differential converter for providing the template for the receiver.

Fig. 19 Architecture of this transmitter.

The TX part in the whole system has two functions as we have discussed

in Chapter II, one is to provide pulse to the antenna, and the other is to pro-

vide template for the coherent receiver. Thus, the whole architecture of TX

part in this UWB transceiver is shown in Fig. 20.

28

Fig. 20 Architecture of this transmitter in Transceiver System.

29

IV. UWB Transmitter Circuit Structure

We use the “carrier based modulated UWB” scheme for this transmitter

shown in Fig. 15. Same scheme is also used before by [18, 19, 20], but the

triangular envelope used in this transmitter is different from [18, 19], and the

circuits to realize each block are much different from [18]. The core of this

transmitter is the pulse generator, which consists of envelope generator, up-

converting mixer, and ring oscillator. As the output of mixer is differential, a

differential to single converter is also applied using a traditional current

mirror topology. Finally, the modulated single-ended pulse is amplified by a

two-stage drive amplifier which is matched with 50 ohm load and can

provide -2 dBm output powers. The goal of this transmitter is to generate

high amplitude (over 500 mV) pulse which has bandwidth of about 500

MHz and sidelobe rejection of over 20 dB. Because we are using the 3.1

GHz to 5.15 GHz band, which make our center frequency set to be 4.3 GHz,

in order to avoid the interference domestic regulation of Korea also. And as

a part of radar system, the power consumption should be small, using 1.8-V

supply voltage.

30

4.1 Charge Pump

The function of the charge pump is to generate a triangular shaped

envelope, which is used to modulate the “carrier frequency” to generate the

desired spectrum mask. Similar approach has been used in [18] and [20], but

in [18], the triangular shaped envelope is generated by a more complicated

circuit. And [20] use external triangular signal. The idea of using charge

pump to generate triangular comes from the “edge combination method”

which is used to form pulse using digital way in [15], but in [15] they did

not use this “carrier based UWB” and use edge combination approach

instead. The merit for this approach of generate triangular signal is that it

can generate high amplitude envelope with little power consumption. In Fig.

21, schematic of charge pump and its output is shown. The two input clocks:

CLK_N and CLK_P are generated using DTG 5334 data timing generator

for this transmitter test chip, while it is generated by the delay line for the

whole UWB radar system. By the tuning of bias for M1 and M4, the

capacitor which is about 2-pF will be charged when CLK_P is low and

discharged when CLK_N is high. If the current of charging and discharging

is same, the output of charge pump would generate a triangular signal with a

width of designed value 5.5 ns, and the amplitude is about 0.7 V with an

offset of 450 mV. This envelope will be directly connected with the mixer.

The output of this CP is shown in Fig. 22.

31

Fig. 21 Charge Pump input clock, circuit and its output of triangular

envelope.

Fig. 22 Charge Pump Output.

32

4.2 Mixer

Mixer block is specially designed for this transmitter. It is basically

designed out of a single balance mixer with an added switch pair. As we

know, single-balanced mixer is always used in the receiver part, and for a

transmitter which operate at 4.3 GHz center frequency, if we use single

balanced mixer as the up-conversion mixer, there would be large LO leakage

to the output, because the single balance mixer does not have the LO

suppression ability which double balanced mixer has. But here we still could

use a modified version of single balanced mixer to up-convert the envelope,

because this transmitter has some special characteristics. The input IF, which

is the triangular envelope generated by charge pump, has a big amplitude

and small time duration. Using this characteristic, a novel mixer idea is

implemented in this transmitter: we add another differential switch pair to

the single balanced mixer, as shown in Fig. 23. Because the input envelope

has high amplitude and the offset is as small as 450 mV, this mixer has

modulated pulse output only when there is a big envelope coming in. For the

rest of time, it does not have DC current since the Gm stage is biased at such

low voltage (same with offset). Thus when there is no DC current, this mixer

is the same as a double passive balanced mixer and with no DC current

consumption, and thus it has LO suppression function. And the merit here is

that we do not need to add DC current source for the added switching pair,

which is the novelty of this up-converting mixer. The output is shown in Fig.

33

24 which consists of two differential output of the mixer. As we can see,

when there is no pulse envelope coming into input, the two differential

output is “in phase” (Fig. 25), which means it works like a double balanced

passive mixer with LO suppression ability. But in the contrast, without this

switching pair (single-balanced up-conversion mixer), the two different

output is “differential” as it should be (Fig. 26). The simplest way to explain

this LO suppression functioning is to consider this mixer as an open circuit

at both pairs’ tail current source when there is no input envelope, thus of

course Out+ and Out- are symmetrical and identical or “in phase” as the load

is same for the differential outputs which is exactly like double balanced

passive mixer. When we take the output of mixer differentially, they cancel

each other. And when there is big envelope coming in, the envelope is

modulated and we have differential output which can be converted to single

ended pulse with a triangular shaped envelope. Thus we need a differential

to single converter after this mixer.

34

Fig. 23 Circuit of Mixer Proposed.

Fig. 24 Output of Mixer.

35

Fig. 25 With added switching pair, the outputs are “in phase”.

Fig. 26 Without added switching pair, the outputs are “differential”.

36

4.3 Single to Differential Converter

The role of differential to single converter is to make the differential

output of mixer into single-ended. As we can see that the output of the mixer

is like “V” shaped, that is because of the triangular shape of envelope shown

in Fig. 23 is modulated by the LO signal which comes from the ring

oscillator. In order to turn them into a symmetrical pulse like Fig. 15, a

subtract function circuit is needed. We can use an on chip transformer to do

this function, but it is not easy to integrate and consumes big chip area. Here,

we decide to use the simple topology of differential to single converter [21],

which is shown in Fig. 27. The PMOS transistors are used at the input

because of the input in Fig. 27 has the shape of “V”, and the NMOS

transistors are used as at the current mirror thus the phase delay of this

subtract circuit can be minimized. All of the transistors are using the

minimum size in order to reduce the phase delay during subtract process and

make this to be nearly an ideal subtraction circuit.

37

Fig. 27 Differential to single converter.

38

4.4 Ring Oscillator

A three-stage ring oscillator is designed using the typical circuit topology

[22]. Because there-stage ring oscillator has smaller stage delay, we can

achieve high oscillation frequency without consume much current. The

circuit is shown in Fig. 28. This type of oscillator oscillate at lower

frequency when the bias is smaller, thus the current to charging and

discharging the capacitance of transistors is smaller, which lead to longer

stage delay, thus lower oscillation frequency. Current consumption of this

ring oscillator is about 5 mA using 1.8 V supply voltage and the layout area

is less than 0.01 mm^2. The tuning range of oscillation frequency is from 3.7

GHz to 6.7 GHz from measurement result by changing the bias of tail

current source. And the time transient response is shown in Fig. 29 with the

frequency spectrum.

39

Fig. 28 Ring Oscillator circuit.

Fig. 29 Oscillator Output.

40

4.5 Drive Amplifier (DA)

In order to amplify the pulse from the output of differential to single

converter and get -3 dBm output power which is matched to 50 ohm, a two-

stage drive amplifier is designed. The topology of drive amplifier is using

very popular cascode topology at each stage. The first stage of the drive

amplifier can be turned off by disable the CG stage transistor using a clock.

The clock goes through two inverters to control the bias of CG stage and

these inverters act as a buffer to increase the loading ability of the clock. The

reason to turn it off is for the whole radar system application in the future. In

this test pattern, we enable it all the time. The gain of two-stage DA is about

13 dB, and consumes 7 mA DC current from simulation and it has an IIP3 of

6 dBm when the input is using 125 ohm signal source which is equal to the

output impedance of the block before DA. The total circuit is shown in Fig.

30.

41

Input

Bondingwire

Output matched 50ohm

DA turn on/off control

Fig. 30 Drive Amplifier Circuit.

42

4.6 Single to Differential Converter

From the system architecture of the TX, we can see that the output of the

differential to single converter also goes to another branch besides the Drive

Amplifier. The function of this branch is to provide the Pulse Template to the

receiver, and it will be given to the correlator (which is a multiplier) in the

receiver. We use the simple CS topology to get the two differential output.

The topology is shown in Fig. 31.

Fig. 31 Single to Differential Converter.

43

4.7 Amplifier for Template Pulse

After the Single to Differential converter, we get the differential template,

and since the receiver need about 800 mV of each template, we need an

Amplifier for the template. Here we use the differential amplifier for the

differential template. The interface issue between the correlator and this

amplifier is a problem. We manage to use the inductor peaking for high

output template swing. Thus the inductor resonate with the receiver

correlator input capacitance at our center frequency for inductor peaking.

The size of the inductor is about 3.5 nH. The current consumption of this

Amplifier is about 3.3 mA at 1.8 V supply voltage. From system level

simulation we get the differential template each is 800 mV peak to peak. The

circuit topology is shown in Fig. 32.

Fig. 32 Template Amplifier.

44

V. Simulation Result of Transmitter and Layout

5.1 Simulation Result

Fig. 33 is the output of drive amplifier from simulation of first chip. The

output pulse has about 700 mV peak-peak-voltage at 50 ohm load, which is

about 0 dBm. The side lobe rejection is about 29 dB, which is between the

25 dB and 45 dB and it shows that the system architecture is reasonable. The

bandwidth of the pulse is about 500 MHz and it can be tuned by the

envelope of Charge Pump.

Fig. 33 Output of Drive Amplifier and its frequency spectrum.

45

The template output for the correlator in the receiver is shown in Fig. 34.

It has a near Gaussian shape so the side lobe rejection is 34 dB (Fig. 35).

Fig. 34 Template Waveform.

Fig. 35 Frequency Spectrum of Template.

46

5.2 Overall simulation result

The simulation result is shown in Table IV. The second version chip has

different result because of some modifications in the layout and we use

separated ground and voltage supply for the oscillator part.

Table IV. Summary of Post-Simulation in Version I chip

Table V. Summary of Post-Simulation in Version II chip

Required Postsim (TT) Corner(1.8V)

Para. Value unit 1.7V 1.8V 1.9V SS TT FF

DA amplitude >660 mV 546 660 970 470 660 1.0 V

Bandwidth 500 MHz 500 500 500 475 500 525

Side-lobe >20 dB 26 30 24 26 30 26

Frequency 4.35 GHz 4.4 4.35 4.3 4.4 4.35 4. 4

Template Vpp >800 mV 960 1200 1900 700 1.2V 1.7V

47

5.3 Layout of TX part and test block

Layout of this TX chip version one is shown in Fig. 36. The size of it is

about 1.4 mm^2. Layout of TX test pattern version two is shown in Fig. 37.

The size of it is about 2.1 mm×0.88 mm.

Fig. 36 Layout of TX.

Fig. 37 Layout of TX.

48

VI. Measurement Results

Two versions of transmitter test blocks have been fabricated in 0.18 µm

CMOS technology. Fig. 38 and Fig. 39 show the die photograph of two

chips. Both of chips have the active circuit area of 0.45 mm×1.2 mm for

transmitter part which is small for a whole transmitter. The whole circuit is

tested with 1.8 V supply. The second version chip was modified in some

blocks according to the analysis of the first version chip. And from the

measured wave forms, we can see some improvement of second chips.

49

Fig. 38 Die Photo of TX first version.

Fig. 39 Die Photo of TX second version.

50

6.1 First Version Transmitter measurement

Fig. 40 shows the measured output pulse wave form of the first version

transmitter. The input signals are two clocks of charge pump generated form

data timing generator DTG5334. The two clocks have 3 ns duration and

delayed by 3 ns.

From the measurement result of Fig. 40, we can see that the amplitude of

the pulse is over 300 mV, which is -6 dBm at 50 ohm load and meets our

target. The time domain pulse is symmetrical and the envelope is almost

triangular shaped. The width of the pulse is about 4.5 ns, which corresponds

to 460 MHz bandwidth in frequency domain. The slope of the pulse can be

tuned by changing the duration and delay of clocks and by the changing of

current source bias at charge pump. Here we adjust to an optimal value to let

the pulse has the best shape. Fig. 41 is the measured frequency domain

output of the pulse at PRF of 1 MHz. The spectrum has a sidelobe

suppression of about 20 dB.

Total current consumption is 17 mA for the transmitter and the drive

amplifier consumes 9 mA. The Ring oscillator consumes about 6 mA and

differential to single converter consumes 2 mA. The mixer does not

consume static DC power as we designed. For a whole transmitter, the

power consumption of 30.6 mA at this output power is acceptable for

impulse radar.

From the test, we find that the PRF of this transmitter can increase up to

51

100 MHz, thus makes it also capable of communication purpose application

using modulation of PPM or OOK. In this case we do not need the drive

amplifier and external power amplifier which are needed for radar

application. Table below summarizes the transmitter’s performances.

The comparison between the simulation and measurement is shown in

Table VI.

Fig. 40 Measured pulse time domain shape of first version chip.

52

Fig. 41 Measured pulse frequency spectrum of first version chip.

Table VI. Simulation and Measurement of first chip

Simulation Measurement

DA power 660 mV (0 dBm) 330~540 mV (-6 ~ -2 dBm)

Template amplitude 280 mv NA

Center frequency 4.3 GHz 4.3 GHz

Bandwidth 480 MHz 460 MHz

Power Consumption 30.6 mW 30.6 mW

Sidelobe rejection 27 dB 20 dB

53

6.2 Second Version Transmitter measurement

Fig. 42 shows the measured output pulse wave form of the second version

transmitter. The condition setup is same with the first version chip.

From the measurement result of Fig. 42, we can see that the amplitude of

the pulse is over 540 mV, which is -2 dBm at 50 ohm load and meets our

target. The time domain pulse is more symmetrical which means more

sidelobe suppression ability. The width of the pulse is about 4.5 ns, which

corresponds to 500 MHz bandwidth in frequency domain. From this time

domain figure we could see that it has improved amplitude and pulse shape

comparing with the first version chip.

The template amplitude is about 150 mV after the buffer, which

corresponding to over 500 mV of on chip template since buffer decrease the

amplitude of template a lot ( shown in Fig. 43).

Table VII below shows the simulation and measurement result of second

version TX chip. From the comparison with the simulation result and with

the Table VI, we could see the improvement in DA output amplitude by

nearly 4 dB and the pulse shape improvement by comparing the time domain

pulse shape and their FFT spectrum power density from Fig. 42 with Fig. 40.

54

Fig. 42 Measured DA output of second version TX chip with FFT spectrum.

Fig. 43 Template output of second version TX chip (with buffer).

55

Table VII. Simulation and Measurement of second chip

Simulation Measurement

DA power 0 dBm (670mV) > -2 dBm (540 mV)

Template amplitude 250 mv 170 mv

Center frequency 4. 3GHz 4.3 GHz

Bandwidth 480 MHz 500 MHz

Power Consumption 34 mW 36 mW (without buffer)

Sidelobe rejection 28 dB 22 dB

We use the second version chip to compare with other works, and we can

see that for the transmitter, this work has medium power consumption and

high amplitude. And above all, this transmitter proves best pulse shape

among all. The comparison is below, Table VIII.

Table VIII. Comparison of UWB transmitter

References Technology Amplitude Bandwidth Power

[20],2006 BiCMOS .18μm 200 mV 550 MHz 31.3 mW

[18],2005 CMOS 0.18μm 200 mV 528 MHz 2 mW

[15],2007 CMOS 0.18μm 640 mV 1.4 GHz 29.7 mW

This Work CMOS 0.18μm 540 mV 500 MHz 25.2 mW

56

VII. Conclusions

A “carrier based UWB” transmitter is designed after system level

discussion, comparison and analysis in Section II and III. Circuit blocks are

explained in detail in Section IV. The simulation and measurement result of

two version chips are shown in Section V and VI. From these works, we can

see that our output is what we expected although there are some differences.

The novelty of this work lies in two aspects. The first one is the system

architecture in Fig. 20. The other novelty is the design of this up-conversion

mixer shown in Fig. 23. Although the mixer can only be used in this typical

architecture, we have some invention indeed and which is proved by

simulation and measurement.

57

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