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can be observed in fl oating gate memory devices, with the
conductivity at a given gate–source bias voltage dependent
on the previous operation. [ 15 ] Charge carriers induced at
the semiconductor–dielectric interface by an external gate
voltage can be trapped into fl oating gates during a program
operation and released during an erase operation, resulting DOI: 10.1002/smll.201501382
Nano-fl oating gate memory (NFGM) devices are transistor-type memory devices that use nanostructured materials as charge trap sites. They have recently attracted a great deal of attention due to their excellent performance, capability for multilevel programming, and suitability as platforms for integrated circuits. Herein, novel NFGM devices have been fabricated using semiconducting cobalt ferrite (CoFe 2 O 4 ) nanoparticles (NPs) as charge trap sites and pentacene as a p -type semiconductor. Monodisperse CoFe 2 O 4 NPs with different diameters have been synthesized by thermal decomposition and embedded in NFGM devices. The particle size effects on the memory performance have been investigated in terms of energy levels and particle–particle interactions. CoFe 2 O 4 NP-based memory devices exhibit a large memory window (≈73.84 V), a high read current on/off ratio (read I on / I off ) of ≈2.98 × 10 3 , and excellent data retention. Fast switching behaviors are observed due to the exceptional charge trapping/release capability of CoFe 2 O 4 NPs surrounded by the oleate layer, which acts as an alternative tunneling dielectric layer and simplifi es the device fabrication process. Furthermore, the NFGM devices show excellent thermal stability, and fl exible memory devices fabricated on plastic substrates exhibit remarkable mechanical and electrical stability. This study demonstrates a viable means of fabricating highly fl exible, high-performance organic memory devices.
Organic Memory
J. H. Jung, Prof. J. H. Oh Department of Chemical Engineering Pohang University of Science and Technology (POSTECH) Pohang , Gyeongbuk 790-784 , Korea E-mail: [email protected]
S. Kim, H. Kim, Prof. J. Park School of Energy and Chemical Engineering Ulsan National Institute of Science and Technology (UNIST) Ulsan 689-798 , Korea E-mail: [email protected]
1. Introduction
Conventional fl ash memory devices based on inorganic mate-
rials are typically produced on a limited number of rigid
considerable charge carriers forming drain current in the
active layer can be trapped in nano-fl oating gates. [ 15 ]
The energy levels of the NPs were estimated from cyclic
voltammograms (CVs) and UV–vis absorption spectra. These
data provided a means of determining the charge trapping
and release mechanism of the NFGM devices and effects of
NP size on the electrical memory characteristics. The energy
level of the valence band of CoFe 2 O 4 NP was obtained from
the cyclic voltammetric data shown in Figure S3 (Supporting
Information). The energy bandgap was determined from a
plot of the modifi ed Kubelka–Munk function as a function of
the energy of exciting light derived from the UV–vis absorp-
tion spectra (Figure S4, Supporting Information). [ 47 ] The
energy band diagrams of pentacene [ 48,49 ] and the various sizes
of CoFe 2 O 4 NPs are shown in Figure 4 a. The energy levels
of CoFe 2 O 4 NPs derived from electrochemical/photochem-
ical measurements are summarized in Table S1 (Supporting
Information). As the diameter of the NPs increased from 5 to
11 nm, the energy level of the valence band increased gradu-
ally from −6.56 to −6.52 eV, while that of the conduction band
decreased from −3.80 to −3.94 eV. Concurrently, the energy
bandgap decreased from 2.76 to 2.58 eV. Schematic energy
band diagrams for program/erase (P/E) operations and charge
trapping/release mechanisms are shown in Figure 4 b. During a
program operation (at V GS = 60 V), electrons at the semicon-
ductor–dielectric interface can be transferred by the strong
electric fi eld from the lowest unoccupied
molecular orbital (LUMO) of pentacene
to the conduction band of CoFe 2 O 4 NPs
by passing through the thin oleate layer
(≈2 nm). As a result, negatively charged
NPs generated by the accumulation of
electrons can induce a negative internal
electric fi eld. This leads to accumulation of
holes in the channel region and a positive
threshold voltage shift, which maintains a
high conductance state during the subse-
quent read on operation (at V GS = 0 V).
Conversely, during an erase operation (at
V GS = −60 V), a negative threshold voltage
shift is induced by the release of electrons
from the NPs or by recombination with
holes transported by the strong negative
external electric fi eld, which results in a
low conductance state during the read off
operation (at V GS = 0 V).
Although the charge carriers that contribute directly to
the drain current of p -type pentacene active layer are holes,
the fl oating gate architecture allows trapped negative charge
carriers (electrons) to also affect output current. In addi-
tion, the energy barrier for electron transport between the
LUMO of pentacene and the conduction band of CoFe 2 O 4
NP is lower than that for hole transport between the highest
occupied molecular orbital (HOMO) of pentacene and the
valence band of CoFe 2 O 4 NPs.
As summarized in Table 1 , the memory window
(73.84 ± 6.34 V) of NFGM devices based on 8 nm CoFe 2 O 4
NPs was slightly larger than that of 5 nm NP-based ones
(68.27 ± 2.77 V). NFGM devices based on 11 nm CoFe 2 O 4
NPs had the smallest memory window of 62.51 ± 7.16 V,
although they were expected to exhibit the largest memory
window based on their relative energy levels compared to
those of the 5 or 8 nm CoFe 2 O 4 NPs. This is most likely due to
the formation of irregular aggregates of 11 nm CoFe 2 O 4 NPs.
Atomic force microscopy (AFM) phase images indicated that
5 and 8 nm CoFe 2 O 4 NPs on Si/SiO 2 wafers (Figure S5, Sup-
porting Information) were relatively uniformly dispersed.
In contrast, the 11 nm CoFe 2 O 4 NPs formed close-packed
aggregates. This aggregation was confi rmed on TEM images
(Figure 1 e,f). This aggregation likely prevents the uniform
deposition of pentacene during thermal evaporation, thereby
hindering charge trapping and release, resulting in a smaller
small 2015, DOI: 10.1002/smll.201501382
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-ID (
A)
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-ID (
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erase program
a) b)
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10-10
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(V)
erase program
c)
Figure 3. Transfer curves of the NFGM devices based on a) 5, b) 8, and c) 11 nm CoFe 2 O 4 NPs at V DS = −30 V.
Figure 2. A schematic confi guration of the NFGM devices based on CoFe 2 O 4 NPs with cross-sectional bright-fi eld (BF) and high-angle annular dark fi eld (HAADF) scanning transmission electron microscopy (STEM) images (left inset), and a TEM image of 8 nm CoFe 2 O 4 NPs (right inset).
memory window and decreased charge mobility. The aggrega-
tion of 11 nm CoFe 2 O 4 NPs may be attributed to the stronger
coercivity and van der Waals interactions among the larger
NPs. [ 50,51 ] It has been experimentally verifi ed that van der
Waals forces increase with the size of CoFe 2 O 4 NPs because
of permanent dipole moments in their spinel structures. [ 52 ]
The inverse spinel structure of CoFe 2 O 4 NPs was confi rmed
in X-ray patterns (Figure S6, Supporting Information, XRD).
Among the devices tested, the best electrical memory
performance was observed from NFGM devices based on
8 nm CoFe 2 O 4 NPs. Therefore, these devices were selected
for further characterization. The typical output curves of
8 nm CoFe 2 O 4 NP-embedded NFGM devices are shown in
Figure 5 a. The drain current ( I D ) responses for the repeated
pulse bias of P/E operations were investigated to measure
memory switching speed and electrical stability (Figure 5 b).
Gate voltages of 60, 0, −60, and 0 V were sequentially and
repeatedly applied for program, read on, erase, read off oper-
ation, respectively. This switching cycle is usually called as
write-read-erase-read (WRER) cycle. As shown in Figure 5 b,c,
fast and stable switching I D responses with the value of read
I on / I off above 10 3 was maintained over 1000 WRER cycles.
In addition, data storage capability estimated from data
retention test is one of the important factors in nonvolatile
memory devices. A read I on / I off (at V GS = 0 V) of ≈1.62 × 10 3
was maintained over 1000 s as well (Figure 5 d).
To investigate the effects of P/E operation bias volt-
ages on memory performance, the gate–source voltage was
gradually increased from ±10 to ±60 V at intervals of 10 V, as
shown in Figure S7 (Supporting Information). The results are
summarized in Table S2 (Supporting Information). Both the
memory window and read I on / I off remained low and constant
from ±10 to ±30 V, but started to increase above ±30 V. These
observations indicated that the CoFe 2 O 4 NPs start to behave
as charge trap sites above ±30 V. The memory window and
read I on / I off of these devices increased to ≈76.79 V and
≈2.72 × 10 3 , respectively, at ±60 V.
The following equation can be used to estimate the
charge carrier storage capacity of 8 nm CoFe 2 O 4 NPs: [ 53 ]
n V Cet iΔ = Δ
(1)
where Δ n is the amount of transferred charge carriers, C i is the capacitance of the blocking dielectric layer, and e is
the elementary charge. Equation ( 1) indicates that ca. 1.57
× 10 13 charge carriers are expected to be transferred. The
deposition density of the 8 nm CoFe 2 O 4 NPs in the NFGM
devices is ≈8.29 × 10 11 cm −2 based on AFM phase images
of NPs on OTS-treated Si/SiO 2 wafers. These data indicate
that approximately 18 charge carriers were trapped in each
CoFe 2 O 4 NP. It is noteworthy that the charge trapping capa-
bility of the CoFe 2 O 4 NPs is comparable to that of Au NPs
without the aid of additional tunneling dielectric or self-
assembled monolayer (SAM) treatments on the dielectric
layer. [ 6,20,24 ]
The thermal stability of the memory devices has also been
investigated for the practical application in electronic appli-
ances. The NFGM devices showed thermally and electrically
stable behaviors in repeating P/E cycles and data retention
test at 100 °C (Figure S8, Supporting Information). In addi-
tion, it is notable that not only charge carrier mobility but
also I D increases as the temperature of the memory device
small 2015, DOI: 10.1002/smll.201501382
Table 1. Electrical memory characteristics of the NFGM devices based on CoFe 2 O 4 NPs in various sizes and pentacene-based OTFTs.
Size of NPs [nm]
μ avg, initial [cm 2 V −1 s −1 ]
μ max, initial [cm 2 V −1 s −1 ]
V t, initial [V]
V t, program [V]
V t, erase [V]
Δ V t [V]
Read I on [−A]
Read I off [−A]
Read I on / I off
5 2.33 × 10 −3
(±1.95 × 10 −3 )
2.61 × 10 −3
(±1.92 × 10 −3 )
4.53
(±8.13)
32.46
(±1.78)
−35.82
(±2.09)
68.27
(±2.77)
8.60 × 10 −7
(±7.52 × 10 −7 )
1.64 × 10 −10
(±3.06 × 10 −11 )
5.13 × 10 3
(±3.86 × 10 3 )
8 1.96 × 10 −3
(±6.81 × 10 −4 )
2.24 × 10 −3
(±8.44 × 10 −4 )
−3.38
(±5.39)
31.63
(±4.25)
−42.21
(±3.48)
73.84
(±6.34)
5.97 × 10 −7
(±4.08 × 10 −7 )
2.28 × 10 −10
(±1.07 × 10 −10 )
2.98 × 10 3
(±5.29 × 10 2 )
11 1.04 × 10 −3
(±3.05 × 10 −4 )
1.18 × 10 −3
(±2.56 × 10 −4 )
−6.18
(±3.65)
30.52
(±3.16)
−31.99
(±4.05)
62.51
(±7.16)
4.49 × 10 −7
(±1.61 × 10 −7 )
3.27 × 10 −10
(±8.87 × 10 −11 )
1.35 × 10 3
(±1.99 × 10 2 )
No NPs 5.17 × 10 −1
(±1.12 × 10 −1 )
5.21 × 10 −1
(±1.11 × 10 −1 )
−20.75
(±4.67)
−24.91
(±2.05)
−32.51
(±2.26)
7.60
(±1.13)
1.32 × 10 −10
(±1.12 × 10 −11 )
2.25 × 10 −10
(±7.48 × 10 −11 )
6.21 × 10 −1
(±1.24 × 10 −1 )
Figure 4. a) Energy band diagrams of pentacene and CoFe 2 O 4 NPs in different sizes and b) a schematic energy band diagrams during program (left) and erase operations (right) for the charge trapping/release mechanism description.
rises, which can be attributable to the facilitated charge hop-
ping. [ 54 ] The mechanism can be expressed as: [ 55–58 ]
exp2
I Sqa n vqa V
dkTqkTD m e f
m t= − ∅⎛⎝⎜
⎞⎠⎟
⎡⎣⎢
⎤⎦⎥
(2)
where S is the contact area, d is assumed to be the fi lm thick-
ness, q is the electronic charge, V is the applied bias, a m is the
mean hopping distance, n e is the density of space charge, v f is
the intrinsic vibration frequency, and k is Boltzmann’s con-
stant. Thermally excited electrons in pentacene layer can hop
from one trap state to another over barrier height between
the localized sites. In addition to hopping mechanism, carrier
mobility may be increased as the interconnectivity between
pentacene grains is improved as the substrate temperature
increases, leading to the reduced number of traps at the grain
boundaries under a given channel length. [ 59 ] Furthermore,
hysteresis can be enhanced as the temperature increases due
to the fl uctuation in the number of trapped charges resulting
from the change in the values of q∅ t and a m , which are
affected by the gate voltage. [ 60 ]
2.2. Effects of an Additional Tunneling Dielectric Layer on Memory Characteristics
The outstanding electrical memory characteristics of
CoFe 2 O 4 NP-based NFGM devices in the absence of a tun-
neling dielectric layer may be attributed to the exceptional
charge trapping and release capability of oleate-capped
(≈2 nm) CoFe 2 O 4 NPs. A coating consisting of a SAM of
alkyl chains can act as an alternative tunneling dielectric layer
due to the insulating nature of hydro-
carbon chains. [ 15 ] In conventional NFGM
devices, a tunneling dielectric layer is usu-
ally prepared at high temperatures and
under high vacuum over a long period.
This step is considered vital for charge car-
rier storage in NPs, which is required for
data retention. In addition, optimization of
the thickness of the tunneling layer, which
separates charge trap sites from the semi-
conducting layer, is important to achieve
a balance between data retention and
P/E speed. [ 22 ] A thick tunneling dielectric
layer can degrade P/E speed and increase
power consumption. [ 18 ] Conversely, a thin
layer can enhance the P/E operation speed
but an excessively thin layer can limit
the number of P/E cycles and/or result
in charge loss or leakage current through
defects in the layer. [ 61 ]
To verify the effects of an additional
tunneling dielectric layer in our memory
devices, 10 nm thick Al 2 O 3 thin fi lm was
deposited by atomic layer deposition (ALD)
between the CoFe 2 O 4 NPs and the penta-
cene layer. Al 2 O 3 is widely used as an insu-
lator in various electronic devices because of
its high electrical breakdown fi eld, high dielectric constant, and
large bandgap. [ 62 ] In addition, ALD methods have simple and
accurate thickness control, resulting in dense and pinhole-free
thin fi lms with excellent thickness uniformity over large areas. [ 63 ]
The electrical memory characteristics of 8 nm CoFe 2 O 4
NP-based NFGM devices with and without the Al 2 O 3 tun-
neling dielectric layer are summarized in Table S3 (Supporting
Information). Although the integration of the Al 2 O 3 layer
enhanced several parameters, including charge mobility and
read I on / I off by isolating the NPs from pentacene (Table S4,
Supporting Information), the memory window was reduced
from ≈73.84 to ≈59.72 V. These results indicate that the addi-
tional Al 2 O 3 tunneling dielectric layer disrupts the transfer of
charge carriers into the CoFe 2 O 4 NPs and the oleate layer is a
suffi cient tunneling layer in our NFGM devices.
2.3. Electrical Memory Characteristics of Flexible NFGM Devices
The CoFe 2 O 4 NP-embedded NFGM devices were prepared
on polyethylene terephthalate (PET) fi lms to demonstrate
the low voltage operation and the feasibility of fabricating
fl exible organic memory devices since they are essential
prerequisites for the practical application in fl exible devices.
Most of the organic NFGM devices reported so far required
gate voltages of at least ±30 V for effi cient fi eld-effect mod-
ulation and maximization of the charge trap in NPs [ 12,53,64 ]
and a small memory window less than 20 V was often
obtained at higher P/E operation voltage in fl exible NFGM
devices. [ 6,22 ] Al 2 O 3 dielectric layer (≈100 nm) was subse-
quently deposited using radio-frequency (RF) sputtering.
small 2015, DOI: 10.1002/smll.201501382
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(V)
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read on
read off Ion
Ioff -250
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50
100
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S (V)
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erased state
-ID (
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10-8
10-7
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-ID (
A)
Time (s)
erased state
programmed state
a) b)
c) d)
Figure 5. Electrical memory characteristics of programmable 8 nm CoFe 2 O 4 NP-based NFGM devices: a) Output curves, b) drain current response for P/E cycles, c) electrical endurance for 1000 P/E repeating cycles, and d) data retention test.
The CoFe 2 O 4 NPs and pentacene layer were deposited con-
secutively, followed by the formation of gold source–drain
electrodes. Figure 6 shows a schematic, photograph, and
electrical memory characteristics of the resulting fl exible
NFGM devices. Despite the risks of current leakage and
performance degradation due to the high surface rough-
ness and temperature susceptibility of the PET substrate,
the fl exible NFGM devices exhibited excellent electrical
memory performance with a large memory window of over
32 V, even after 700 P/E cycles in low gate–source voltage
sweep between −20 and +20 V (Figure 6 c,d, and Figure S9a,
Supporting Information). The mechanical stability of the
CoFe 2 O 4 NP-based NFGM devices was tested by measuring
electrical memory performance after repeated bending
cycles. The tensile strain at the top surface ( ε top ) of the fl ex-
ible memory devices can be calculated from the following
equation for a simple bending: [ 65 ]
1 2
2 1 1 2top
F S2
sD D
RD
Rε
η χηη χη( )
( )( )( )
=+ + +
+ +≈ (3)
where η = D F / D S and χ = Y F / Y S . R is the bending radius, D is
the thickness and Y F and Y S are the Young’s modulus of the
thin-fi lm (F) and substrate (S), respectively. ε top can be simply
calculated as D S /2 R .
As shown in Figure 6 e and Figure S9b (Supporting Infor-
mation), the memory window was retained above 26 V over
500 bending cycles with minimal electrical degradation during
gate–source voltage sweeps between −20 V and +20 V against
a tensile strain of ≈0.54%. This strain was induced by a bending
radius of 7 mm, indicating that these devices have high poten-
tial for use in fl exible or stretchable electronic devices. Con-
versely, a memory window smaller than 2 V was observed with
fl exible devices prepared without CoFe 2 O 4 NPs (Figure S9c,
Supporting Information). This confi rmed that the CoFe 2 O 4
NPs acted as charge trap sites for memory performance.
3. Conclusion
High-performance fl exible organic NFGM devices were
fabricated using pentacene and CoFe 2 O 4 NPs as the semi-
conductor and charge trapping agent, respectively. Monodis-
perse CoFe 2 O 4 NPs with three different diameters (5, 8, and
11 nm) were synthesized by a simple thermal decomposition
method starting from a low-cost and non-toxic metal–oleate
complex precursor. NFGM
devices based on 8 nm CoFe 2 O 4
NPs exhibited the best electrical
memory performance due to
favorable energy levels and uni-
form dispersion on the substrate.
These factors resulted in a large
memory window of ≈73.84 V,
fast and reversible switching
behavior, a high read I on / I off of
≈2.98 × 10 3 , and outstanding
data retention, facilitated by an
oleate capping layer that acted
as an alternative tunneling die-
lectric layer. It is noteworthy
that the electrical memory per-
formance of the NFGM devices
based on CoFe 2 O 4 NPs was
comparable to that of Au NP-
embedded ones. Furthermore,
the NFGM devices were electri-
cally and mechanically stable on
fl exible PET substrates at low
operation voltage and retained
a memory window over 32 and
26 V with little electrical degra-
dation after 700 P/E cycles and
500 bending cycles, respectively.
Solution-processed, monodis-
perse CoFe 2 O 4 NPs allowed
simple and cost-effective depo-
sition of nano-fl oating gates
with controllable size and den-
sity, which has been challenging
in the fabrication processes of
NFGM devices.
small 2015, DOI: 10.1002/smll.201501382
a) b)
c) d)
e)
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program erase
0 100 200 300 400 500-20
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0
10
20
programmed state
Vt
bending cycles
erased state
0 200 400 600 800-20
-10
0
10
20
programmed state
Vt
P/E cycles
erased state
Figure 6. a) A schematic image, b) photograph, c) transfer curves (at V DS = −20 V), d) electrical, and e) mechanical stability test of the fl exible NFGM devices based on 8 nm CoFe 2 O 4 NPs on PET substrate.
In addition, the oleate capping layer signifi cantly simpli-
fi ed the fabrication process by eliminating the need for an
additional tunneling dielectric layer. Our fi ndings demon-
strate that sophisticated control of methodologies when syn-
thesizing semiconducting or metal oxide NPs can yield novel
charge trapping agents for memory devices and open up new
possibilities for the simple and low-cost fabrication of high-
performance data storage devices.
4. Experimental Section
Synthesis of (Co 2+ Fe 2 3+ )–Oleate Precursor : FeCl 3 ·6H 2 O (8.64 g, 32 mmol), CoCl 2 ·6H 2 O (3.808 g, 16 mmol), and sodium oleate (38.96 g, 128 mmol) were dissolved in a mixture of 80 mL of ethanol, 80 mL of D. I. water, and 160 mL of n -hexane. The solution was stirred until all the reagents were dissolved com-pletely. Then, the solution was refl uxed at 60 °C for 4 h. The reacted (Co 2+ Fe 2 3+ )–oleate was washed three times with 120 mL of D. I. water and residual solvent was evaporated in the rotary evaporator at 80 °C.
Synthesis of 8 nm CoFe 2 O 4 NPs : (Co 2+ Fe 2 3+ )–oleate complex (2.5 g), OLA (0.25 g), and octadecene (10 mL) were mixed and evacuated at 80 °C for 1 h. The mixture was stirred with Ar bub-bling at rising temperature. After 30 min, the mixture was heated to 310 °C at a heating rate of 1 °C min −1 and maintained at this temperature for 1 h. The reacted solution was cooled to room temperature and washed three times with acetone/ethanol mix-ture. Finally, the purifi ed CoFe 2 O 4 NPs were dispersed in 10 mL of n -hexane for long-term storage.
CoFe 2 O 4 NPs in different sizes can be synthesized by the same procedures, except for the Ar bubbling fl ow rate, which optimizes the NP size. 5 nm CoFe 2 O 4 NPs were synthesized under vigorous Ar bubbling. Reversely, 11 nm ones were synthesized when Ar bub-bling was stopped before the solution was heated.
NFGM Device Fabrication : CoFe 2 O 4 NP solution (2 mg mL −1 ) was spin-coated at 1000 rpm for 60 s on the OTS-treated Si/SiO 2 wafer (D. I. water contact angle: ≈107° (Figure S10, Supporting Informa-tion)) [ 66,67 ] and annealed at 60 °C for 3 h in the vacuum oven to evaporate the solvent thoroughly. 50 nm thick pentacene was ther-mally deposited on the surface of NPs at a rate of 0.01–0.03 nm s −1 at 60 °C (substrate temperature) under a pressure of 5.0 × 10 −6 Torr. Gold source–drain electrodes (40 nm) were also thermally depos-ited in the evaporation chamber at room temperature using shadow masks with 50 µm of channel length (L) and 1000 µm of channel width (W). For the fl exible NFGM device fabrication, 100 nm thick Al 2 O 3 gate dielectric layer was deposited on the PET substrate by RF sputtering technique after the gate electrode (Cr (5 nm)/Au (100 nm)) was formed by thermal evaporation. The other processes are the same as those in the fabrication on the Si wafer as described above. Additional tunneling dielectric layer, 10 nm Al 2 O 3 thin fi lm was deposited by ALD at a substrate temperature of 150 °C.
Energy Level Measurement : All the cyclic voltammetry (CV) measurements were performed in 0.1 m of tetabutylammonium hexafl uorophosphate (Bu 4 NPF 6 ) in anhydrous acetonitrile elec-trolyte at room temperature at a scan rate of 100 mV s −1 under N 2 gas blowing for the estimation of the valence band energy level of the CoFe 2 O 4 NPs. CoFe 2 O 4 NP solution was deposited on indium tin oxide (ITO) glass and used as a working electrode.
The counter electrode and the reference electrode were platinum (Pt) wire and Ag/Ag + electrode containing 0.01 m of AgNO 3 with 0.1 m of tetrabutyl ammonium perchlorate (TBAP) in acetonitrile, respectively. The Ag/Ag + reference electrode was internally cali-brated by ferrocene/ferrocenium couple (Fc/Fc + ) and the valence band energy level of NPs can be estimated using:
E E EeV 4.8valenceband ox
onsetferrocene
onset( ) = − − +⎡⎣
⎤⎦( ) ( )
(4)
For the estimation of the energy bandgap of CoFe 2 O 4 NPs, both NP solution and spin- coated samples were measured using double-beam mode. The sample for the solution-based UV–vis absorption spectrum was prepared by diluting 100 µL of extracted 5, 8, and 11 nm CoFe 2 O 4 NP solution in 3 mL of n -hexane. For the spin-coated samples, UV–vis absorption spectra can be obtained by similar procedures except the quartz cuvette was replaced with quartz plate which was spin-coated at 1000 rpm using of CoFe 2 O 4 NP solution (10 mg mL −1 ) before loaded on the sample holder.
Instruments for Characterization : All the electrical perfor-mances of the NFGM devices were measured in an N 2 -fi lled glove box using a Keithley 4200 semiconductor parametric analyzer.
The size and shape of NPs were characterized using transmis-sion electron microscopy (TEM; JEM-2100, JEOL) operated at 200 kV. Specimens for TEM were prepared by conventional methods, drop-ping the diluted CoFe 2 O 4 NP solution onto the copper grid. Inverse spinel structure of NPs was characterized using X-ray diffraction (Figure S6, Supporting Information, XRD; Bruker, Germany). Rotating anode was used as X-ray source, and the measurement was oper-ated at 220 V. The sample was prepared in the form of solid powder.
For the surface analysis of the NFGM devices, tapping-mode atomic force microscope (AFM; Veeco (USA)) was used and the sample for cross-sectional STEM analysis was prepared using dual-beam focused ion beam (FIB, Helios 450 HP, FEI, USA) on the copper grid and analyzed with high-resolution transmission elec-tron microscope (HR-TEM, Cs-corrected JEM-2100F, JEOL, Japan). The bandgaps of CoFe 2 O 4 NPs were measured using UV-1800 (Shi-madzu Corp.) and VARIAN CARY 100 (Agilent Tech).
Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.
Acknowledgements
This work was supported by the Center for Advanced Soft Electronics under the Global Frontier Research Program (2013M3A6A5073175), the National Research Foundation of Korea (2014R1A2A2A01007467) of the Ministry of Science, ICT & Future Planning, Korea, and the New & Renewable Energy Core Technology Program (20133030000180) of the Korea Institute of Energy Tech-nology Evaluation and Planning (KETEP), granted fi nancial resource from the Ministry of Trade, Industry & Energy, Korea. J.H.J. acknowl-edges Moo Yeol Lee for his help in drawing 3D illustrations.
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