Shift Register

CENT-113 Digital Electronics1

Shift Registers

Socketed 74LS164 8-Bit Shift Register Chip


Interest

• Optical micrograph of the InGaAs 4x4 Shift Register. The 4x4 Shift Register contain 16 pixel on a 2mmx1mm chip. Each pixel contain 2 differential Input, 2 differential Output and 2 Solder bumps. All differential Input/Output contain 2 circular SEED devices (MQW-pin diode), with a 20µm diameter optical window, working as reflection mode SEED. The SEED device spacing is 33µm/66µm. The Input/Output pitch is 100µmx200µm. The overall pixel pitch is 400µmx400µm. The solder bump height is 12µm.

• This array is used in the 16-channels optoelectronic bitonic sorter.


Review• Monostable Multivibrater chips.


Shift Registers• A shift register is a register in which the contents

may be shifted one or more places to the left or right. This type of register is capable of performing a variety of functions. It may be used for serial-to-parallel conversion and for scaling binary numbers.


Shift Registers Characteristics1. It is a temporary memory and holds the

numbers on display.2. It shifts the number to the to the left on the

display each time a new digit is pressed on the keyboard.

• Calculator Example:– Press & release 1 on keyboard & 1 displayed right.– Press & release 1 on keyboard & 1 displayed right,

11 displayed.– Press & release 3 on keyboard & 3 displayed right,

113 displayed.


Digital System Using Shift RegistersInput

Keyboard

7 8 9

1

4 5 6

2 3

0

Encoder ShiftRegister Decoder

OutputDisplay

•4-bit serial load shift register

ShiftRegister

ProcessingUnit

D Q

CLK

CLRFF A

D Q

CLK

CLRFF A

D Q

CLK

CLRFF A

D Q

CLK

CLRFF A

Line#

Inputs Outputs

Clear Data ClockPulse#

FF A FF B FF C FF D

A B C D

1 0 0 0 0 0 0 0

2 1 1 0 0 0 0 0

3 1 1 1 1 0 0 0

4 1 1 2 1 1 0 0

5 1 1 3 1 1 1 0

6 1 0 4 0 1 1 1

7 1 0 5 0 0 1 1

8 1 0 6 0 0 0 1

9 1 0 7 0 0 0 0

10 1 0 8 0 0 0 0

11 1 1 9 1 0 0 0

12 1 0 10 0 1 0 0

13 1 0 11 0 0 1 0

14 1 0 12 0 0 0 1

15 1 0 13 0 0 0 0

A B C D

DataInput

ClockClear

CENT-113 Digital Electronics

Storage RegisterGroup of storage elements read/written as a unit

4-bit register constructed from 4 D FFsShared clock and clear lines

TTL 74171 Quad D-type FF with Clear

Schematic Shape

Q1

CLR

D3D2D1D0

171

Q1

Q0Q0

CLK Q3Q3Q2Q2

11

109

5

67

43

2

14

13

151

12


Register Classifications

MSB LSB

• Where bits come in & go out:– Serial in-serial out.

– Parallel in-serial out.

– Serial in- parallel out.

– Parallel in-parallel out.

MSB LSB


Serial & Parallel Transfers & Conversion • SERIAL TRANSFER means that the data is

moved along a single line one bit at a time. A control pulse is required to move each bit.

• PARALLEL TRANSFER means that each bit of data is moved on its own line and that all bits transfer simultaneously as they did in the parallel register. A single control pulse is required to move all bits.


Serial in - Parallel out Register• Disable the clock to access parallel data.• Count incoming bits to know when register is full.


Parallel in - Parallel out Register• The new input values will be seen at the output at

the next clock transition.


Parallel in - Parallel out Register ...


Parallel in - Parallel out Register• We have now added logic to allow current data

to be retained (by feedback from flip flop output) or new data to be loaded from external inputs.

• Control mode of operation via “Load” switch:– Load = 1 means load new data;– Load = 0 means retain existing data.

• Clock now runs freely without skew or switching.

• i.e. 74195.


Parallel in - Serial out Register


Parallel in - Serial out Register ...• The structure is similar to the parallel in/out circuit,

but now the output from Q0 is fed to input of Q1, output Q1 to input Q2, and so on.

• Load/Shift control retained to determine which phase of the operation is being done: parallel load or serial output. The parallel load operation is used to set up the data initially. Then we switch to a ‘serial out’ mode where the the data are sent out serially.

• i.e. 74165.


Bidirectional Shift Register


Bidirectional Shift Register ...• This is a serial in serial out register than can

either shift left or shift right.• The mode of operation is determined by the the

Right/Left control line. • Clearly more economical than separate left shift

and right shift devices. (But only, of course, if we need both operations.)

• The FFs act as a four-element queue, but we can do some permutation of the data by being able, in effect, to swap the head and tail of the queue.


Serial and Parallel Transfers • The four-bit word 1101

is being transferred to a storage device.

• One control pulse will cause the entire word to be stored .

• Serial transfer takes more time.


Serial and Parallel Conversion • Serial-to-parallel

conversion or parallel-to-serial conversion describes the manner in which data is stored in a storage device and the manner in which that data is removed from the storage device.


Scaling • SCALING means to change the magnitude of a

number. Shifting binary numbers to the left increases their value, and shifting to the right decreases their value. The increase or decrease in value is based on powers of 2.

• A shift of one place to the left increases the value by a power of 2, which in effect is multiplying the number by 2. To demonstrate this, let's assume that the following block diagram is a 5-bit shift register containing the binary number 01100.


4-bit Shift Register • This register is capable of left shifts only.• Before any operation takes place, a CLEAR

pulse is applied to the RESET terminal of each FF to ensure that the Q output is LOW.


Parallel-to-serial conversion timing


4-bit Shift Register Operation• At CP1, a CLEAR pulse is applied to all the FFs, resetting the

register to a count of 0. The number 01012 is applied to the parallel inputs at CP2, causing FF1 and FF3 to set. At this point, the J inputs of FF2 and FF4 are HIGH. AND gate 2 has a LOW output since the FF4 output is LOW. This LOW output represents the first digit of the number 01012 to be output in serial form. At the same time we have HIGHs on the K inputs of FF1 and FF3. (Notice the NOT symbol on FF1 at input K. With no serial input to AND gate 1, the output is LOW; therefore, the K input to FF1 is held HIGH). With these conditions CP3 causes FF1 and FF3 to reset and FF2 and FF4 to set. The HIGH output of FF4, along with CP3, causes AND gate 2 to output a HIGH. This represents the second digit of the number 01012.


4-bit Shift Register Operation Cont.• At CP4, FF2 and FF4 reset, and FF3 sets. FF1 remains

reset because of the HIGH at the K input. The output of AND gate 2 goes LOW because the output of FF4 is LOW and the third digit of the number is output on the serial line. CP5 causes FF4 to set and FF3 to reset. CP5 and the HIGH from FF4 cause AND gate 2 to output the last digit of the number on the serial line. It took a total of four CLK pulses to input the number in parallel and output it in serial. CP6 causes FF4 to reset and effectively clears the register for the next parallel input. Between CP7 and CP10, the number 11102 is input as parallel data and output as serial data.


Serial-to-parallel conversion timing


4-bit Shift Register Operation• A CLEAR pulse resets all the FFs at CP1. At CP2, the

most significant bit of the data is input to AND gate 1. This HIGH along with the clock pulse causes AND gate 1 to output a HIGH. The HIGH from the AND gate and the clock pulse applied to FF1 cause the FF to set. FFs 2, 3, and 4 are held reset. At this point, the MSD of the data has been shifted into the register.

• The next bit of data is a 0. The output of AND gate 1 is LOW. Because of the inverter on the K input of FF1, the FF senses a HIGH at that input and resets. At the same time this is occurring, the HIGH on the J input of FF2 (from FF1) and the CLK cause FF2 to set. The two MSDs, 1 and 0, are now in the register.


4-bit Shift Register Operation Cont.• CP4 causes FF3 to set and FF2 to reset. FF1 is

set by the CLK pulse and the third bit of the number. The register now contains 01012, as a result of shifting the first three bits of data. The remaining bit is shifted into the register by CP5. FF1 remains set, FF2 sets, FF3 resets, and FF4 sets. At this point, the serial transfer is complete. The binary word can be sampled on the parallel output lines. Once the parallel data is transferred, a CLEAR pulse resets the FFs (CP6), and the register is ready to input the next word.


Scaling Operation• The number to be scaled is loaded into the

register either in serial or parallel form. Once the data is in the register, the scaling takes place in the same manner as that for shifting the data for serial output. A single clock pulse will cause each bit of data to shift one place to the left. Remember that each shift is the equivalent of increasing the value by a power of 2. The scaled data is read from the parallel outputs. Care must be taken not to overshift the data to the point that the MSDs are shifted out of the register.


Universal Shift Register• 74194 4-bit bidirectional shift register.• Serial Inputs: LSI, RSI• Parallel Inputs: D, C, B, A• Parallel Outputs: QD, QC, QB, QA• Clear Signal• Positive Edge Triggered Devices• S1,S0 determine the shift function

– S1 = 1, S0 = 1: Load on rising CLK edge, synchronous load

– S1 = 1, S0 = 0: shift left on rising CLK edge

• LSI replaces element D• S1 = 0, S0 = 1: shift right on rising CLK

edge• RSI replaces element A• S1 = 0, S0 = 0: hold state• Multiplexing logic on input to each FF.


Questions• Q. What are the two control lines to access four

separate functions in the universal shift register?• A.

load Parallel11rightShift 01leftShift 10dataRetain 00

SSOperationcontrolMode

01


Universal Shift Register Truth Table

• See EWB 74194 ...


Universal Shift Register Schematic

3210

S0S1

Inputmode

control

MUX

Parallel data in

Output

74174


Universal Shift Register Operation• 74194 used in a stepper motor driver


Sample Shifter Application • Communicating between a terminal & a computer over

phone lines, the terminal expects data to appear in a byte-wide parallel form, but the data must be sent over the line in bit-serial form.

• Shift registers convert between parallel and serial formats. Hardware is designed to load the data from the computer in parallel and shift it out serially over the communications link.

• On the return trip, serial data from the terminal is captured by the shift register, bit by bit, and presented to the computer via the shift register's parallel outputs.


Sample Shifter Application Schematic Parallel to serial

conversion

ParallelInput

ParallelOutput

SerialConversion


8 Bit Shift Register


Shift Register Operation • The system is receiving the data bits in serial form, and

that it generates the parity bit continuously for the most recent 8 data bits. To accomplish this, the incoming serial data stream must first be converted into a parallel input vector for the parity generator. We will use a shift register for this task.

• A N-bit shift register consists of N D flip-flops (DFF) connected in cascade. At each clock cycle the input of one DFF will be transferred to the input of the next DFF in the register. If the inputs of each DFF are made available, this structure can be used as a serial input- parallel output structure.


Questions• Q. What are devices that use shift registers?• A. Calculators, computers.


Registers Input/Output Variations

74377 Octal D-type FFswith input enable

74374 Octal D-type FFswith output enable

EN enabled low andlo-to-hi clock transitionto load new data into

register

OE asserted lowpresents FF state to

output pins; otherwisehigh impedence

D3

D6Q5

Q2

377

Q1Q0

Q3

EN CLK

Q6

Q4

Q7

D5

D2D1D0

D4

D7

1

3478

13141718

11

256912151619

HGFEDCBA

QHQGQFQEQDQCQBQA

OE

37411

1

3478

13141718

256912151619

CLK


74670 RegisterTwo dimensional array of flip-flops

Address used as index to a particular wordWord contents read or written

4x4 Register File withTri-state Outputs

Separate Read and Write EnablesSeparate Read and Write AddressData Input, Q Outputs

Contains 16 D-ffs, organized asfour rows (words) of four elements (bits)

670

Q4

D1

D4D3D2

Q3Q2Q1

WE

WAWB

RE

RARB

54

11

1413

12

15123

10976


CMOS Shift Register• 74HC164 is an 8-bit serial in-parallel out shift

register.


Ring counter• A shift register can also be used as a primitive

counter, a ring counter. The shifter sequences through the states 1000, 0100, 0010, 0001 and then repeats. The four-element ring counter sequences through only 4 states, compared with the 16 states of the four-element binary counter.


Johnson counter• A shift register can also be used as a primitive

counter, a ring counter. The shifter sequences through the states 1000, 0100, 0010, 0001 and then repeats. The four-element ring counter sequences through only 4 states, compared with the 16 states of the four-element binary counter.


Troubleshooting Shift Registers• Check mechanical & temperature problems.• Listen carefully to the last thing that was done on

the circuit. (Usually cause of circuit not working acceptable at the moment).

• Clear input to 0 & back to 1 to check clear function operating correctly (output=0000-not lit).

• Data input=1 & clock pulse checks FF A loading.• Data input=1 & clock pulse checks FF B loading.• Data input=1 & clock pulse checks FF C loading.• Data input=1 & clock pulse checks FF D loading.


Troubleshooting Shift Registers Cont.• Use a logic probe to troubleshoot a specific FF

chip.• Use redundant circuits to check what normal

operation is.• Use the redundant chips (i.e. 7474 chip in

redundant circuit to replace suspected bad 7474 chip in a faulty circuit) to check logic probe testing.


Conclusion• Q. What are differences in shift registers?• A. parallel-series input/output.

Shift Register

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