Sec Mirror Updates Firenze Feb 2, 2007. Sec Mirror Updates Firenze Feb 2, 2007.

Firenze Feb 2, 2007 Sec Mirror Updates



Sec Mirror Electronics Upgrades: Overview

1. Digital Control System: FPGA => DSP

2. Capacitance Sensor:

Search for a different proximity sensor

Estimate the real formula of the capacitance / stray capacitance

Make a linear dependency between the measured voltage and the gap

Search for a single capacitance-to-DN converter chip

Test upgrades to the current circuit

Test different approaches

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


Schematic of adaptive optics system

Feedback loop: next cycle

corrects the (small) errors

of the last cycle

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


LBT672 control system global layout

Communication Board (1x backplane)

DSP control Board (14x backplane)

Reference Signal Generator Board (1x backplane)
















Liquid cooled crates, each comprehending 2 backplanes (3x)

Distribution boards

Actuators

Gap

Thin mirrorReference signal

Real timecomm link2.9 Gbit/s

Daisy chain connection



Coil84 custom DSP boards2 DSP/board 168 DSP Tot32-bit floating-point 470Mmac/s

Gigabit Ethernet SwitchDiagnostic communication linkTo the AOsupervisor 400Mbit/s

Total computational power:78 Gmac/s (32bit fp)Real-time reconstructor on-board Slope comm time: 20s

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


DSP Role

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


FPGA vs DSP

What can an FPGA do for real-time video processing compared to a DSP device? The parallel processing capability of an FPGA device meets performance requirements within a single device vs multiple DSP devices DSP device-based designs have traditionally included FPGAs on board for glue logic and processor peripherals. Now, primary DSP functionality can also be handled by the FPGA, including the glue logic, in one device. The integration of hundreds of processors in a real-time design is non-trivial and provides serious complications including design complexity, form factor, power consumption, development time and cost.

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


FPGA vs DSP (ELT)

Number of actuators: 7000+ Power consumption of the actuators: 3kW+ The computational power is related to the square of the number of channels

Maintaining this control concept, we could have an increase of up to two orders of magnitude of the number of DSPs!

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


FPGA vs DSP (summary)

Design complexity

Power consumption

Development time

Cost

Size

System complexity

Performance ? ?

Experience/History

DSP FPGA

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


What we can do…

Test a prototype to verify the feasibilitySplit the design into modulesOutsource the modules to collaborating groups

…since:

Human resources are poor (numerically)

The development time is quite long (3+ yrs)FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


Actel Evaluation Kit

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


Capacitive sensors: current approach

Reference signal

Cvar(gap)

Cref(solid state)

OLD CAPSENS NEW CAPSENS

Sample here

Sample here

DSP BOARD

OUT +

OUT -

Differentialamplifier

OUT1

gap

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


Adopted formula:C = A / d (for the parallel-plate capacitor)

One plate has a hole => the area is reduced by 1/3, but more important, the effect of the internal edge is not negligible One plate is not plane (distortion of the magnet) => the formula is dynamically changing and it depends also on the behavior of the surrounding actuators

Estimate the capacitance (also the stray capacitances) to have an idea of the dynamical behavior and of the direct/inverse dependency

Estimation of the REAL capacitance

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


Next generation?

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


Next generation? (2)

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


Next generation? (3)

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


The main improvements are reported hereafter:

Embedded signal generator. The main advantage is that in this way the noise pickup due to ground level fluctuations observed in the present implementations (where the reference signal is common to all capacitive sensors) can be dramatically reduced

Selection of critical components. The new design is entirely based on single supply, low voltage technology

Direct conversion of the analog output and digital de-modulation. This avoids the use of additional sample and hold circuitry on the sensor output, with benefit on noise and bandwidth

On-board analog to digital conversion. In this way, the noise pick-up along transmission cables is eliminated

Board routing to reduce the effects of stray capacitances and noise sources

Next generation? (summary)

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


Vout

Charge Amplifier

Av= 1 + (Xc2/Xc1)

C1

C2

V+

V-

+

-

U11

3

26

74

V1

12

Upgrades to current approach

CDS Correlated Double Sampling

to the ADC

SW11

2

SW21 2

Reference signal

Cvar(gap)

Cref(solid state)

OLD CAPSENS NEW CAPSENS

Sample here

Sample here

DSP BOARD

OUT +

OUT -

Differentialamplifier

OUT1

gapFPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


Capacitive sensors: a small modification

Dielectric Performance Comparison Table

COG Film Capacitor X7R

Shock Noise Excellent Excellent Good

3rd H Distortion Excellent Excellent Good

ESR Excellent Good Good

Resistance to Heat

Excellent Good Excellent

BDV Excellent Good Excellent

Temp Characteristics

Excellent Excellent Good

DC-Bias Characteristics

Excellent Excellent Good

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


V-

V+

+

-

U16

3

26

74

Vout

Absolute Value Circuit(full-wave rectifier) 4-th order low-pass filterCharge Amplifier

V+

V-

+

-

U12

3

26

74

V2

12

V-

V+

+

-U13

3

26

74

V+

V-

+

-

U14

3

26

74

V-

V++

-

U15

3

26

74

Time

13.00ms 13.01ms 13.02ms 13.03ms 13.04ms 13.05ms 13.06ms 13.07ms 13.08ms 13.09ms 13.10msV(R6:2)

-0.5V

0V

0.5V

1.0V

Time

13.00ms 13.01ms 13.02ms 13.03ms 13.04ms 13.05ms 13.06ms 13.07ms 13.08ms 13.09ms 13.10msV(R2:1)

-1.0V

-0.5V

0V

0.5V

1.0V

Upgrades to current approach (2)

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach • No switches

• Sine waveConclusions


Output

Time

0s 5ms 10ms 15ms 20ms 25ms 30msV(VOUT)

0V

0.2V

0.4V

0.6V

0.8V

1.0V

Vout = 3,5 mV/pF•The DC voltage is 2X the Vin RMS value

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


M1

M2N6758

-

+

U22

INA132/BB

SENS

E5

OUT6

V+7

REF

1V-

4

+3

-2

V+

V-

+

-

U19

3

26

74

Vout

4-th order low-pass filter

V-

V+

+

-

U20

3

26

74

Charge Amplifier

Difference Amplifier Syncronous Demodulator

V-

V+

V+

V-

+

-

U17

3

26

74

V3

12

V+

V-

+

-

U18

3

26

74

-

+

U23

INA132/BB

SENS

E5

OUT6

V+7

REF

1V-

4

+3

-2

V-

V+

U21A

TLC339/5_1/TI

+7

-6

V+3

V-12

OUT1

R29R

R30R

V+V53.5Vdc

Upgrades to current approach (3)

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


Time

0s 5ms 10ms 15ms 20ms 25ms 30msV(VOUT)

0V

40uV

80uV

120uV

160uV

200uV

240uV

Vout = 17,5 mV/pF•No Common Mode DC voltage

Output

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


Capacitive sensors: a different approach

C REF

Capacitivesensor

SensorOscillator

ReferenceOscillator

Phase/FreqComparator

Low PassFilter Gain Stage Vout

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


Capacitive sensors: a different approach

+

-

U8

3

26

74

V+

V-

+

-

U9

3

26

74

V+

V-

U1 LM555

OUT3

RST4

VCC

8G

ND1

CV5

TRG2 THR6

DSCHG7

Vout

V+

U2 LM555

OUT3

RST4

VCC

8G

ND1

CV5

TRG2 THR6

DSCHG7

V+

2nd order Chebyshev LP

reference

sensor

U3A

SN74HC74

D2

CLK3

Q5

Q6

PR4

CL1

U3B

SN74HC74

D12

CLK11

Q9

Q8

PR10

CL13

U4ASN74HC04

12

U4BSN74HC04

34

U5A

SN74HC00

1

23

U6A

SN74HC02

2

31

U6B

SN74HC02

5

64

V+

V+

V+

V+

Frequency Lock Loop

+

-

U7

3

26

74

V-

V+

Sensitivity = 125mV/pF

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Conclusions


Conclusions

FPGA vs DSP

Cap sensor:Now

DSP Role

Next Generation?

OUTLINES

Upgrades tocurrent

AnotherApproach

Potentially there is room for improvements in both the analog and digital aspects of the control system of the adaptive secondary mirror

This could be an occasion to bring the development of this system back to our labs…

…and also the money for these contracts could be used to consolidate and expand our staff

Conclusions


End of capacitive sensors


Facilities

Logic Analyzer

Digital Oscilloscope

PCB Prototyping

Machine

OUTLINES

All are connected to the LAN

2 new (!) entries


Facilities: Tektronix DPO7104

Logic Analyzer


PCB Prototyping

Machine

OUTLINES 1GHz Bandwidth

5 GS/s on all channels, 20 GS on one ch.

20 Megasamples Record Length on all channels, 80 MS on one ch.

>250,000 wfms/s Maximum Waveform Capture Rate

Pinpoint™ Triggering Provides the Most Flexible and Highest Performance Triggering, with over 1400 Combinations to Address Virtually Any Triggering Situation

Save data directly to excel

Zoom-in on four areas of interest simultaneously

Basic spectral analysis

2 new (!) entries


Facilities: Tektronix TLA5201B Logic Analyzer

Logic Analyzer


PCB Prototyping

Machine

OUTLINES 34 Channel

2 GHz Timing with 125 ps MagniVu™ Acquisition

235 MHz State

512K Memory Depth

Drag & Drop Triggering

Flagging the Glitch

Drag & Drop Measurements

TS/TH Violation Triggering

2 new (!) entries


Facilities

Logic Analyzer


PCB Prototyping

Machine

OUTLINES

Tektronix' Integrated View (iView™) data display enables digital designers to solve signal integrity challenges and effectively debug and verify their systems more quickly and easily. This integration allows designers to view time-correlated digital and analog data in the same display window, and isolate the analog characteristics of the digital signals that are causing systems failures.

2 new (!) entries


Facilities: a machine for drilling and routing of PCBs

Logic Analyzer


PCB Prototyping

Machine

OUTLINES Machine bed with universal fixture system, suitable for both clamps and ref. Pins

KaVo high speed , 60,000 rpm spindle motor, 150 W, including 1/8" (3.175 mm) chuck

Standard travel area: 320 x 270 x 30 mm

Smallest drill diameter: 0.3mm

Integral depth limiting device for (isolation) milling and engraving on uneven surfaces

All machine parameters software controlled and configurable, including Z axis

Step definition: 1 mil (= 0,0254 mm), precision +/- 1 step.

2 new (!) entries


Facilities: examples of boards for AGW

Logic Analyzer


PCB Prototyping

Machine

OUTLINES

2 new (!) entries


Facilities: new (old) entries

Logic Analyzer


PCB Prototyping

Machine

OUTLINES

2 new (!) entries

Agilent 15 MHz Function/Waveform Generator

TTi Digital Multimeter


End of Facilities

Sec Mirror Updates Firenze Feb 2, 2007. Sec Mirror Updates Firenze Feb 2, 2007.

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