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SD/eMMC Controller Integration in SHIVA Pankaj Talwar 5 Mar, 2015
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SD/eMMC Controller Integration in SHIVAPankaj Talwar5 Mar, 2015

# 2012 Cadence Design Systems, Inc. All rights reserved.

1# 2011 Cadence Confidential. All rights reserved.

SD cards better known as memory cards are generally used in mobile phones, digital cameras, etc.SD basically stands for Secure DigitalWas developed as an extension to MMC cardsAdvantagesSmall SizesLow PowerLow CostsHigh Capacity

Introduction to SD cards

# 2012 Cadence Design Systems, Inc. All rights reserved.

# 2011 Cadence Confidential. All rights reserved.

Types of SD cardsMemory OnlySDSC(1MBto 2GB)SDHC(2GB to 32GB)SDXC(32GB to 2TB)Memory + I/O functionsSDIO

Speeds in SD cards: So SD card speed is customarily rated by its sequential read or write speed. And the bus interface supports 3 kind of SD card speedsHigh Speed cards(25MByte/s)UHS I(12.5 MByte/s 104 MByte/s)UHS II(156 MByte/s 312 MByte/s)Types of SD cards

# 2012 Cadence Design Systems, Inc. All rights reserved.SD bus Mode:1-bit4-bitSPI(Serial Peripheral Interface) ModeTransfer Modes

# 2012 Cadence Design Systems, Inc. All rights reserved.Electrical Interface:Has total of 9 pinsRequires only 6 wire for communicationUses operational voltage 1.8V - 3.3 VA strong consideration if interface complexity/low power is a concern

Command Interface:The host device sends 48-bit commands and receives responsesCommands help Determine different parameters of cardCard to use a different voltage & speedsCard to receive a block to write/read

Interface

SD Card Diagram

# 2012 Cadence Design Systems, Inc. All rights reserved.Serial information transfer through bi-directional CMD and DATA pinsHost initiates the commandResponse is sent by cardCommands supporting data-transferOperating states in cards

Protocol

# 2012 Cadence Design Systems, Inc. All rights reserved.Data Transfer in BlocksSingle & Multiple BlocksHost responsible for configuring DAT lines

Basic Transaction

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Basic Read & Write

Basic WriteBasic Read

# 2012 Cadence Design Systems, Inc. All rights reserved.Bridge between CPU & SD busIncludes DMA supportResponsible for clock signal to SD Card256 byte Register set

SD host controller

# 2012 Cadence Design Systems, Inc. All rights reserved.Divided into 4 setsHRSSRSERSCRS

Register Set

0x0EF0x1FF

# 2012 Cadence Design Systems, Inc. All rights reserved.SD Host 4 Controller Environment

# 2012 Cadence Design Systems, Inc. All rights reserved.

# 2011 Cadence Confidential. All rights reserved.

Process We followedUnderstanding the basicsExploring block levelIntegrating with SHIVARunning C tests

# 2012 Cadence Design Systems, Inc. All rights reserved.

# 2011 Cadence Confidential. All rights reserved.

Integration

NIC

CPU

PV_MEM_15

TGEN_62

SD Host ControllerAXI Lite Slave InterfaceAXI 4 Master Interface

SD card Model

SD Busdut

Xtensa(C-test)

# 2012 Cadence Design Systems, Inc. All rights reserved.

# 2011 Cadence Confidential. All rights reserved.

Experience & ChallengesDivide the motive into sub partsRestrict yourself from deep divingRevise the source Confidence

# 2012 Cadence Design Systems, Inc. All rights reserved.

# 2011 Cadence Confidential. All rights reserved.

ConclusionExposure to different dimensionsFairly complex designUsed for feature testing

# 2012 Cadence Design Systems, Inc. All rights reserved.

# 2011 Cadence Confidential. All rights reserved.

# 2012 Cadence Design Systems, Inc. All rights reserved.