Address comments to Address comments to [email protected][email protected]Robust FPGA Resynthesis Based on Fault-Tolerant Boolean Matching Yu Hu 1 , Zhe Feng 1 , Lei He 1 and Rupak Majumdar 2 1 Electrical Engineering Dept., UCLA 2 Computer Science Dept., UCLA Presented by Yu Hu Presented by Yu Hu
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Robust FPGA Resynthesis Based on Fault-Tolerant Boolean Matching
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Logic Masking reduces the probability of the propagation of random faults Maximizes the stochastic yield
However, logic synthesis to maximize yield rate w/o explicit redundancy and testing has not been studied for fault tolerance!
Key questions How much does logic masking affect robustness? How and where to place logic masking?
How much Logic Masking Affect Robustness?
18 synthesis solutions obtained by Berkeley ABC (for MCNC i10, LUT bit fault rate = 0.1%)
Different synthesis leads to different logic masking.
Stochastic synthesis maximizes logic
masking!
How and Where to Place Logic Masking?— Our Major Contributions
Propose a Robust FPGA resynthesis (ROSE) Maximize the stochastic yield rate for FPGAs No need to locate faults Use the same synthesis for different chips of one
FPGA application Proposed a new PLB template for robustness ROSE + Robust Template reduces fault rate by 25%
with 1% fewer LUTs, and increases MTBF by 31% while preserving the logic depth compared to Berkeley ABC
Outline Background Preliminaries Robust Resynthesis Experimental Results Conclusion and Future Work
FPGA Synthesis Flow
Attempt to re-map a logic block by Boolean matching Boolean matching can be used to handle both homogenous
and heterogeneous PLBs
RTL Synthesis
LogicSynthesis
Technology Mapping Resynthesis Packing P&R
FPGA Synthesis Flow (cont.)
Multi-iterations of Boolean Matching-based Resynthesis
(Source: Andrew Ling, University of Toronto, DAC'05)
RTL Synthesis
LogicSynthesis
Technology Mapping Resynthesis Packing P&R
Boolean Matching for Resynthesis
2-LUT
2-LUT
2-LUT
2-LUT
2-LUT
ff gg??
Formulate the sub-problem of resynthesis to Boolean matching (BM) BM: Can function f be implemented in circuit g ? Resynthesis: Is there a configuration to g so that for all
inputs to g, f is equivalent to g? Existing algorithms: area/delay-optimal
(Source: Andrew Ling, University of Toronto, DAC'05)
Problem Formulation FTBM Algorithm Robust PLB Template
Experimental Results Conclusion and Future Work
Modeling of Faults
LB1LB2
Intermediate logics
Fault rateof LB1
Input faults of LB2
CIs
Faults in config-bits
X
Faults in config-bits
X
Model both faults in LUT configurations and the faults in intermediate wires as random variables, whose probabilities are given as inputs of our problem.
Resynthesis(Boolean matching)
ROSE: Robust Resynthesis w/ FTBM
Boolean Matching Inputs
PLB H and Boolean function F Fault rates for the inputs and the SRAM bits of the PLB
Outputs Either that F cannot be implemented by PLB H Or the configuration of H which minimizes the probability that
the faults are observable in the output of the PLB under all input vectors.
FTBM tasks breakdown: Step 1: Find a Boolean matching solution Step 2: Evaluation the stochastic fault rate of a solution
RTL Synthesis
LogicSynthesis
Technology Mapping
ROSE(FTBM)
Packing P&R
Fault-Tolerant Boolean Matching
FTBM Step1: SAT Encoding for FTBM
LUT1
c0, SRAM
c1, SRAM
c15, SRAM
x'1 x'2 x'3 x'4
LUT2
c16, SRAM
c17, SRAM
c31, SRAM
x'5 x'6 x'7z1
G
x1 x2 x3 x4 x5 x6 x7 F0 0 0 0 0 0 0 F0
1 0 0 0 0 0 0 F1
0 1 0 0 0 0 0
1 1 1 1 1 1 1 F127
F2
PLB
tem
plat
eB
oole
an fu
nctio
n
If implementable, multiple configurations might exist The one with minimal fault rate is needed!
Conjunctive Normal Form (CNF)
Deterministic SAT vs. SSAT
FTBM Step2: Fault Rate Calculation Based on SSAT
Deterministic SAT Stochastic SAT
Simulation-based fault rate calculation Not scalable for multiple defects
SAT-based fault rate calculation Intelligently modeling random defects
SSAT Encoding for Fault Rate Calculation
Faults in intermediate wiresFaults in LUT configurations
Binary search is performed to find
the maximal β
Example: SAT-Based FTBM
abc g
000 1
001 1
010 1
011 0
100 1
101 1
110 0
111 0
g= !x1!x3+ !x2
2-LUT
2-LUT
2-LUT
x1
x2
x3
fz1
z2
Boolean function
PLB Template
Boolean matching
Example: SAT-Based FTBMStep1: CNFs for the PLB template
2-LUT
2-LUT
2-LUT
x1
x2
x3
fz1
z2
G LUT = ( x1 + x2+ ¬L0 + z) ( x1 + x2+ L0 + ¬ z)
( x1 + ¬ x2+ ¬L1 + z) ( x1 + ¬ x2+ L1 + ¬ z)
(¬ x1 + x2+ ¬L2 + z) (¬ x1 + x2+ L2 + ¬ z)
(¬ x1 + ¬ x2+ ¬L3 + z) (¬ x1 + ¬ x2+ L3 + ¬ z)
L0
L3
L1 4-1 MUX
x1
z
LUT-2
00
11
01
L2 10
x2
PLB Characteristic Function: G = G LUT1 · G LUT2 · G LUT3
Example: SAT-Based FTBMStep2: Replication based on Truth Table