RIFLE: a Research Instrument for FLash Evaluation AT Active Technologies.

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Active Technologies - RIFLE presentation - October 2003

PresentationPresentation

This file contains a RIFLE instrument presentation

A RIFLE’s user demo is shown in the Rifle demo file

This demo has been designed for Office 2002, but it may run quite well under Office 2000


IndexIndex

• Introduction ( 1 min. 15”)

• Hardware features ( 7 min. 10”)

• System performances ( 1 min. 55”)

• Software architectureSoftware architecture ( 2 min. 10”)

• Scientific references ( 1 min. 10”)

• Role of Active Technologies and N-plus-T ( 20”)

• End of presentation

Select the section to visit by clicking on the section nameSelect the section to visit by clicking on the section nameSelect the section to visit by clicking on the section nameSelect the section to visit by clicking on the section name


Project historyProject history

• 1996 – Kick-off of the RIFLE project, at the Università di Ferrara, Italy

• 1998 – First prototype: beginning of research activity

• 2001 – First industrialized release

• 2002 – Second industrialized release

• 2003 – Creation of the Academic spin-off Active Technologies for RIFLE commercialization and support


Aims of the projectAims of the project

• Development of a “flexible” instrument for research/characterization activities

• ATE-like hardware performances

• Standard software support (C, C++ languages and LabVIEW)

• Ultra-friendly use


Flexible instrument: whyFlexible instrument: why

• New products development and characterization require high flexibility (data acquisition, signal

waveforms, voltages, …)

• “What if” philosophy

• Possibility of identify and track selected cells

• Possibility of evaluating the impact of any modification on long-term reliability

• Possibility of immediate availability of measure’s results


End of SectionEnd of Section

Make your choice by using the PC mouseMake your choice by using the PC mouseMake your choice by using the PC mouseMake your choice by using the PC mouse

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Instrument architecture


FeaturesFeatures

P.C.I. BUS

• Standard Bus

• DUTDUT (Device Under Test) is treated as an extension of the PC memoryextension of the PC memory: it is simply accessed like an array structure during read/write cycles

• PC’s storing and computational capabilities PC’s storing and computational capabilities are fully exploitedare fully exploited

• Storing and computational capabilities can Storing and computational capabilities can be upgraded by upgrading the PCbe upgraded by upgrading the PC

• Address spaceAddress space: 512Mbytes

• Bus widthBus width: 8, 16, 32 bits

• Bus speedBus speed: up to 33 MHz


A Programmable state machine translates the PCI cycles into the DUT cycles to match its timing requirements

Timing Generator


Waveform generators

Unused slots for waveform generators can be used to plug-in customized plug-in customized cards cards to add new hardware features new hardware features

RIFLE can be equipped with up to 16 arbitrary waveform generators16 arbitrary waveform generators.

The impact on device performance and long term reliability of any shape any shape and duration modification in the waveform and duration modification in the waveform applied during writing operations can be easily evaluated


Waveform generators

DA

C

Top

Bottom

ControlBlock

The generator architecture is based on a high speed 32ksample (or 128ksample) SRAM, managed as a FIFOFIFO, where the waveform samples are stored during the measurement setup


Waveform generators

DA

C

Top

Bottom

ControlBlock

When the waveform is generated, its samples are poppedpopped from the FIFO memory and convertedconverted into an analog signal by a high speed (125 Msps) D/A converter and a current feedback output buffer (140Mhz Bandwidth, 2500 V/s Slew-Rate)


Waveform generators

DA

C

Top

Bottom

ControlBlock

• Output buffer performances:Output buffer performances:

• Output voltage range: up to ± 13 V (trimmerable)• Maximum output current: ± 50 mA• Bandwidth: 140 MHz• Slew rate: 2500 V/s

• Different requirements can be obtained by substituting the output buffer or by pluggingplugging a specific generator into the motherboard


Waveform generators

DA

C

Top

Bottom

ControlBlock

Single pulseSingle pulse or periodicperiodic arbitrary waveforms can be generated

The sampling rate is programmable:

- The maximum time resolutionmaximum time resolution is 10 ns (@100Mhz) with a maximum pulse duration of 327.68 s

(with a 32K sample FIFO) - The minimum time resolutionminimum time resolution is 327.68 s with a

maximum pulse duration of 10.7 s (with the clock signal divided by 32768)


Waveform generator synchronization

RIFLE has advanced synchronization capabilities to keep the timing RIFLE has advanced synchronization capabilities to keep the timing requirements of the DUT and to synchronize all its data acquisition requirements of the DUT and to synchronize all its data acquisition and generation circuits:and generation circuits:

All generators can be simultaneously triggeredAll generators can be simultaneously triggered

All generators can be triggered by external events All generators can be triggered by external events

Waveforms can be arbitrarily and mutually delayedWaveforms can be arbitrarily and mutually delayed

3 specific waveform generators have the alternative function of 3 specific waveform generators have the alternative function of synchronization generatorssynchronization generators to generate the trigger events for the to generate the trigger events for the analog acquisition circuits or for the other arbitrary waveform generatorsanalog acquisition circuits or for the other arbitrary waveform generators

Analog signal acquisitions can be synchronized with the applied voltage Analog signal acquisitions can be synchronized with the applied voltage waveformswaveforms


General purpose I/O

16 digital outputs and 8 digital inputs are provided 16 digital outputs and 8 digital inputs are provided to drive the DUT internal logic circuitsto drive the DUT internal logic circuits


Level Translators

• All All the the digital signal levels are translateddigital signal levels are translated into the programmable DUT power supply voltage level to support devices with different power requirements

• The DUT power supply can be programmed from 5V down to 1.2 V5V down to 1.2 V

• The DUT power supply is provided by a 3Amp3Ampss programmable voltage generatorprogrammable voltage generator


Current Generator

A programmable Current GeneratorCurrent Generator provides the reference currentreference current required for read and verify operations


Direct Memory Access

A circuit called DMADMA is provided to measure the current current characteristicscharacteristics of any cell.

Both 2D or 3D2D or 3D characteristic can be evaluated.



I/V ConvertersA/D

A/D

Data BusVoltage

Generator

Sw

itch

Matr

ix

I

By means of a switch matrix two data bus linestwo data bus lines are selected and a voltage is appliedvoltage is applied by means of a voltage generator



I/V ConvertersA/D

A/D

Data BusVoltage

Generator

Sw

itch

Matr

ix

I

The currents supplied on these lines are converted into voltages and then digitized in parallelparallel by two 12 bit ADCs with a 2.5s conversion time



The trigger command can be generated by means of a synchronism generator so that the acquisition can start at any any desired and synchronized timedesired and synchronized time

I/V ConvertersA/D

A/D

Data BusVoltage

Generator

Sw

itch

Matr

ix

I


Power Zero

RIFLERIFLE has a circuit called Power ZeroPower Zero that performs synchronized high speed current waveform measurementssynchronized high speed current waveform measurements on anyany DUT signal


Power Zero

Video Diff. Amp.ADC FIFO

control signals

Switch Matrix

By means of a switch matrixswitch matrix anyany DUT signal (power supply included) can be selected and connected to the PW0 unit



control signals

Switch Matrix

Power Zero

Pulse Generator

A pulse generatorpulse generator applies a waveform on the selected device pin



control signals

Switch Matrix

Power Zero

A high speedhigh speed differential differential AmplifierAmplifier reads the voltage drop across a sensing resistance due to the current flowing

Pulse Generator



Pulse Generator

control signals

Switch Matrix

Power Zero

Third state

AnyAny pin of the DUT can also be connected to an alternative voltage generatoralternative voltage generator



Pulse Generator

control signals

Switch Matrix

Power Zero

The current waveformcurrent waveform is then sampled at up to 40Msps40Msps by a 10 bit10 bit A/D converter



Pulse Generator

control signals

Switch Matrix

Power Zero

The samples are stored in a FIFOstored in a FIFO memory (4Ksample deep)


Power Zero


Pulse Generator

control signals

Switch Matrix

The current waveform conversion and storing can be triggered by means of a synchronism generator so that the waveform acquisition can start at any waveform acquisition can start at any desired time, synchronously with the applied pulsedesired time, synchronously with the applied pulse


Calibration

The hardware calibration is made during the first factory system testing and doesn’t need any user intervention.

A further software fine calibration can be periodically executed by the user.

By means of a dedicated calibration board and a multimeter, the user can adjust both the offset and gain errors of all analog circuits following the step by step procedure of the calibration software provided with the calibration board.




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Performances

Current unit resolutions and full-scales

DMADMA current measurement unit:

2 full-scales: 2 full-scales: ±500 ±500 A, 12 bit resolutionA, 12 bit resolution

±± 50 50 A, 12 bitA, 12 bit resolutionresolution


Performances

PW0PW0 current measurement unit:

3 full-scales:

500 500 A, 10 bit resolutionA, 10 bit resolution

5 mA, 10 bit resolution5 mA, 10 bit resolution

50 mA, 10 bit resolution50 mA, 10 bit resolution



Performances

Current generatorCurrent generator:

2 full-scales:





The time requirements for standard operations strongly depend on device speed and bandwidth

Time limitations are usually imposed by the device itself

The following time requirements refer to a 8.6 Mbit sector of a commercial device

Performances

Time requirements (examples)Time requirements (examples)


Minimum read cycleMinimum read cycle (@32 bit bus width, 0 wait-states):

4 clock periods 200 ns200 ns (@20Mhz) (@20Mhz)

Performances



ProgrammingProgramming:

1 sector (8.6 Mcells), with verify, 1 single pulse applied to each cell, 8bit parallelism: 1.9 1.9 ss

Performances



ErasingErasing:

8.6 Mcells sector, with verify, 1 pulse applied: 1.201.20 s s

Performances



Performances

Threshold Voltage DistributionsThreshold Voltage Distributions

with 20 resolution levels: 1818 s s



Threshold Voltage MapsThreshold Voltage Maps

with 20 resolution levels: 1’ 29 1’ 29 ss

PerformancesTime requirements (examples)


Criterion based subset identificationCriterion based subset identification:

identification of 1000 cells complying with a particular requirement (i.e., the lowest, the highest, etc.): 40.140.1 s s



VVthth tracking for subset of cells tracking for subset of cells:

threshold voltage measure of the identified 1000 cells : 5.45.4 s s





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Software

RIFLEinstrument

Architecture

The instrument software is hierarchically organized to hide the implementation details and, by means of different programming languages, to create a powerful and easy to use environment


Software

RIFLEinstrument

Instrument Driver

At the lowest level, just above the hardware, there is the instrument driver. It belongs to the PC Operating System and it must not be modified by the user. It’s written in “C” and assembler languages.

System Level Interface: Virtual Device Driver


Software

RIFLEinstrument


Application Program Interface: Dynamic Link Libraries

API

At a higher layer we find the API. It’s a library of functions that work as an interface between the driver routines and the higher level programming languages. Also this layer must not be modified by the user.


Chip Dependent Interface

This is the first layer that can be modified by the user.

It consists of a library of functions specific for the DUT.

It’s written in “C” or “C++” to achieve high efficiency and must be implemented for any new device.

Software

RIFLEinstrument



Chip Dependent Interface: Dynamic Link Libraries


SoftwareHigh level Program Interface

The High Level Program Interface is written in the “G” language of the National Instrument LabVIEW program.

At this level, by means of several panels, the user can control any instrument operation, execute measurements and graphically analyze data.

RIFLEinstrument



Chip Dependent Interface: Dynamic Link Libraries

High Level Program Interface:LabVIEW Virtual Instrument Libraries


High level software structure

Any measurement can be set up and launched in a completely graphical environment developed under the National Instruments LabVIEW platform


Executing standard measurements

By means of a navigator window it is possible to set up the parameters for any measurement (program, erase, IV measures, distributions and maps, stresses, ..), to browse among 2D and 3D maps and distributions of threshold voltages or current gains, 2D and 3D I-V characteristics




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Scientific referencesScientific references

RIFLE has been extensively used for research purposes at the Università di Ferrara

Several papers have been published on international journals or presented at international conferences thanks to RIFLE

A list of paper published on int. journals is here reported



P. Pellati et al, “Automated Test Equipment for Research on Nonvolatile Memories” IEEE Trans. Instrum. Meas. vol. 50, p. 1162, Oct. 2001

A. Chimenton et al, "Threshold voltage spread in Flash memories under a constant DQ erasing scheme", Microelectronic Engineering, vol. 59, p. 109, Nov. 2001

A. Chimenton et al. "Analysis of Erratic Bits in Flash Memories", IEEE Trans. on Device and Materials Reliability, vol. 1, p. 179, Dec. 2001

G. Cellere et al., "Radiation Effects on Floating-Gate Memory Cells", IEEE Trans. on Nucl. Sc., vol.48, p. 2222, Dec 2001

A. Chimenton et at, "Constant Charge Erasing Scheme for Flash Memories", IEEE Trans. on Electron Devices, vol. 49, p. 613, Apr.2002

G. Cellere et al., "Anomalous charge loss from Floating-Gate Memory Cells due to heavy ions irradiation", IEEE Trans. on Nucl. Sc., vol. 49, p. 3051, Dec. 2002



A. Chimenton et al., "Erratic bits in Flash Memories under Fowler-Nordheim programming", Jpn. J. Appl. Phys., vol. 42, p. 2041, April 2003

A. Chimenton et al., "Flash Memory Reliability: an Improvement Against Erratic Erase Phenomena Using the Constant Charge Erasing Scheme", Jpn. J. Appl. Phys., vol. 42 , p. 2025, Apr. 2003

A. Chimenton et al., "An Insight Into Flash Memory Reliability: Erratic, Fast and Tail bits", Proceedings of the IEEE, Vol. 91, p. 617 - 626, Apr. 2003

A. Chimenton et al., “Erratic Erase in Flash Memories (part I): Basic Experimental and Statistical Characterization” IEEE Trans. on Electron Devices, Vol. 50, p. 1009, Apr. 2003

A. Chimenton et al., “Erratic Erase in Flash Memories (part II): Dependence on Operating Conditions” IEEE Trans. on Electron Devices, Vol. 50, p. 1015, Apr. 2003




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Role of Role of ATAT and and N-plus-TN-plus-T

RIFLE production Service and maintenance Test head design and production

RIFLE commercialization


Role of Role of ATAT and and N-plus-TN-plus-T

Training Software upgrade Driver design

&&




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The staff of The staff of Active TechnologiesActive Technologies thanks you for your kind thanks you for your kind

attentionattention

www.activetechnologies.itwww.activetechnologies.it

[email protected]@activetechnologies.it

RIFLE: a Research Instrument for FLash Evaluation AT Active Technologies.

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