Reversible Computing Performance Analysis

8/10/2019 Reversible Computing Performance Analysis

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REVERSIBLE COMPUTINGPERFORMANCE ANALYSIS

Presented by

Shiny M.I(!""!#

Priy$dh$rshini.M(%""

Sree R$n'$ni R(%""#

)*+)*"%


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O,t-ine

Oerie/ $b0,t the reersib-e -01i21$tes.

Ty3es 04 reersib-e -01i2 1$tes.

T0 desi1n $ 205bin$ti0n$- 2ir2,it,sin1 reersib-e -01i2 1$tes.

T0 desi1n $ se6,enti$- 2ir2,it ,sin1reersib-e -01i2 1$tes.

Si5,-$ti0n ,sin1 7s3i2e.

A33-i2$ti0n 04 reersib-e -01i2 1$tes.)*+)*"% *


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Intr0d,2ti0n

A 2ir2,it is reersib-e i4 it 5$3s e$2hin3,t e2t0r int0 $ ,ni6,e 0,t3,te2t0r $nd i2e ers$.

Reersib-e G$tes $re 2ir2,its in /hi2hn,5ber 04 0,t3,ts is e6,$- t0 then,5ber 04 in3,ts $nd there is $ 0ne

t0 0ne 20rres30nden2e bet/een thee2t0r 04 in3,ts $nd 0,t3,ts.

)*+)*"% !


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S05e reersib-e 1$tes..

Feynman Gate

Double FeynmanGate (F2G)

Tofoli Gate Fredkin Gate

Peres Gate

Double Peres gate

NCG[Ninescompliment gate

!"# Gate

"!C$ gate

%&G Gate

!C$ Gate

DPG Gate "%' Gate

D&G Gate

"#F Gate

T&! Gate

T!G Gate

G Gate

)*+)*"% %


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Feynman Gate

The in3,t e2t0r is I (A8 B# $nd the0,t3,t e2t0r is O(P8 9#.

The 0,t3,ts $re de:ned by P;A89;A


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Double Feynman Gate(F2G) The in3,t e2t0r is I (A8 B8 C# $nd the

0,t3,t e2t0r is O(P8 98 R#.

The 0,t3,ts $re de:ned by P ; A89;A


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Fredkin Gate

The in3,t e2t0r is I (A8 B8 C# $nd the0,t3,t e2t0r is O(P8 98 R#.

The 0,t3,t is de:ned by P;A8 9; A>B C


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Tofoli Gate

The in3,t e2t0r is I(A8 B8 C# $nd the0,t3,t e2t0r is O(P898R#.

The 0,t3,ts $re de:ned by P;A89;B8 R;AB


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Double Peres gate

The in3,t e2t0r is I(A8B8C8@# $nd the0,t3,t e2t0r is O(P898R8S#.

The 0,t3,t is de:ned by P;A89;A


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DKG Gate

A % % reersib-e @G 1$te th$t 2$n/0r sin1-y $s $ reersib-e F,-- $dder$nd $ reersib-e F,-- s,btr$2t0r.

I4 in3,t A;"8 the 3r030sed 1$te

/0rs $s $ reersib-e F,-- $dder8 $ndi4 in3,t A;8 then it /0rs $s $reersib-e F,-- s,btr$2t0r.

@G GATE)*+)*"%


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. Mini5iDe the 1$rb$1e

*. Mini5iDe the /idth 04 the 2ir2,it

(the n,5ber 04 $dditi0n$- in3,ts#

!. Mini5iDe the t0t$- n,5ber 04 1$tes

%. Mini5iDe the de-$y

Goals o* re+ersible logicsynt,esis

)*+)*"% *


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COMBINATIONAL CIRCUIT

C05bin$ti0n$- -01i2 is $ ty3e 04 di1it$- -01i28 /hi2h isi53-e5ented by B00-e$n 2ir2,it.

The 0,t3,t 04 the 205bin$ti0n$- -01i2 is $ 3,re 4,n2ti0n 04the 3resent in3,t .

C05bin$ti0n$- -01i2 is ,sed in 2053,ter 2ir2,its t03er40r5 B00-e$n $-1ebr$ 0n in3,t si1n$-s 8 s05e $re

7$-4 $dders8 F,-- $dders8 7$-4 s,btr$2ti0ns 8 F,--s,btr$2ti0ns.

M,-ti3-e


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FULL ADDER


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MULTIPLEXER

A multiplexer can use addressin !its t" select "ne "#

se$eral input !its t" !e t%e "utput&' A select"r c%""ses a sinle data input and

passes it t" t%e MUX "utput

' It %as "ne "utput selected at a time&


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CON(ENTIONAL ) TO * MULTIPLEXER

C"nsists "#+

Inputs ,multiple- . /n

Output ,sinle-

0elect"rs ,depends "n t%e inputs- . n

Ena!le ,acti$e %i% "r acti$e l"1-


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RE(ER0IBLE LO2IC

Double Peres gate

T%e input $ect"r is I,A3B3C3D- and t%e "utput $ect"r is O,P343R30-& T%e #ull adder circuit is implemented usin DP2 ate


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0E4UENTIAL CIRCUIT0

0e5uential circuits use current input $aria!les and pre$i"us

input $aria!les !6 st"rin t%e in#"rmati"n and #eed!ac7 t%e

"utput int" t%e circuit in t%e next cl"c7 c6cle&

T%e mem"r6 elements are used t" st"re t%e past %ist"r63

'8ire

' Latc%es and' Flip #l"ps&


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D FLIP FLOP

T%e D #lip #l"p trac7s t%e input3 ma7in transiti"ns 1it% matc% t%"se "# t%einput D&

T%e D stands #"r 9data:3 t%is #lip #l"p st"res t%e $alue t%at is "n t%e data

line


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RE(ER0IBLE LO2IC

T%e ate is "ne t%r"u%3 1%ic% means "ne "# t%e input $aria!les is als"

"utput&

The 3r030sed reersib-e RR 1$te is 3$rity 3reserin1. This iseri:ed by 2053$rin1 the in3,t 3$rity ABC@ t0 the0,t3,t 3$rity P9RS.

T%e D Flip #l"p is desined usin RR re$ersi!le l"ic 31it% a #eed!ac7

part&


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MA0TER 0LA(E D FLIPFLOP

T%e master stae is p"siti$e le$el sensiti$e3 1%ile t%e sla$e stae is

neati$e le$el sensiti$e&

Hhen the 2-02 is hi1h8 the 5$ster st$1e 40--0/s the @ in3,t/hi-e the s-$e st$1e h0-ds the 3rei0,s $-,e.

Hhen the 2-02 2h$n1es 4r05 -01i2 t0 -01i2 "8 the 5$ster-$t2h 2e$ses t0 s$53-e the in3,t $nd st0res the @ $-,e $tthe ti5e 04 the 2-02 tr$nsiti0n $nd the s-$e 3$sses thest0red 5$ster $-,e t0 the 0,t3,t.


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Per40r5$n2e 04 Reersib-eG$te

,A- Peres ate+ P2,A3 B3 C- . A ; B C

,B- Fred7in ate+ F,A3 B3 C- . A


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@G Reersib-e G$te

)*+)*"% *!


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@G ,sed 40r F,-- Adder

)*+)*"% *%


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)*+)*"% *=


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C0nenti0n$- F,-- Adder

)*+)*"% *&


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Reersib-e @G 1$teF,-- Adder

)*+)*"% *+


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Are$C0nenti0n$- F,-- Adder

)*+)*"% *


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Are$ J@G Reersib-e G$te FA

)*+)*"% *?


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P0/erC0nenti0n$- F,-- Adder

)*+)*"% !"


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30/er J@G Reersib-e G$te FA

)*+)*"% !


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@F-i3F-03

)*+)*"% !*


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Fredin G$te

)*+)*"% !!


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F$y5$n G$te

)*+)*"% !%


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A33-i2$ti0n 04 Reersib-e -01i2 1$tes

L0/ 30/er CMOS. 9,$nt,5 2053,ter.

N$n0te2hn0-01y .

O3ti2$- 2053,tin1 .

@esi1n 04 -0/ 30/er $rith5eti2 $nd d$t$3$th 40r di1it$- si1n$- 3r02essin1 (@SP#.

Fie-d Pr01r$55$b-e G$te Arr$ys (FPGAs#

in CMOS te2hn0-01y 40r e


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CONCLUSION

Re$ersi!le C"mputin is an attracti$e researc%

area.

T%e re$ersi!le circuits #"rm t%e !asic !uildin!l"c7 "# 5uantum c"mputers as all 5uantum

"perati"ns are re$ersi!le&

It als" !etter #"r desinin c"mputati"nal

!l"c7s t" "$erc"me t%e ar!ae "utputs and

c"mplexit6 "# ates&

)*+)*"% !&


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Re4eren2es*&T%apli6al >3 M&B&0%rini$as&? A Ne1 Re$ersi!le T02 2ate and Its

Applicati"n #"r Desinin E##icient Adder Circuits?& Centre #"r (L0I and

Em!edded 06stem Tec%n"l"ies Internati"nal Institute "# In#"rmati"nTec%n"l"63 >6dera!ad3 @*3 India&

/& >imans%u T%apli6al and M&B 0rini$as3 :A !einnin in t%e re$ersi!le

l"ic s6nt%esis "# se5uential circuits %a$in #eatures "# "nline

testa!ilit6?3 0PIE Micr"electr"nics3 MEM03 and Nan"tec%n"l"606mp"sium3 Bris!ane3 Australia3 Decem!er ***)3 /@&

& R& Fe6nman3 :4uantum Mec%anical C"mputers?3 Optical News,

*@3 pp& **/

)& Ra%a$a 2aripell6*3 P&Mad%u iran/3 A&0ant%"s% umar : A Re$ie1

"n Re$ersi!le L"ic 2ates and t%eir Implementati"n?Internati"nal

G"urnal "# Emerin Tec%n"l"6 and Ad$anced Enineerin & ("lume 3

Issue 3 Marc% /*)*+)*"% !+


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)*+)*"% !

T%an7 H"u

Reversible Computing Performance Analysis

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