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Report Gdc 10

Apr 10, 2018

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    1. Introduction:

    An Insulated Gate Bipolar Transistor (IGBT) is a power semiconductor device,

    which is widely used in power electronic applications such as uninterruptible power supplies, motor

    drives and active filters. An IGBT combines certain advantages of a power Bipolar Junction

    Transistor (BJT) and a power Metal Oxide Silicon Field Effect Transistor (MOSFET). An IGBT

    can be driven easily and switched at high frequencies like a MOSFET. Further it has low on-state

    loss and a high current density like a BJT.

    For an IGBT based converter to be rugged and reliable, the IGBT gate-drive circuit

    should be reliable. In this paper, a gate-drive circuit for an IGBT is presented. The drive circuit is

    capable of protecting the IGBT against short-circuit. During fault, excessive current flows through

    the device, causing the device to come out of saturation and increasing the collector-emitter voltage

    Vce. The gate-drive circuit senses a fault through the increased Vce drop [1]-[5], and shuts down the

    gate pulses. The drive circuit also protects the IGBT from gate-emitter over-voltage [6]-[8].

    Further, if the on-state gate-emitter voltage decreases, the on-state drop of the device increases,

    leading to increased loss and possible device failure [6]-[9]. The proposed circuit is capable of

    protecting the device from gate-emitter under-voltage as well.

    The proposed IGBT gate-drive circuit is tested both under normal condition and

    short-circuit condition. The switching characteristics include gate-emitter voltage Vge, collector-

    emitter voltage Vce and device current Ic. While Vge and Vce can be measured, there are difficulties

    in sensing Ic in many practical situations. A current probe of appropriate bandwidth may not be

    available or may be too expensive. More importantly, it may not be possible to insert a current

    probe in series with the device owing to the sandwich bus-bar structure. Such a bus-bar structure is

    to ensure low parasitic inductance in order to avoid excessive over-voltage spikes that could cause

    device failure [1]. Owing to such practical difficulties, this paper adopts a testing method which

    does not require any current sensing.

    Section 2 of this paper briefly discusses the gate-drive requirements. An IGBT gate-

    drive circuit is presented in section 3. Section 4 of this paper discusses the experimental set-up.

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    Section 5 and section 6 present the experimental results under normal condition and short-circuit

    condition, respectively. The conclusions are presented in section 7.

    2. Requirement of a gate-drive circuit:

    A gate-drive circuit should have certain features, which help a power electronic

    system to be rugged and reliable, as discussed below.

    The drive circuit should provide adequate on-state gate-emitter voltage. Also the off-

    state gate-emitter voltage should be well below the threshold voltage [6]-[9]. Even though the

    IGBT is a voltage controlled device, an adequate amount of gate-drive current is required for a

    short duration during turn-on/off as indicated by Fig. 1 and 2, because the device has a large input

    capacitance [10]. The gate-drive circuit should be capable of supplying the peak current required

    for effective turn-on/off.

    For safe operation of the device, the gate-emitter voltage should not exceed the

    absolute maximum gate-emitter voltage [6]. An over-voltage protection is required in this regard.

    Also, lower value of on-state Vge significantly increases the on-state voltage drop of IGBT [6]. The

    increased conduction loss could lead to device failure. The circuit should also be capable of

    protecting the device against such failure on account of Vge under-voltage. Further, it should also

    have the capability to protect an IGBT against short-circuit. Under short-circuit condition, an IGBT

    can withstand a fault current of roughly eight to nine times of its rated current for 10 s [7]. The

    gate-drive circuit should have the capability to sense the fault and turn-off the IGBT well within 10

    s. The following conditions have to be fulfilled to guarantee safe operation [7];

    i. The short-circuit has to be detected and turned off within a maximum of 10 s,

    ii. The time between two short-circuits has to be at least 1 second,

    iii. The IGBT must not be subjected to more than 1000 short-circuits during its total operation time.

    The gate-drive circuit should provide isolation between the control side and the

    power side of the system. The high voltages in the power circuit should not reach the control circuit

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    for safety of personnel and equipment. Further, in a voltage source inverter, the pulse width

    modulation signals for all six devices are generated in a controller (typically a digital controller).

    These signals have to be fed between gate and emitter terminals of the individual devices. The

    emitter terminals of different devices are at different potentials. Hence electric isolation is required

    between the control circuit and power circuit [5]. Further, the drive circuit should have an on-board

    isolated power supply to power the isolated side of the circuit.

    Vg

    Vge

    Ic

    Vce

    I0

    Vce,sat

    VGG

    VGG

    tr

    tfv1

    tfv2

    t

    t

    t

    t

    Vge(th)

    Vge,I0

    Vf1

    Td,on

    Ig

    Fig. 1 Turn-on characteristics of IGBT [10]

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    Vg

    Vge

    Ic

    Vce

    I0

    Vce,sat

    - VGG

    - VGG

    Td,off

    trv

    tfi1

    tfi2

    t

    t

    t

    t

    Vge(th)

    Vge,I0

    VD

    If1

    tfIg

    Fig. 2 Turn-off characteristics of IGBT [10]

    An IGBT gate-drive circuit with the above features is presented in the following

    section.

    3. Proposed gate-drive circuit:

    Fig. 3 shows a block diagram of the proposed gate-drive circuit. Fig. 4 presents the

    circuit schematic of the same. The gate-drive circuit is powered by a +15V dc power supply. The

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    drive signal and Vce sensing signal are the inputs to the drive circuit, while the gate-emitter voltage

    Vge and the status signals are the outputs, as indicated in Fig. 3.

    Fig. 3 Block diagram of a gate-drive circuit

    3.1 Isolation:

    The drive signal is electrically isolated using an opto-coupler HP3101, (U1) [11], as

    shown in Fig. 4. The status signal, produced by the gate-drive circuit as will be explained in section

    3.4, is similarly isolated using another opto-coupler (U6). An isolated power supply is used to feed

    the isolated (power) side of the circuit, indicated by dashed lines in Fig. 3.

    3.2 Drive:

    When the gate-drive signal is HIGH, the corresponding output of the opto-coupler,

    U1 [11], is also HIGH. This isolated drive signal is fed to a logic circuit, which is simply a

    NAND gate (U3/4), as seen from Fig. 4. The other input to the NAND gate is the isolated status

    signal (Status_Iso) produced by the protection circuit as indicated in Fig. 3.

    The output of the NAND gate drives an inverting buffer (U4), MIC4429 [12], and a

    non-inverting buffer (U5), MIC4420 [12]. The output of the non-inverting buffer is connected to

    the emitter terminal as shown in Fig. 4. The output of the inverting buffer is connected to the gate

    terminal through gate resistance Rg. Sometimes, the gate resistance required for turn-on and turn-

    off transitions are different. In Fig. 4, R16 is Rg,on, while R17 is Rg,off.

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    6

    ++

    1

    4

    2

    7,6

    8

    5

    1

    4

    2

    7,6

    8

    5

    R1 C1

    R2

    R3

    R4

    R5

    R6D1

    R7

    Z1

    R8

    R9

    R10

    R11

    R12

    R13

    R14

    Z2

    R15

    R16

    R17D2

    D3

    C8 C10

    C9 C11

    C6

    C7

    R18

    R19

    R20

    R27 C23

    C12

    Q1

    Q2

    13

    1211

    108

    94

    5

    6

    31

    2

    7

    14C5

    13

    11

    1016

    7

    C15

    R24

    LD1

    C13

    POT1

    C14R22

    R23

    R26

    R21

    D5

    Q3

    T1

    C15

    D4

    C16

    C17

    C18

    R25

    LD2

    C19

    31 2

    2,12,15

    3

    14

    5

    6

    8,11

    1,4,7,9

    10,13,16

    U1

    U2/1

    U2/2

    U3/1

    U3/2 U3/3

    U3/4

    U4

    U5

    U6

    U7

    U8 +15V_ISO

    GND_ISO

    +15V

    GND

    PWM

    C'STATUS

    G'

    E'

    NI

    I

    LED

    ON

    OFF

    O/P

    H

    L

    G'

    E'

    J2

    C'

    J3

    +15V

    GND

    PWM

    STATUS

    J1

    C3

    2

    3

    8

    5

    6

    7

    2

    3

    8

    5

    6

    7

    C22

    C2

    3

    12

    C4

    +15V_ISO+15V_ISO

    +15V_ISO

    +15V

    +15V

    GND

    GND_ISO

    GND_ISO

    GND_ISO

    TP4

    TP1

    TP5

    TP6

    TP7

    TP8

    TP9

    TP11

    TP10

    TP12TP3

    TP13

    TP14

    TP15

    TP16 TP17

    TP18

    C20

    (a)

    (b)

    Fig. 4 (a) Gate-drive Card (b) Zener Card

    Under healthy condition, if the drive signal is HIGH, then the output of the NAND

    gate (U3/4) is LOW. Correspondingly, the vo