Abstract The sigma-delta modulator based closed loop systems make high resolution, high SNR, low frequency systems. The sigma- delta analog to digital converter consists of the modulator followed by the decimation filter. In this project the design of decimation filter, which performs the role of filtering the shaped quantization noise and converting 1-bit data stream into 20 bit high-resolution output is reported. An efficient multi-stage decimation methodology is adapted where decimation is performed in several stages due to high order of the decimation filter which is almost impossible to implement in hardware. The multi-stage structure consists of Cascaded Integrator Comb (CIC) filter followed by FIR. The specifications of decimation filter are derived from the specifications of a third-order single bit sigma-delta modulator. Use of cascaded integrated comb filter for the first stage has made the implementation easy by requiring no multiplication. Furthermore, it can be used to decimate the data by a large factor, allowing easier implementation of the following stages. Distributed arithmetic algorithm is used to design FIR filters. Software model for the decimation filter is developed using MATLAB /Simulink, and integrated with
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Abstract
The sigma-delta modulator based closed loop systems make high resolution, high SNR,
low frequency systems. The sigma-delta analog to digital converter consists of the modulator
followed by the decimation filter. In this project the design of decimation filter, which
performs the role of filtering the shaped quantization noise and converting 1-bit data stream
into 20 bit high-resolution output is reported.
An efficient multi-stage decimation methodology is adapted where decimation is
performed in several stages due to high order of the decimation filter which is almost
impossible to implement in hardware. The multi-stage structure consists of Cascaded
Integrator Comb (CIC) filter followed by FIR. The specifications of decimation filter are
derived from the specifications of a third-order single bit sigma-delta modulator. Use of
cascaded integrated comb filter for the first stage has made the implementation easy by
requiring no multiplication. Furthermore, it can be used to decimate the data by a large
factor, allowing easier implementation of the following stages. Distributed arithmetic
algorithm is used to design FIR filters. Software model for the decimation filter is developed
using MATLAB /Simulink, and integrated with sigma-delta modulator model to analyze the
responses. The hardware model for the filter is developed using Verilog HDL.
The design is implemented and tested using SPARTAN 3E FPGA. Filter has got pass
band of 100Hz and stopband of 200Hz .The test environment has the feature of taking
external input as well as the internally stored bit stream in LUT. The designed system
exhibits good linearity and the design consumes a power of 40.4mW.
Sangil Park, 3rd order modulator, SNR 120 dB18-20 Bit resolution
This architecture uses 6stage half band filter, Increasing resolution of conventional filters with FIR filters
Table 2.3 shows gives a quick summary of papers that is been referred for this
project. Even though Patick and Ali [5] discuss about area efficient FPGA implementation,
they talk only about lower order filter, which will not help in implementing higher order
filters. Whereas, Fujicikl [3] discuss about decimation filter implementation using multiplier
for higher frequency system. Sangil [6] discuss about implementing decimation filter using
halfband filters which will increase the area in FPGA implementation.
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2.2.7 Important points from journals/transactions/books referred
Lukas Fujcik [3] presents the practically possible architecture for decimation filter, with
multistage approach. The proposed architecture consists of three stages – one Cascaded
Integration Comb filter followed by two (FIR) filters. Decimation filter specification is
derived from the modulator specification. It is understood from the paper that quantization of
filter coefficients reduces the filter performance and when using 24 bit for the quantization
the response of the quantized filter matches that of the reference filter from MATLAB. This
paper takes of FPGA implementation with multipliers.
Eugene B. Hogenauer [4] presents a class of digital linear phase finite impulse response
(FIR) filters for decimation (sampling rate decrease) and interpolation. It is very efficient to
use a cascaded Comb filter because it can be easily implemented in hardware requiring no
multipliers.
Patrick Longa [7] presents an area-efficient FIR Filter design on FPGAs using Distributed
Arithmetic. He compares with different way of implementing the FIR filters in FPGA. While
implementing with multipliers it takes more area and is critical for higher order filters. Many
multiplier less techniques were compared, like canonic sign digit (CSD), Dempster-Mclood
method, use of memories and Look-Up tables to store pre-computed values of coefficient
operations (memory based method). He tells Distributed arithmetic as the very efficient
solution for FIR implementation because this algorithm on FPGA permits everything from
bit-serial implementations to pipelined or full parallel versions of this scheme, which can
greatly improve the design performance.
Richard and Gabor [8] presents technical literature on sigma-delta modulator, they also talk
about noise shaping which is central to sigma-delta modulator. The main points that are
observed from his book are
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The modulator output can be decimated by the factor of OSR without the loss of
information since the minimum sample rate at the output of the decimation filter is
2fB, where fB frequency band width.
The procedure of analyzing ∆∑ data using the fast Fourier Transform F. This step is
necessary to estimate the power spectral density of the ∆∑ data.
The filter has to cut off at faster rate around fB than the NTF of the ∆∑ the modulator
rise, this is to ensure very little out-of-band noise is left unsuppressed around f=fB
after decimation.
The gain response should be flat around fs/OSR, this guaranties that the folding noise
of the noise from frequency bands around fs/OSR, 2fs/OSR etc, after decimation adds
little to the in-band noise.
Steven [1] presents basic concept of understanding of modulator and decimation in his
book. Some of the very important concepts that are absorbed from his book are listed below
To get a SNR of 120 dB ,it is necessary to have an Over Sampling Ration (OSR)
above 256 for sigma-delta modulator
Better performance can be obtained by using the filter that is represented by a product
of sinc function.
Order of the filter should be one more than the order of the modulator and the penalty
for using this class of decimation is typically less than a 0.5-dB increase in noise.
Droop in the frequency response of the filter at the edge of the signal band. As the
frequency, ratio decreases droop increases
The aliasing distortion is the most dominant design parameter because amplitude
distortion and noise penalty can be repaired by following FIR stages, where as
aliasing distortion cannot be repaired
Jacab Baker [9] presents the art of designing decimating filters and implementation in
hardware, some of the important points that he has discussed
a) It is highly desirable to design a CIC or sinc filter without droop
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b) Sinc filter is ideal for removing the modulation noise
c) Sinc filter response is not monotonic
d) For single stage CIC difference between the main lobe and first side lobe is around
13.5dB and need to cascade averaging filters to get large amount of attenuation at
frequencies above fs/K, where K is the decimation factor.
Uwe Meyer-Baese [5] presents the technique of implementing CIC filter and FIR filter in
FPGA some of the important points discussed by him are
a) A three stage CIC has three integrator, one decimation part and three-comb section.
b) Max-Bit growth in the CIC can be calculated and while implanting this has to be
used to avoid over flow.
c) Since the comb section is two’s compliment system, it will automatically
compensate for the integrator over flow.
d) Amplitude distortion in CIC can be corrected in the cascaded FIR compensation
filter, but the aliasing distortion cannot be repaired.
2.3 Summary of literature review
It is impossible to implement FIR filter as a single filter in hardware
The proposed architecture consists of two stages – one Cascaded Integration Comb
filter followed by FIR filter.
To get a SNR of 120 dB ,it is necessary to have an OSR above 256
Better performance can be obtained by using the filter that is represented by a
product of sinc function.
Order of the filter should be one more than the order of the modulator and the
penalty for using this class of decimation is typically less than a 0.5 dB increase in
noise.
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Droop in the frequency response of the filter at the edge of the signal band. As the
frequency, ratio decreases droop increases
The aliasing distortion is the most dominant design parameter because amplitude
distortion and noise penalty can be repaired by following FIR stages, where as
aliasing distortion cannot be repaired
Explains the implementation of Distributed arithmetic in FPGA, requirement of
memory increases with increase in order (b) of the filter (2b), if memory based
implementation is used.
2.4 Design specification and block diagram
The specifications of the decimation filter are dependent upon the overall
specification from the sigma-delta converter.
Table 2.4: Specification of sigma-delta data converter
Parameter Symbol ValueSignal Band width BW 100HzSampling Frequency Fs 62.5KHzOver sampling Ratio for 200Hz
OSR 312
Number of bits in modulator bit stream
Bmod 1
Number of bit in output of filter
Bout 20
Table 2.4 shows the overall specification of Delta-Sigma converter. To get an SNR of
120dB, it needs OSR of 256 and above. Based on available crystal frequency (4 MHz)
sampling frequency of modulator is fixed as 62.5 KHz. The overall characteristics of the
decimation filter is as given in Table 2.5
Table 2.5: Over all characteristics of the decimation filter
Parameter Symbol ValuePass band Fp 100Hz
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Stop band Fstop 200HzSampling Frequency Fs 62.5KHzPass band ripple Apass 0.00005dBStop band ripple Astop 120dBDecimation factor Df 100Down-sampling Frequency Fds 625Hz
The Block diagram of the Decimation Filter based on literature survey and Design
specification of the Sigma-delta converter is shown in Figure 2.5
Figure 2.6: Block diagram of decimation FIR filter
Selecting 62.5 KHz as the sampling frequency of modulator is because of the reason
that we can directly derive this frequency from 4 MHz crystal. The sigma-delta modulator
produces a single bit stream at the rate of 62.5 KHz and because of this reason first stage of
decimation filter (CIC) reads the input at the rate 62.5 KHz and performs a decimation of 25
and obtains an intermediate frequency of 2500Hz. Based on the intermediate frequency and
order of the filter, decimation factor for first stage FIR filter is fixed to 4 and the output
sampling frequency of the filter is 625Hz. Since the resonance frequency of the inertial
navigation system is 1 KHz. Because of this reason output of the decimation FIR filter will
be at the rate of 625Hz.
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2.5 First stage cascaded comb filter
The first stage CIC is easy to implement in hardware, requiring no multiplications and
it can be used to decimate the data by a large factor. One drawback of this filter is droop in
the pass-band due to sin(x)/x response of the filter. The specification of the CIC filter is
shown in Table 2.6. Decimation factor for the CIC filter is fixed 25 based on the requirement
of the intermediate frequency and order is one more that the sum of orders of sigma-delta
modulator and MEMS accelerometer sensor.
Table 2.6: Cascaded integrator comb filter
Parameter Value Decimation factor 25Number of sections 6Differential Delay 1Fs 62.5Khz
2.6 FIR filtering
Table 2.7 shows the FIR requirements of the filter.
Table 2.7: Requirements of FIR filtering
Filter parameter FIR filter
Sampling frequency (Fs) 2500 Hz
Pass band frequency (Fpass) 100Hz
Stop band frequency(Fstop) 440Hz
Pass band Max ripple
(Apass)
0.00025 dB
Stop band attenuation
(Astop)
120 dB
Order of the filter 47
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2.7 Summary
Decimation filter takes the 1-bit data stream that has a high sample rate and
transforms it in to a 20-bit data stream at a lower sampling rate. The specification of the
decimation filter is delivered from specification of modulator section and application. It is
not possible to implement the decimation filter as a single filter in hardware due to order of
the filter, so two stage architecture is selected (CIC followed by FIR stage) to implement in
hardware. The advantage of CIC filter is that it is easy to implement in hardware because it
does not require any multiplication. The FIR filter is implemented with the concept of
distributed arithmetic which performs well in FPGA implementation. Chapter 3 discusses
about problem definition, project objectives and methodology followed for execution of this
project.
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3 – Problem Definition
3.1 Problem definition
Because of the use of over sampling in sigma-delta modulators, the need arises for
changing the sampling rate of signal, decreasing it to Nyquist rate. Thus, the high resolution
can be achieved by the decimation (sample reduction). Such sample reduction can be
achieved employing high precision FIR filters. Thus design and implementation of
decimation filter for sigma delta modulator as per the specification is very important for the
performance of data converters.
3.3 Problem statement
To design and implement FIR filter using distributed arithmetic algorithm for Sigma-
Delta Modulator on FPGA
3.3 Project objectives
To review literature on architectures for decimation FIR filters for sigma-delta modulator
To arrive at design specifications of the DA-FIR filter based on sigma-delta modulator
To develop a MATLAB model of the decimation FIR filter based upon derived specifications
To model and simulate the hardware for DA-FIR filter
To implement and verify the Decimation FIR filter on FPGA
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3.4 Methodology adopted to meet the objectives
Literature review on application of FIR Filter in Sigma-Delta modulators is carried
out by referring journals, books, manuals and related documents
Literature review on FIR filter designs using distributed arithmetic algorithm (DA-
FIR) is carried out by referring journals, books, manuals and related documents
Design specifications for DA-FIR filter is arrived at based on application and
reviewed literature
Suitable architecture for DA-FIR filter is identified as per the specifications and
reviewed literature
Reference model for decimation-FIR filter is developed based upon identified
specifications using MATLAB
Hardware for DA-FIR filter is modeled in HDL and simulated using ModelSim
HDL test bench is developed for verifying DA-FIR filter and simulated using
ModelSim
The hardware model is optimized to meet the design specifications
The HDL model is synthesized using Xilinx-ISE
A test environment is developed for verifying decimation FIR filter on FPGA
The decimation-FIR filter is implemented on FPGA and the outputs is verified with
ModelSim results
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4 – Hardware Modelling and FPGA Implementation of FIR Filter
The Hardware model of the FIR filter is designed using Xilinx-ISE and simulations where
performed using ModelSim. The hardware model requires algorithm which can be
implemented in hardware form. The following section discuss about designing, simulation
and testing of hardware model of decimation FIR filter for FPGA.
4.1 Design of hardware model
The design of the Hardware model for decimation filter is subjected to FPGA
and sigma-delta modulator specification. Following are the some of the important points that
are considered while designing the hardware model or block.
Algorithm selected should consume less area and should fit in targeted FPGA
Selected algorithm should use all power reducing technique , so that design
consumes less power in FPGA
Algorithm should meet all the specifications of Decimation FIR filter (Digital
section of Sigma-Delta converter)
Hardware model architecture for decimation filter
The hardware model for decimation FIR filter consists of following blocks
Clock divider
Cascaded COMB filter
FIR filter
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Figure 4.1: Hardware model architecture of FIR filter
The Figure 4.1 shows the hardware model architecture of decimation FIR filter;
following are the port requirements of hardware model.
INPUTS:
Clk – 4MHz form crystal oscillator
Rst – asynchronous Rest signal
Xin- Output of the sigma-delta modulator at the rate of OSR clk
OUTPUTS:
FIR1_yout – 20-bit digital output
FIR1_out -Output indicator
OSR clk - OSR clk output for modulator section
The system clock of the design is 4MHz; the clock divider module performs the
action of dividing the clock in to OSR clk of 62.5 KHz and another clock of 2MHz for the