Rémi CORNAT (IN2P3/LPC) - Review feb’05 Preshower FE Board design R. Bonnefoy, G. Bohner, C. Cârloganu, E. Conte, R. Cornat, E. Delage, J. Lecoq M-L. Mercier,

Rémi CORNAT (IN2P3/LPC) - Review feb’05

Preshower FE Board design

R. Bonnefoy, G. Bohner, C. Cârloganu, E. Conte, R. Cornat, E. Delage, J. Lecoq

M-L. Mercier, P. Perret

[email protected]


Analogue receiver & digitization

4Rémi CORNAT (IN2P3/LPC) - Review feb’05Rémi CORNAT (IN2P3/LPC) - Review feb’05

Analogue receiver & ADC

Q2’01


Prototype

Constraints– 1 cm height per channel

64 channels/32 cm

– EMC

Noise σ=0,8 mV lowered to 0,4 mV

PCB hierarchical block– CMS 0805– AD9203– Compact placement

– Ground plane– Signal diff. pairs– Diff. clock


New analogue module

Refined component placement

Compatible for both ADC multiplexing and direct connection to Fe_PGA

Optimized differential signal traces

Q4’03


Digital processing


Digital processing

UUU nncorr 1

8 bits parametersOptimized operators sizes4 pipe-line steps

Offset [0..255] Gain = 1+ G/512, G [0..255] Alpha = A/512, A [0..255] Trigger threshold [0..255]


Data processing Design Options

Fe_PGA ‘S’ version– AX1000 pga

ASIC + Fe_PGA ‘A’ version– AX250 pga– 2 ASICs / pga– Multiplexed ADCs (80 MHz)

Both are using LAL L0 readout ECS interfaces are LPC made

The current prototypeimplements the 2 ways :32 channels with ASIC32 channels without ASIC


General architecture

I2C1I2csl7b_2

ECS1Psfeeecs_protocol_34_e

rr

STOCKAGE16B4VHamming_partiel4voies4a16

DECODEURHamming_22_16_3_decoder

PIPELINEBYPASSTmr_registerr

GENDMUX

PIPELINE1pipelineced




ALGO1Psdataalgo_bp

ALGO2Psdataalgo_bp

ALGO3Psdataalgo_bp

ALGO4Psdataalgo_bp

TV1Flags_register

TV1Flags_register

TV1Flags_register

OR

TVERRTmr_tv

ALGOETHAMMING

Muxdreg

Error bit

Error flags

ECS data

Load command bits and data dispatching

Pipeline length bypass

Error bits

Algo. param

eters

80 MHz Multiplexed data

40 MHz data

Trig_out

Data_out

Trig_out

Trig_out

Trig_out

Data_out

Data_out

Data_out

Communication bus (i2c)

PHY

protocol


HammingFor parameters registers

load_ecs

22 bits words

– 16 data bits– 5 hamming bits– 1 global parity bit– Loaded by 8 bits slices

from I2C 1 bit error correction 2 bits error detection Decoder shared among 12 22b

registers

– Cyclic check and correction using a counter

Hamming decoder

tmr counter

offset gain alphaetthreshold

222222

22

22

2222

Bits Mapping Bits Mapping

Half channel synchronization

Half channel synchronization

offset1 offset2

gain1 gain2

alpha

threshold

88 88 8 8

88

offset gain

synchro

mux

errcod 2

Bits Mapping


ASIC version

4 channels digital processing I2C interface SEU Autocorrected register bank

– Triple voting– EDAC Hamming coding

Saves a lot of flip-flops Needs combinational logic Exists in 13/8 or 22/16 versions

6.25 mm² / QFP80 package

comb seq

Hamming 624 230

3 voting 980 576

AMS CMOS 0.35µ / CSI Same HDL code used for

both ASIC and PGA

Q1’03


ASIC test board

40 MHz digital inputsfrom memory board(40 bits)

PQFP80 test support

PGA : 80 MHz muxI2C master &Chip emulation

ADC@80MHzTest area

Q3’03


Technology choice : ASIC vs AX

CAD (HDL & Sim) : ASIC ~ AX Performance : ASIC > AX PCB : ASIC > AX

AX allows to freeze design later– Wait for ECS, SEQ, etc… (and then tests)– More low level HW test before production

ASIC cost slightly increase as AX cost decrease– ~ same cost on Q4’2004

Final choice : AX

03 04

AX

ASIC

cost


Trigger part


L0 trigger

Link ECAL to PS/SPD

Trigger data = 1b/ch


Overview : trigger functions

Interconnection between :– SPD and PS (boards corresponding to the same cells) :

24m serial LVDS– Adjacent PS board (T/B : lvcmos 40MHz, R/L : serial LVDS)– ECAL and PS (boards corresponding to the same cells) :

serial LVDS– PS and ECAL validation board : serial LVDS– PS and SPD control board (multiplicity) : serial LVDS

Cells mapping issue : geographic algorithms 2x2 cluster search algorithm for SPD an PS trigger

bits


Trigger task

Two cluster addresses sent by ECAL– One per half PS FE Board

SPD data deserilization– Received in FE PGAs : sent to DAQ– Centralized into TRIG PGA

Neighbours algorithm– Transmission between boards– Simple multiplexor…– Need one Tclk

Algorithm validated (Q1’01 prototype) SPD Multiplicity

– Adder tree Migration from AX500 to APA450

– Flash allow design upgrade and bug fix (detector mapping )

– AX/APA HDL code ready but not tested


Timing model


Clock and timing


Logical clock tree

Clk taken from the backplane

No LVDS RT fan-out found…

– Delay chips and LV048 – Multidrop LVDS (Up to

2*4 LVDS buffers per branch)

Tree leaves are LVTTL Tree trunk and

branches are LVDS

Delay chips allow to set– VFE (start of analogue

integration time)– VFERST (phase of VFE rst

signal)– ADC (analogue signal

sampling time)– ADC’ (ADC data sampling

time into FE_PGAs)– Sampling time of serial

LVDS data (SPD, ECAL, TOP)


Clock model


Clock distribution (schematics)

4*16 ADCs

Global clk

8 FE1 TRIG1 SEQ1 GLUE

4 serializers

SPD

VFE

ADC’


SEL & SEU protection


Radiation test of the Preshower electronics

Have been tested at Ganil in April 2003

– Front-End electronic ADC (AD9203): 4

chips Operational Amplifier

(AD8132): 4 chips– Very-Front-End

electronic New version of the

ASIC integrator: 2 chips with 1 complete channel each

Active PMT Base (AB): 2 basis with 2 HV transistors each

No cumulated dose effects– 26 krad for AB, ASIC and OA– 52 krad for ADC

Some SEL observed for ADC– Not destructive

The 4 ADC have been tested getting back to laboratory

– They all work perfectly Current in the ADC increased

“only” by a factor 3 to 4– Holding the power supply voltage in the

required range

– Estimation : 10 SEL per year– Use of delatchers

No SEL for AB, ASIC and OA


Triple voting

Antifuse PGA (FE), RT flash PGA (TRIG, SEQ, GLUE)

Triple voting technique :– Used on control bits and FSM state register– Used on RAM address counters– Hamming counters developed (HDL) – Error bits are summarized (logical OR)


EDAC Hamming coding

22 bits words– 16 data bits– 5 hamming bits– 1 global parity bit

1 bit error correction 2 bits error detection Decoder can be shared

with many registers– Cyclic check and

correction using a counter

Saves a lot of flip-flops Needs combinational logic Exists in 13/8 version

Synthesis results (4 channels) :

comb seq

Ham 624 230

tv 980 576


Power supplies

Use of -3.3 and 3.3 V only– Not compatible with ECAL/HCAL boards

including CROC– If possible add jumper to select an

auxiliary 5V power supply for PS CROC or 5V aux for everybody

– Anyway 6 independent PW supply blocs are available (3 modules)

– And SPD controller ???

1.5 V made with LHC regulators

SEL sensitive components are protected with self switch-off current limiters

-3. 3 1 A / board (ECAL -5V)

+3.3 D 5 A / board (ECAL 3.3V)

+3.3 D

+3.3 A (ECAL +5V)

+3.3 A

+5 Vfree1 Aux for PS CROC


Main characteristics

Current limiter – (2A : MAX869, 1.2A : MAX890, – 0.5A : MAX891,…)

2.7 to 5.5 V Switch resistance : 90 m typ.@3V Programmable current limit (external resistor)

– Minimum limit is 0.2*Imax (240 mA for MAX890)

Fault indicator Enable input (forced switch off is possible) Thermal shutdown


Delatcher with time constant

MAX890L

74LVC010


Radiation hardness of MAX8xx

MAX869L was tested at GANIL by LAL (thanks

to F. Machefert) MAX869L & MAX892L was tested by AMS

– Same technology as MAX890L, no SEL– http://ams.cern.ch/AMS/Beamtest/note_2.pdf

SN74LVC10 tested by ATLAS

http://sunset.roma1.infn.it/muonl1/rpc-rha/atlas_docs/test_reports/SN74LVC10A_SEE.doc


2004 prototype


PCB

Sent to manufacturer on 30/04/04

Came back on 18/05 !

Uses SEQ and GLUE unchanged from LAL versions

HDL code designed (95 %)

Fe

Trig

Seq

Glue


PCB

Class 6 - 12 layers

Fe ‘A’

Seq

GlueA

SIC

s

AD

C

Delay chips

Regulators

LVDS clk& glob. Sig

network


PCB

Class 6 - 12 layers

Fe ‘S’

Trig

Seq

JTAG & PRBconnector

VFEclk & rst

LVDS 21:3SERDES


Low level tests


Low level tests environment

PCB available since mid may’04, home cabled Dedicated VC++ SW Performed WITHOUT GLUE_PGA

– No SPECS– But I2C signals connected directly on the PCB through LVDS/TTL

converters I2C generation thanks to PCI SPECS MASTER board (and

embedded SPECS SLAVE)– Unfortunate limit to 26 words frames making FE_PGA full test

impossible– ACK is not checked– Use of an USB based generator designed for L0DU

Delay chip not readable (current version) SEQ_PGA since mid aug’04 WITHOUT CROC (jan’05)


ECS issue

Need to R/W data processing parameters

– ECS HW&SW based on USB (specially designed for L0DU)

– Generates I2C– Overcomes SPECS limits– Tested with AX1000– First version designed by a

student Q1’04– New HDL version Q4’04

Stand alone ECS for debug purpose (Laptop)

ASIC tests fully done !

USB

I2C

prototype

Q1’04


Test bench

Prototype and productions tests VME and SPECS (PCI master) controlled Analogue stimuli from AWG + fan out (64)

Designed to generate and capture every FE board I/O (analogue & digital data, TTC, ECS)

– Fully autonomous test (no need of a CROC,…) Up to 2^16 BX patterns (digital RAMs) Fully synchronous (1 central clock generator, TTCrq

compatible soon)

Designed as a simplified backplane

(2 slots : FE & CROC)– RJ45 & LVDS links

from pattern generator to memory board

– Include lvds 21:3 serdes and logic analyzer probe connectors

Tests with or without CROC are allowed


Set up

AX1000

AX250

2 ASICs

SEQ


Tests

Board level signals– Clocks (LAL delay chips) & global signals– Signal integrity– I/Os (analogue, L0, rst, SPD deserializer, CROC serializer)– I2C but no ECS

Data processing ASIC Data processing PGA Injection RAMs (FE & TRIG)

Stringent HDL simulations ensures (most of) behavior error free PGAs (design is not too complex)…


ASIC & AX250 tests (1)

Specially designed AX250 with custom Acquisition RAM (no SEQ/CROC)

Intensive tests done on ASIC– R/W parameters– Data processing– ADC demultiplexing (80 MHz)

AX250 core functions validated (I2C layers, ASIC interface, SPD data)

PCB design OK

No use of a trigger

Partially tested due to SPECSlimitation (26 bytes/I2C frame)


ASIC & AX250 tests (2)


AX1000

Same HDL code as for ASIC (data processing) Includes

– injection RAM (PS & SPD, 256 words deep)– L0seq LAL interface to SEQ (std acquisition)– Custom acquisition RAM (512 words deep)

Trigger controlled 3 trigger shaping options (raw, edge, shaped) TTC controlled Injection/acquisition cycle (test_seq)

– Most of final core functions– Need to be refined

Test beam !

SEQ tests !

• Dedicated SW• I2C R/W : ok (SPECS limited)• ACQ RAM + raw trigger : ok• INJ RAM R/W : ~ok• Prelim. Tests with SEQ

See Cristina’s talk


New layout

P&R fully done– 12 layers, class 6

APA450 as TRIG_PGA

3 DC only 1 test support on one

FE_PGA Connector for

external USB/I2C generator

Individual JTAG/SILEXP connectors for debug purpose


Conclusion

PCB :– Drawing & layout

techniques ok for production

– Global architecture ok– New (final) layout ready

ASIC + AX250– Data processing ok– Not chosen…

AX1000 : – Close to final version with many other functions for test

beam– More long term tests needed

Need to overcome SPECS limitations

TRIG– APA450 migration done– Full HDL simulation– Not tested with CROC


From January 1st 2005:

1 week schematic 7 weeks layout

Review mid February 8 weeks PCB fabrication with components 8 weeks for lab test (May → …) 4 weeks common tests Ready for production in September? 12 weeks production Reception December? Tests

Planning

Rémi CORNAT (IN2P3/LPC) - Review feb’05 Preshower FE Board design R. Bonnefoy, G. Bohner, C. Cârloganu, E. Conte, R. Cornat, E. Delage, J. Lecoq M-L. Mercier,

Documents