Preshower LV Review

CMS Preshower LV Review, 3rd November 2003 David Barney, CERN1

Preshower LV Review

• Overview of presentation– Reminder of Preshower structure

• Electronics architecture

• Geometry

– Baseline LV system• Regulator constraint and usage on different motherboards

• Power-on/off scenarios

• Cabling

• Failure scenarios

– Grounding

N.B. This is a first draft of our LV system!


Preshower Readout & Control Architecture

DCC

Opt

ical

Rec

eive

rs FPGADSP

FED Bus

Readout Path

CCS Module

Opt

oele

ctro

nics

Link Controller

processor

CLK & T1logic

TTCrx

TTCrx

TTCvimodule

Front End Readout ASICs

Front End Control ASICs

Control Path

Clk LV1I2C

DCUIV

I2CCCUCCUCCUCCUCCUCCU

Slow Control & Fast Timing SignalsRe

K chipK chip

K chipK chip

K chipK chip

K chipK chipPACE

ADC

Slow Control

All on-board ASICs are in 0.25m technology – need 2.5V


Preshower Geometry – physical location


Preshower Geometry – envelope


Preshower Geometry – internal structure20cm


Preshower geometry – modules and LaddersMicromodule Building a ladder

Prototype ladder of 8 micromodules 2003

Ladders for 7 and 10micromodules also exist


Preshower geometry – heatsinks & motherboards

Add aluminium heatsinks Motherboard

Ladder completewith motherboardand cables etc.


Preshower geometry – ladders & control rings

A & B = motherboards (MBs)containing DOH

12 control rings / plane1 control ring = max 12 MBs


Regulator Constraint

Could load with more current if we increase Vin (i.e. drop-out voltage increases with irradiation) – but undesirable from a cooling perspective

Limit maximum output current from a regulator to <2 Amps

Load regulation: Vin=5V 4913 Vout vs. neutron fluence, September 2003

0

0.5

1

1.5

2

2.5

3

3.5

0 1 2 3 4 5 6Iout(A)

Vo

ut(

V)

prerad_1

8.00E+12

1.49E+13

7.97E+13

2.12E+14

3.44E+14


Current consumptions from ASICsPACE DCU ADC

analogueADC digital

K-chip CCU LVDSbuf PLL QPLL DOH GOH

230 20 40/chan 100 250 100 65 40 30 110 160

• MB type 0 = 10 PACE + 11 DCU + 5 ADC + 3 K + 3 GOH + control (no DOH) ~5 Amps

•MB type 1 = 8 PACE + 9 DCU + 4 ADC + 2 K + 2 GOH + control (±DOH) ~4 Amps

•MB type 2/3 = 7 PACE + 8 DCU + 4 ADC + 2 K + 2 GOH + control (no DOH) ~3.5 Amps

•Should add ~20% safety margin and ~7% for current used by regulators

•Variation: some type 0 and type 1 MBs contain an additional CCU as a “ring terminator”. At the moment it is unclear if this additional CCU will be powered by the board in question or an adjacent board – for redundancy considerations


Motherboard type 0 – 10 micromodules

GR (GOH Regulator): for GOH + K-chip = 3xGOH + 3xK = 1230mA (1600mA)

AR2 (Analogue Regulator #2): PACE-3, DCU and analogue part of ADC = 4xPACE + 4xDCU + 4xADCanalogue = 1160mA (1510mA)


DR (Digital Regulator): for Control system, QPLL and digital part of ADC = CCU + DCU + LVDSbuf+ PLL + 3xQPLL + 5xADCdigital = 815mA (1060mA)


Total CurrentsAnalogue: 2.9A (3.8A)Digital: 2.0A (2.7A)Total : 4.9A (6.4A)

Red = nominal

(Blue) = +30% margin

DCU used tomonitor LVRs


Motherboard type 1 – 8 micromodules

GR (GOH Regulator): for GOH + K = 2xGOH + 2xK= 820mA (1070mA)



DR (Digital Regulator): for control system, QPLL, DOH and digital part of ADC = CCU + DCU + LVDSbuf + PLL + 2xQPLL + 4xADCdigital + DOH= 795mA (1040mA)

Total CurrentsAnalogue: 2.3A (3.0A)Digital: 1.6A (2.1A)Total: 3.9A (5.1A)

Red = nominal




Motherboard type 2/3 – 7 micromodules

GR (GOH Regulator): for GOH + K-chip = 2xGOH + 2xK = 820mA (1070mA)



DR (Digital Regulator): for control system, QPLL and digital part of ADC = CCU + DCU + LVDSbuf + PLL + 2xQPLL + 4xADCdigital= 685mA (890mA)


Red = nominal




Example power consumptions per control ring

1

234

5

6

Control ring MB0 MB0t MB1 MB1t MB1doh MB2/3 analogue digital total +30%

1 1 1 5 0 2 3 27580 20075 47655 61951

2 4 1 4 0 2 1 30010 21585 51595 67073

3 5 1 1 0 2 0 24250 17280 41530 53989

4 6 0 1 1 2 0 26625 18730 45355 58961

5 3 1 1 0 2 1 20480 14695 35175 45727

6 1 1 5 0 2 3 27580 20075 47655 61951

Currents in mA


Operating sequence• Constraints (some of them!):

– Should power all parts of mixed-mode chips at same time– GOH (on GR) must be powered after CCU (on DR)– Inhibit lines are active HIGH at ≥2.4V (annoying!)– Need to be careful of parasitic powering effects (next slide)

• Inhibit lines– Make a wire “AND” of inhibit signals from DR + ARx and take this to the

outside – will refer to this as the “AND inhibit”– GOH regulator (GR) also inhibited from outsideneed 24 inhibit lines per Control Ring = per LV PSU Ideally want the LV PSU to control these inhibit lines…

• Overcurrent monitoring (do we need it?)– DR is monitored externally; others monitored by CCU …


Operating sequence (cont.)

1. Power is supplied to all boards in a control ring. AND and GR are inhibited externally.

2. AND inhibit is disengaged – control ring comes to life, as do the PACE and ADC chips

3. GOH reset from CCU is asserted, the GR inhibit is released

• Chip can become powered through the clock and draw largecurrents – could result in CCU etc. being destroyed• need to include series resistors on the clock/reset lines inorder to limit the currents – but this needs to be done carefully!

Need to be careful of parasitic powering of chips via i2c lines etc.


Inhibit and overcurrent scheme (cont.)


Use of LV power supplies and LV cabling• Average current for one control ring, including ~30% margin, is ~60 Amps

– Average analogue part, including 30% margin, is ~35 Amps– Average digital part, including 30% margin, is ~25 Amps

• Baseline is to separate analogue and digital supplies at the power supply• According to recent news the proposed LV supply possibilities are:

– 12 x 5A– 6 x 15A– 2 x 50A– 1 x 100A

• Proposal is to use one 2x50A supply for each control ring– 1 channel for analogue; 1 channel for digital+control– Ideally need 24 controllable inhibit lines per supply – is this possible for the

PSUs?? Otherwise we need to build a unit that can communicate with the PSU etc.

– 4x16mm2 conductor for analogue, 4x10mm2 conductor for digital, per supply; - including return conductors

– We have provision for ~50 wires per feedthrough : 24+few for inhibits; + 12+few for overcurrent monitoring, + DCS….

• Granularity of HV can match the LV granularity


Failure scenarios

• Failure = “something” happens to a sensor or one of the chips that requires us to switch it off

• Silicon sensor– Can turn-off groups of 2 sensors at the power supply end (using

jumpers) and turn-off an input to the K-chip – PACE remain operational but in sleep mode

• PACE, ADC or control chip– can only turn-off complete board!– unless problems with the LVDSmux are resolved we MAY lose the

complete control ring!– Can also lose the complete ring if the board in question contains the

ring-terminator CCU

• K-chip or GOL– Will lose the data part of a board– Can maintain the control part


Grounding

• General guidelines– LV supplies are floating– Every sub-detector should be electrically insulated from the others– The lead absorbers (=“structure” in the following diagrams) in the

ES are the most logical pieces to define as “earth”– The ES vessel should be connected to the safety ground

(Protective Earth - PE) at one single point– Each LV return should be connected to PE on the detector side– There should be a voltage limiter (~50 V) between our HV return

(and cable shield) and PE on the supply side– Common return line analogue+digital from hybrid to motherboard– Motherboard layout: if possible confined (power and) ground

planes analogue vs digital


LV,HV connections to PE


Front-end grounding

This scheme is adequate from a safety perspective

PE

Pre-amp groundto Al tile


Powering scheme

VERY large area ground loops! Need to test consequences….Avoiding these would be a major undertaking by CMS

Potential problemdue to differentcable lengths…


Alternative front-end grounding

This scheme is hopefully adequate from a safety perspective

PE

PE1

Pre-amp groundvia C to Al tile


Alternative powering scheme


Summary

• We have tried to develop a baseline LV scheme that has as much flexibility as possible, given certain constraints

• There are some questions that need to be addressed seriously:1. Maximum number of controllable inhibit lines per LV PSU – is 24

possible?2. Parasitic powering of chips via i2c lines etc.3. Details, details, details!

• In the coming months we will try to resolve as many issues as possible, and test a variety of powering/grounding schemes.

• There are many unverified parts of our system (particularly in the grounding scheme). We will not have all the answers before the cables need to be laid in 2004


Backup slides


Token ring tests (cont.)

• 1 board (=no “ring”) runs for ever with no serious problems

• 4 boards in a ring can run for ever (some modifications to the C++ code were necessary to remove “tracker” specifics)

• 4 boards, with one board bypassed (redundancy in operation) powered, runs ok

• As above but with the “bad” board powered down (PD) causes fatal errors – not yet fully understood– Errors reported in the two boards following the one that is powered-down

– The LVDS output lines from the PD board are floating – and the LVDSmux chip is susceptible to noise (no hysteresis pads)

– More tests planned with dedicated boards….

– …and more tests when we get the real system boards

IV

Control Ring

chipset

Control Ring

chipset

A

B

A

BIV

Control Ring

chipset

Control Ring

chipset

A

B

A

B IV

Control Ring

chipset

Control Ring

chipset

A

B

A

B

DOHDOH

IV

Control Ring

chipset

Control Ring

chipset

A

B

A

B


Supplies/channels/feedthroughssupply cable channel feedthrough12 1 1r7 1 1l7 1 2r7 1 2l8 2 3r8 2 3l1 2 4l9 3 5r9 3 5l1 3 6r1 3 6l9 3 7r9 3 7l2 4 8r2 4 8l2 4 9r3 4 9l3 5 10r3 5 10l4 5 11l


R2=2*R1R3=3*R1

I1=I*(18/11)I2=I*(9/11)I3=I*(6/11)

If tot=3*IIr tot=3*I

U1

I3’=I*(5/11)

I2’=I*(2/11)

I1

I2

I3

R1

R2

R3

Power Supply

- +

RL

RL

RL I

I

I

I1=I+I1’=I*(18/11)

U2

U=U2-U1

I1’=I2’+I3’=I*(8/11)


Motherboard type 0 – 10 micromodulesalternative scheme

GR (GOH Regulator): GOH + digital part of ADC = 3xGOH + 5xADCdigital = 980mA (1280mA)



DR (Digital Regulator): for Control system and K-chip = CCU + DCU + LVDSbuf + PLL + 3xK + 3xQPLL = 1065mA (1390mA)



Red = nominal




Motherboard type 0 – 10 micromodulesIf the CCU could be used to control regulators

CR (Control Regulator): control system + GOH = DCU + CCU + LVDSbuf + PLL + 3xGOH = 705mA (920mA)



DR (Digital Regulator): for K-chip, QPLL and digital part of ADC = 3xK + 3xQPLL + 5xADCdigital = 1340mA (1740mA)



Red = nominal




Motherboard type 1 – 8 micromodulesalternative scheme

GR (GOH Regulator): for GOH + digital part of ADC = 2xGOH + 4xADCdigital = 720mA (940mA)



DR (Digital Regulator): for control system, K-chip, QPLL and DOH = CCU + DCU + PLL + LVDSbuf + 2xK + 2xQPLL + DOH = 900mA (1160mA)


Red = nominal




Motherboard type 1 – 8 micromodulesif CCU could be used to control regulators

CR (Control Regulator): control system + GOH = DCU + CCU + LVDSbuf + PLL + DOH + 2xGOH = 655mA (850mA)





Red = nominal




Motherboard type 2/3 – 7 micromodulesalternative scheme

GR (GOH Regulator): for GOH + digital part of ADC = 2xGOH + 4xADCdigital= 720mA (940mA)



DR (Digital Regulator): for control system, K-chip, QPLL = CCU + DCU + LVDSbuf + PLL + 2xK + 2xQPLL = 785mA (1020mA)


Red = nominal




Motherboard type 2/3 – 7 micromodulesif CCU could be used to control regulators

CR (Control Regulator): control system + GOH = DCU + CCU + LVDSbuf + PLL + 2xGOH = 545mA (710mA)





Red = nominal



Preshower LV Review

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