REDUCE VERIFICATION COMPLEXITY IN LOW/MULTI-POWER DESIGNS

Chapter 1

INTRODUCTION

In particular, today’s competitive products demand power-efficient design practices. What does

power-efficient design entail? Designers are using ever-lower voltages wherever practical in a

design, reserving higher voltages for those portions of the design that truly require the additional

power. While power-efficient designs may contain several different voltages, there are often

tens, or even hundreds, of power domains—discrete portions of the design that can be turned on

and off to minimize power usage. Accurate and efficient low-power and multiple-power domain

verification requires both knowledge of the overall system’s power intent and careful tracking of

signals crossing these power domains. The ability to evaluate the interactions of different power

states at the transistor level, where bulk connections, floating wells, and other physical

implementation details can be verified, is critical to avoid latch-up conditions and ensure high

reliability compliance.

Typical hardware description language (HDL) design and checking tools can verify digital

designs at the module level, accurate reliability verification must happen at the transistor level.

Calibre® PERC™ provides a new approach to reliability verification for low-power and multi-

power designs, by leveraging the information contained in the unified power format (UPF) and

applying it to transistor-level designs. The UPF provides a way to annotate a design with the

power and power control intent of that design (including such elements as supply nets, supply

sets, power states, power switches, level shifters, isolation, and retention) that is independent of

any HDL. UPFs are typically used at all levels of the design flow for P&R designs.

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Chapter 2

BACKGROUND

The increasing demand for highly reliable products covers many industries, all process

nodes, and almost all design implementations. To satisfy this demand, reliability requirements

are growing in all market segments. Ensuring these requirements are met requires design

verification that goes beyond traditional design rule checking (DRC), layout vs. schematic

(LVS) comparison, and electrical rule checking (ERC). Small and large process nodes alike are

affected by these requirements, while both system-on-chip (SoC) and full custom designs also

need comprehensive reliability coverage.

In particular, today’s competitive products demand power-efficient design practices.

What does power-efficient design entail? Designers are using ever-lower voltages wherever

practical in a design, reserving higher voltages for those portions of the design that truly require

the additional power. While power-efficient designs may contain several different voltages,

there are often tens, or even hundreds, of power domains—discrete portions of the design that

can be turned on and off to minimize power usage. Accurate and efficient low-power and

multiple-power domain verification requires both knowledge of the overall system’s power

intent and careful tracking of signals crossing these power domains. The ability to evaluate the

interactions of different power states at the transistor level, where bulk connections, floating

wells, and other physical implementation details can be verified, is critical to avoid latch-up

conditions and ensure high reliability compliance.

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Power-efficient reliability requirements apply to both low power/low voltage and high

power/high voltage designs. If there’s a memory cell, high-voltage gate, or other element with

signals that are not directly compatible with the rest of the design, the designer must make sure

there is adequate isolation and protection to ensure a design is created that is reliable under all

operating conditions. Level shifters are often used between different voltages to ensure smooth

transitions (Figure 1), while retention cells are often employed to preserve a circuit’s input

values when its domain is switched off.

Figure 2.1: On the left, a level shifter is used to provide a safe transition between differing voltages, while on the right, a retention cell is used to preserve input values.

Designs that incorporate multiple power domain checks are particularly susceptible to

subtle design errors that are difficult to identify using SPICE simulations or traditional physical

verification techniques. These subtle errors often don’t result in immediate part failure, but

performance degradation over time. Figure 2 shows a transistor connected to different VCCs. If

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the VCCs are the same voltage, but in different domains, they may be switching on and off at

different times, leading to reliability issues. This type of error is going to be very difficult to

catch in a SPICE simulation. If VCC2 has a greater voltage than VCC1, the device is at risk for

gate oxide breakdown, a long-term reliability issue.

Place and route (P&R) tools most commonly deal with gate-level blocks. Because verification

in that environment does not go down to the transistor or well level to validate transistor biasing,

problems like the one shown in Figure 2 will not be identified during the P&R process.

Transistor-level power intent verification is a critical need, especially in designs that make

extensive use of IP. SOCs can contain any number of IPs from different providers, many of

which may use different power designs or contain their own internal global signals, and each IP

must be hooked up correctly within the design. Without an understanding of the power intent of

each IP, it’s very difficult to proactively prevent reliability issues (such as power domain

crossing errors) from occurring when the IP is placed into a larger design. In Figure 3, the

voltages internal to the IP block look consistent, but it’s been hooked up incorrectly in the larger

implementation. Also, as stated before, even if the voltages are equal, if they are in different

power domains, they may be switching on and off at different times, leading to additional

reliability issues.

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Figure 2.2: A transistor connected to two different VCCs is susceptible to long-term performance degradation and reliability issues.

Another factor in these designs is the use of thinner oxides that allow designers to use

lower voltage, and subsequently, less power. These desirable effects are offset by the sensitivity

of these circuits to electrical overstress (EOS) issues. In addition, some power domain design

errors lead to eventual oxide breakdown, which results in device failures that occur over time. In

particular, PMOS devices can be susceptible to negative-bias temperature instability (NBTI),

which leads to the threshold voltage of the PMOS transistor increasing over time. This, in turn,

leads to reduced switching time for logic gates, and induces hot carrier injection (HCI), which

then gradually alters the threshold voltage of NMOS devices. Soft breakdown (SBD) also

contributes as a time-dependent failure mechanism, contributing to the degradation effects of

gate oxide breakdown

A transistor-level power-aware checking tool must also be able to statically propagate

voltage values from the various supplies to every node in the circuit to facilitate a variety of

reliability checks. Power-aware checking requires the ability to use the design’s netlist to

recognize specific circuit topologies (such as level shifters, charge pumps, I/O drivers, and other

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structures), and then relate those to the corresponding physical implementation that makes up the

layout, to verify that these specific elements have been included and implemented correctly.

Unlike the foundry DRC decks, the definition of these checks may not all come from the foundry

—some can be tailored to the specific design styles and practices of the designer’s company—so

flexibility and customizability are essential features. Thin oxide gates and high-power

applications require tight controls for voltage and power domains. Many of these issues are

difficult to identify in the simulation space or with traditional physical verification techniques.

Figure 2.3: IPs pose two levels of reliability certification challenges—internal verification, and verification in the context of a larger implementation.

Chapter 3

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CALIBRE PERC: The Next Evolution of Circuit Reliability Verification

3.1 Introduction to Calibre perc

Reliability is a growing concern for integrated circuit (IC) designers, especially in

products such as communications, medical, and transportation, where reliability and

performance are not just market differentiators, but critical components of safe and effective

operation. Many reliability checks are difficult to check using traditional DRC, LVS and ERC

tools, and can potentially affect a wide range of IC designs. Electrostatic discharge (ESD),

electrical overstress (EOS), and latch-up are just some of these complex geometrical and

electrical errors that can result in reduced yield, defect escapes to customers, and delayed

failures in the field.

Advanced reliability verification ensures the robustness of a design both at schematic and

layout levels by checking against various electrical and physical design rules that define IC

performance standards and reduce susceptibility to premature or catastrophic electrical failures.

Calibre® PERC™ is specifically designed to perform a wide range of complex

reliability verification tasks using both standard rules from the foundry and custom rules

created by a design team. Users can insert reliability verification into their existing design

flows with Calibre PERC as part of an integrated Calibre platform for cell, block, and full-chip

verification. Combining rules expressed in SVRF and the Tcl-based TVF language across all

applications provides users with flexibility to meet the specific and evolving needs of their

design teams, while ensuring compatibility with all foundries.

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Contrary to traditional electrical checks using a single device/pin to net relation, reliability

requirements can often only be described by a topological view that combines both circuit

description and physical devices. Calibre PERC’s ability to use both netlist and layout (GDS)

information simultaneously to perform electrical checks that incorporate both layout-related

parameters and circuitry-dependent checks enables designers to address these complex

verification requirements. In addition, Calibre PERC can employ topological constraints to

verify that the correct structures are in place wherever circuit design rules require them.

Calibre PERC can automatically identify complex circuit topology on a design netlist, either

streamed from the schematic or extracted from the layout. It examines the specific constraints

defined by the design team, whether they are electrical or geometrical. Calibre PERC rule decks

may be easily augmented to provide verification beyond standard foundry rule decks to include

custom verification requirements.

3.2 Advanced Reliability Verification

At all process nodes, countless hours are diligently expended to ensure that our integrated

circuit (IC) designs will function in the way we intended, can be manufactured with satisfactory

yields, and are delivered in a timely fashion while meeting the market need. Traditional IC

verification relies on a collection of well-known and well-understood tools. Design rule checking

(DRC), layout vs. schematic comparison (LVS), electrical rule checking (ERC), parasitic

extraction (PEX), design for manufacturing (DFM) and simulation (most often SPICE and

timing closure) are all used as part of this cohesive verification flow that provides us the insight

required to find and correct any errors or omissions in our design process. Many design errors

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lead to hard failures in manufacturing, and can be readily identified and fixed, like a metal width

that is too small for a process node layer, cells that were incorrectly placed, or shorts across other

elements in the design. Finding and fixing these issues is the mainstay of IC verification. 

3.2.1 The legacy of simulation

SPICE simulation, and the associated parasitic extraction that it uses, plays a vital role in

identifying less obvious errors—those that deal primarily with reliability. Ensuring that you have

the correct simulation vectors to provide sufficient coverage while validating the waveforms or

analyzing messages from your simulation environment can be time-consuming and CPU-

intensive activities, where results often require both expert interpretation and the keen eye of

someone who understands the subtleties of each particular design. 

3.2.2 Finding scalable alternatives

Whichever Greek philosopher first said that necessity is the mother of invention must

have foreseen the challenges that the IC industry would one day face. Time and again, when

faced with a new set of requirements not addressed by existing tools, engineers have leveraged

their imaginations to create innovative solutions, designs, and process flows. 

The same is true for reliability verification. With larger designs, smaller process nodes,

and the increased pressure on time-to-market schedules and productivity targets, many design

teams are turning to new alternatives that provide critical advantages over existing tools:

a simple-to-use environment for the designer and verification engineer,

fast runtime (that can scale to the full chip),

a cohesive platform that is able to validate a wide range of issues.

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One tool that has found a strong role in reliability verification is Calibre® PERC™. With its

ability to evaluate both the logical intent and physical implementation of the design, Calibre

PERC provides a unique and powerful reliability verification platform not previously available.

While there are many applications where Calibre PERC technology is successfully leveraged,

one of the most common uses is the automated identification and resolution of typical reliability

design challenges:

Electrostatic discharge (ESD)

Electrical overstress (EOS) and power intent

Voltage-aware DRC

Many of these topics may be quite familiar to you, or perhaps you already have solutions

in place today to help with these issues, but let's go through them one at a time to provide

a broader understanding for all. 

3.2.3 Electrostatic Discharge

Designers have always needed to ensure that designs are robust from an ESD perspective.

To provide that surety, they need to know what structures the design requires to protect pins

from an ESD event, and they need to make sure that the implementation of those structures is

correct. They also need to verify that the design complies with the topology rules (that is, the

correct combination of protection devices are in place), and that these devices are robust enough

to handle the ESD event.

Generalized ESD cells are often designed for this use, but the designer must still ensure

that the cell is placed correctly into the design. Additionally, the chip design may change after

the ESD IP is placed, requiring the designer to adjust the ESD IP to ensure it fits within the new

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design parameters (area, performance, etc.). In these situations, it is essential to validate the

philosophy of the ESD intent, not just check that the ESD IP has remained intact and unchanged.

ESD specialists are often called upon to provide custom solutions for each design, while keeping

an eye out for known issues and previous concerns. The best IP in the world can be compromised

by a simple implementation oversight.

While never an ideal solution, many designers have always relied on visual inspection

and manual methods to evaluate the accuracy of the implementation of ESD structures. The large

number of pin pairs in today’s devices makes this solution a daunting, if not impossible, task.

The designer simply can’t select a “typical” connection and evaluate just a few; rather, every

reasonable combination must be evaluated. This challenge was one of the catalysts that led to a

rethinking of how ESD structures are evaluated.

Calibre PERC can automatically select and analyze all of the required combinations.

For schematic checking, the rules are directed more towards verifying the presence of the

appropriate protection schemes from a topological perspective. Users can perform checks on

circuitry directly connected to pads, as well as checks on the ESD network. For layout checking,

the rules focus on verifying the point-to-point parasitic resistance between the pad and the ESD

device, checking current density between pad and the ESD device, detecting pmos/nmos devices

sharing the same well, detecting pmos/nmos field oxide parasitics, detecting latch-up issues, and

more.

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2.3.4 EOS and power intent

Designs that incorporate multiple power domain checks are particularly susceptible to

subtle design errors. Often, these subtle errors don’t result in immediate part failure, but

performance degradation over time. Effects such as Negative Bias Temperature Instability

(NBTI) can lead to the threshold voltage of the PMOS transistors increasing over time, resulting

in reduced switching speeds for logic gates, and Hot Carrier Injection (HCI), which alters the

threshold voltage of NMOS devices over time. Soft breakdown (SBD) also contributes as a time-

dependent failure mechanism, contributing to the degradation effects of gate oxide breakdown.

Transistor-level power intent verification is a critical need, especially in designs that

make extensive use of IP. The IP must be hooked up correctly within the design. Thin oxide

gates and high power applications require tight controls for voltage and power domains. Many of

these issues are difficult to identify in the simulation space or with traditional PV techniques. 

Power-aware checking requires the ability to use the design’s netlist to recognize

specific circuit topologies, such as level shifters, I/O drivers, and other structures, and then relate

those to the corresponding GDS geometries that make up the layout, to verify that those specific

elements have been included and have been implemented correctly. Unlike the foundry DRC

decks, the definition of these checks do not all come from the foundry, but must be tailored to the

specific design styles and practices of the designer’s company, so any tool performing this

function must be highly flexible and easily programmable. A transistor-level power-aware

checking tool must also be able to statically propagate voltage values from the various supplies

to every node in the circuit to facilitate a variety of EOS checks.

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For example, one common problem for designers trying to debug power violations at the

transistor level with simplistic tools is a lack of knowledge of the intention (the functionality) of

the circuit where the violation is found. Simply checking for transistors connected to multiple

domains results in a large number of false errors at the boundary between domains, where level

shifter structures intentionally include transistors exposed to both low and high voltages. A

power-aware checking tool like Calibre PERC can prevent such false errors by using an

automated circuit recognition technique to identify particular topologies. The circuit recognition

functionality within Calibre PERC uses the SPICE syntax as an easy way to define complex

circuit structures. Whenever power violations are detected in enable-LS, NAND or NOR

structures, false errors can be quickly waived using topological recognition.

Additionally, the unified power format (UPF) provides a way to annotate a design with

power intent that is independent of any hardware description language (HDL). It is typically used

at all levels of the design flow. A UPF specification at the register transfer logic (RTL) level

defines the power architecture of a given design, and drives synthesis and place-and-route to

achieve correct implementation. In automated reliability verification, using the same UPF

specification for transistor level physical verification ensures the original power intent is

preserved with the final implementation.

UPF specifications can be leveraged as an integral part of Calibre PERC’s understanding

of power intent. Along with the design layout data and verification rule deck, Calibre PERC

examines the UPF definitions of supply networks (consisting of power switches, supply ports,

and supply nets) and checks each supply port’s supply states and its connected supply net. Most

13

importantly, it analyzes the power state tables defined in terms of these states to ensure it

captures the legal combinations of supply voltages in the entire design. With integrated support

for UPF, Calibre PERC can automatically assign voltages based on a design’s power intent,

greatly improving verification coverage and robustness.

3.2.5 Voltage-aware DRC

For smaller process nodes and high reliability designs, the spacing requirements between

nets vary as the nets traverse through the design. The required spacings are dependent on the

operating voltage ranges, and devices operating at different voltages must be properly protected.

For example, many designs have high voltage areas, such as flash memories, that are particularly

susceptible. Designers must identify vulnerable nets and devices, and perform the appropriate

spacing and guarding checks on the layout. With traditional verification methods, this means

creating physical layout markers to perform voltage-aware DRC.

Using its novel circuit topology-aware voltage propagation capability, Calibre PERC can

automatically perform voltage analysis and apply the results against the schematic or extracted

layout netlist. Target nets and devices for the voltage-aware DRC checks are selected from the

layout through the direct integration of netlist-based voltage analysis, using either vectored or

vectorless static voltage propagation. The voltage-aware DRC rules are then applied to the

selected layout objects. Such analysis and verification is used to identify areas of the design at

risk for time dependent dielectric breakdown (TDDB).

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3.3 Multiple Power Domains

Low-power and multiple-power verification requires system knowledge and careful

tracking of signals crossing power domains. Calibre PERC can identify signal lines crossing

directly from one domain to another in designs that require different voltages for multiple

domains. It can also verify additional ERC configurations between multiple power domains,

making it equally easy to verify the layout or the schematic for early detection, and avoid silicon

failure.

3.4 Post-Layout Verification

Transistor placement and design interactions can have a significant impact on design

robustness. Such interactions include:

Point-to-Point resistance (P2P)

Current Density (CD)

Voltage-Dependent DRC

Hot gate/diffusion identification

Layer extension/coverage

Device matching

Post-layout verification can incorporate complex geometrical parameters into Calibre

PERC checks, combining both electrical and geometrical data in a single verification step. In

addition, rather than running verification on an entire design, Calibre PERC’s topological

capabilities enable users to quickly and accurately check specific sections of designs for these

types of issues.

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3.5 Comprehensive Reliability Solution

Accurate and repeatable reliability verification is now a critical capability. Calibre PERC

is the only comprehensive solution capable of verifying geometrical, electrical, or combined

constraints. As part of the Calibre platform, it also integrates easily into your existing signoff

flows, with comprehensive debug provided by Calibre RVE. Calibre PERC provides an easy-to-

use, automated and programmable verification solution for circuits on both the schematic and

layout side, ultimately reducing cost and time to market, while providing the diagnostic insight

to help you improve yield and device reliability.

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Chapter 4

TRANSISTOR-LEVEL POWER INTENT VERIFICATION WITH CALIBRE PERC

While typical hardware description language (HDL) design and checking tools can verify

digital designs at the module level, accurate reliability verification must happen at the transistor

level. Calibre® PERC™ provides a new approach to reliability verification for low-power and

multi-power designs, by leveraging the information contained in the unified power format (UPF)

and applying it to transistor-level designs. The UPF provides a way to annotate a design with the

power and power control intent of that design (including such elements as supply nets, supply

sets, power states, power switches, level shifters, isolation, and retention) that is independent of

any HDL. UPFs are typically used at all levels of the design flow for P&R designs.

A UPF specification at the register transfer logic (RTL) level defines the power

architecture of a given design, and drives synthesis and P&R to achieve correct implementation.

The UPF enables a consistent description of the power intent of a design, and provides power

state tables that describe each power mode of the design. In automated reliability verification,

using the same UPF specification for transistor level physical verification ensures the original

power intent is preserved with the final implementation.

UPF specifications can be leveraged as an integral part of Calibre PERC understands of

power intent. Along with the design layout data and verification rule deck, Calibre PERC

examines the UPF definitions of supply networks (consisting of power switches, supply ports,

and supply nets) and checks each supply port’s supply states and its connected supply net. Most

17

importantly, it analyzes the power state tables defined in terms of these states to ensure it

captures the legal combinations of supply voltages in the entire design. With integrated support

for UPF, Calibre PERC can assign voltages based on a design’s power intent, greatly improving

verification coverage and robustness.

Below figure demonstrates a typical UPF tool flow. The power intent is described at the

HDL/RTL level in the UPF file for the logic design. The UPF file is updated during the synthesis

flow, and again during the place and route process. During verification, Calibre PERC can be

used with either the GDS or LEF/DEF design, or the netlist (prior to physical implementation),

to verify power intent.

While traditional UPF flows do not validate the final transistor implementation, especially for

well and bulk connectors, reliability checking tools such as Calibre PERC can use the UPF’s

description of power intent to validate power and reliability requirements at the transistor level

to provide a comprehensive and deterministic reliability verification strategy for SoCs.

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Figure 4.1: Typical UPF flow

In both custom/analog (which is typically not implemented in HDL designs) and P&R

design flows, understanding how signals cross multiple power domains in the design is

paramount to ensuring robust reliability. With its comprehensive view of the design, Calibre

PERC is able to leverage design flows with or without the UPF to understand the power intent

19

down to the transistor level, then apply reliability verification at the transistor level. Multiple

power and voltage domains can be automatically traced to provide a complete picture of how the

design will interact. Designers can validate design intent for any number of design scenarios,

such as ensuring low-power rules are being honored, or that routing has been correctly

implemented in the design. Specifically for low-power designs, Calibre PERC can ensure that

level shifters are in place, that the correct voltages are tied to the devices, and that the correct

protection circuitry is in place for transitions from one domain to another.

This transistor-level power intent verification simplifies multiple-power and low-power

verification by enabling a consistent description of the power intent throughout the design

flow. Support for the UPF power state table allows verification of each power mode within the

design, enabling a repeatable, comprehensive, and efficient design reliability verification

methodology using industry standards at the transistor level.

Calibre PERC can also examine all thin oxide transistors of the circuit to catch any

occurrence of a voltage across the device terminals that would lead to gradual oxide breakdown

and device failure. A list of thin oxide transistors is identified by the Calibre PERC rule deck

from the complete transistor list that is automatically detected by Calibre PERC during voltage

propagation.

Some of the more obvious reliability checks are available from foundries in Calibre PERC

rule decks, but specific methodology rule checks and internal best practices should be provided

to augment these rules for complete coverage. The functionality provided by Calibre PERC rule

decks may be easily enhanced to provide verification beyond standard foundry rule decks to

20

include custom reliability verification requirements. Users can insert reliability verification into

their existing design flows with Calibre PERC as part of an integrated Calibre platform for cell,

block, and full-chip verification. Combining rules expressed in the proprietary SVRF and the

Tcl-based TVF language across all applications provides users with flexibility to meet the

specific and evolving needs of their design teams, while ensuring compatibility with all

foundries.

Debugging is a key component of any verification flow. One common problem for

designers trying to debug power violations at the transistor level with existing tools is a lack of

knowledge of the power intent of the circuit where the violation is found. Without a clear

understanding of how the circuit works, debugging often becomes a task bogged down with the

elimination of false errors caused by level shifters and other protection mechanisms that have not

been accounted for. Calibre PERC eliminates these false errors by using a circuit recognition

technique to identify particular topologies used to provide these power domain transitions. For

example, Figure4.1 shows a typical level shift circuit . Simply checking for transistors connected

to multiple domains results in a large number of false errors at the boundary between power

domains, where level shifter structures intentionally include transistors exposed to both low and

high voltages (i.e., systematic violations would be reported on {M2, M3} transistors). However,

if these structures are identified by Calibre PERC as level shifters, these false errors can be

quickly waived.

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Figure 4.2: Unless level shifters are recognized by the verification tool, they can create false errors that slow down the debugging process

Additional sources of false errors are the isolation cells used between OFF and Always-

ON domains. The circuit recognition functionality within Calibre PERC uses the SPICE syntax

as an easy way to define these types of complex circuit structures (Figure 5). Whenever such

violations are detected, these false errors can be quickly waived internally by the tool, using

topological recognition.

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Figure 4.3: Isolation cells between to-voltage domains are another example of false positives that can occur without knowledge of the function of circuit structures

Chapter 5

FEATURES & BENEFITS

23

FEATURES:

Advanced Reliability Verification

Processes the most complex circuit reliability requirements of today’s leading-edge

technologies

Automated Checking

Insert reliability checks into existing design flows for cell, block, and full-chip

verification.

Fully Compatible

Rule decks available from major foundries.

Fully Customizable

Programmable SVRF and the Tcl-based TVF platform provide a highly flexible, user-

configurable tool for fast and accurate development of customized rules.

Netlist-based

Analyzes source or layout SPICE netlists.

Fast Runtime

Proprietary automated hierarchical and logic injection technologies provide a scalable

solution with fast runtimes

BENEFITS:

Improve Design Reliability

Eliminate potential electrical violations that can reduce product life or cause catastrophic

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electrical failure

Improve Design Accuracy

Same trusted device recognition as Calibre nmLVS; part of award-winning Calibre

product line

Zero Risk—Fully compatible with the Calibre platform, Calibre PERC integrates easily

into existing signoff flows.

Reduce Time to Market—Timely execution ensures production schedules are

maintained.

.

Conclusion

25

Accurate and repeatable reliability verification is now a critical capability, both for

advanced nodes and for increasingly complex products being produced at established nodes.

Calibre PERC is the only comprehensive solution capable of providing transistor-level power

intent verification without the need for SPICE simulation on both the schematic and layout side

of your design. As part of the Calibre platform, it integrates easily into existing signoff flows,

with comprehensive debugging support provided by Calibre RVE. Calibre PERC provides an

easy-to-use, automated verification solution for low-power and multiple-power domain designs,

ultimately reducing cost and time to market, while providing the diagnostic insight to help you

improve yield and device reliability.

References

26

[1] Lescot, J., Bligny, V., Medhat, D., “Static Low Power Verification at Transistor Level for SoC Design,” Proc. ACM/IEEE International Symposium on Low Power Electronics and Design (2012), 129-134. Doi: 10.1145/2333660.2333694

[2] Hogan, M., “Robust Reliability Verification Beyond Traditional Tools and Techniques,” SemiWiki.com (May 2013). URL: http://www.semiwiki.com/forum/content/2451-robust-reliability-verification.html

[3] Hamed Abrishami, et al., “NBTI-Aware Flip-Flop Characterization and Design,” GLSVLSI’08, May 4–6, 2008

[4] B.C. Paul, K. Kang, H. Kuflouglu, M. A. Alam and K. Roy, “Impact of NBTI on the temporal performance degradation of digital circuits,” Electron Device Letter, vol. 26, no. 8, pp. 560-562, Aug. 2005.

[5] Hong Luo, et al., “Modeling of PMOS NBTI Effect Considering Temperature Variation,” 8th International Symposium on Quality Electronic Design (ISQED’07)

[6] Jin Qin, et al., “SRAM Stability Analysis Considering Gate Oxide SBD, NBTI and HCI,, 2007 IIRW FINAL REPORT

[7] Medhat, D., “Power-Aware Verification in Low-Power ICs,” Chip Design (Fall 2012). URL: http://chipdesignmag. com/display.php?articleId=5163

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