Rangkaian Sekuensial - wicaksonoupdate.files.wordpress.com · Rangkaian Sekuensial ... The J-K flip-flop works very similar to S-R flip-flop. The only difference is that this flip-flop

Rangkaian Sekuensial•Rangkaian Sekuensial

•Flip-flop

Combinational versus Sequential

Functions Logic functions are categorized as being either

combinational (sometimes referred to as

combinatorial) or sequential.

In the case of a combinational function, the logic

values on that function’s outputs are directly

related to the current combination of values on its

inputs.

In the case of a sequential function, the logic values

on that function’s outputs depend not only on its

current input values, but also on previous input

values.

Sequential Functions

That is, the output values depend on a

sequence of input values.

Because sequential functions remember

previous input values, they are also

referred to as memory elements.

RS Latches

One of the simpler sequential functions is that of an RS

latch, which can be implemented using two NOR gates

connected in a back-to-back configuration

RS Latches

The secret of the RS latch’s ability to

remember previous input values is based

on a technique known as feedback.

This refers to the feeding back of the

outputs as additional inputs into the

function.

RS Latches

RS Latches

RS Latches

RS latch two NAND

D-Type Latches

A more sophisticated function called a D-type

(“data-type”) latch can be constructed by attaching

two ANDs and a NOT to the front of an RS latch

D-Type Latches

D-Type Flip-flops

In the case of a D-type flip-flop (which may also be referred to as a register), the data appears to be loaded when a transition, or edge, occurs on the clock input

A transition from 0 to 1 is known as a rising-edge or a positive edge, while a transition from 1 to 0 is known as a falling-edge or a negative-edge

A D-type flip-flop’s clock input may be positive-edge or negative-edge triggered

D-Type Flip-flops

D-Type Flip-flops Waveform

D-Type Flip-flops with Clear (Reset)

JK and T Flip-flops

T flip-flop doesn’t have any data inputs; the outputs

simply toggle to the inverse of their previous values

on each active edge of the clock input.

Flip Flop

Flip-flops are synchronous bistable devices.

The term synchronous means the output changes state only when the clock input is triggered. That is, changes in the outputoccur in synchronization with the clock.

Flip-flop is a kind of multivibrator. There are three types of multivibrators:

◦ Monostable multivibrator has only one stable state. It produces a single pulse in response to a triggering input.

◦ Bistable multivibrator exhibits two stable states. It is able to retain the two SET and RESET states indefinitely. It is commonly used as a basic building block for counters, registers and memories.

◦ Astable multivibrator has no stable state at all. It is used primarily as an oscillator to generate periodic pulse waveforms for timing purposes.

Edge-Triggered Flip-flops

An edge-triggered flip-flop changes states

either at the positive edge (rising edge) or

at the negative edge (falling edge) of the

clock pulse on the control input.

The three basic types are introduced

here: S-R, J-K and D.

Edge-triggered S-R flip-flop

As S = 1, R = 0. Flip-flop SETS on the rising clock edge

Edge-triggered J-K flip-flop

The J-K flip-flop works very similar to S-R flip-

flop. The only difference is that this flip-flop has

NO invalid state.

The outputs toggle (change to the opposite state)

when both J and K inputs are HIGH. The truth

table is shown below.

Edge-triggered D flip-flop

The operations of a D flip-flop is much more

simpler. It has only one input addition to the clock.

Pulse-Triggered (Master-Slave) Flip-flops

The term pulse-triggered

means that data are

entered into the flip-flop

on the rising edge of the

clock pulse, but the

output does not reflect

the input state until the

falling edge of the clock

pulse.

Data Lock-Out Flip-flops

The data lock-out flip-flop is

similar to the pulse-triggered

(master-slave) flip-flop except it

has a dynamic clock input.

The dynamic clock disables (locks

out) the data inputs after the

rising edge of the clock pulse.

Therefore, the inputs do not

need to be held constant while

the clock pulse is HIGH.

Applications

Frequency Division

Parallel Data Storage

Counting

End of slides