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* Some routines use only first 5 bytes of DBUFRADCVAL RMB 1StepDirn RMB 2
StepPtr RMB 2 * Pointer to items in following tableStepTable FCB %0001000, %0100000, FCB %0010000, %1000000, StepEnd EQU *
Variable Speed Stepper Motor (6)
START:TOP5 LDS #$0047 * Top of User's Stack area on EVB LDD #$0 STD StepDirn
LDD #$8000 STD HDLY
LDAA #$7E * Jump (extended) Opcode STAA PVOC2 * Pseudo Vector see manual text LDX #SV5OC2 * Address of OC2 service routine STX PVOC2+1 * Finish jump instruc to TOF svc
Variable Speed Stepper Motor (7)
LDX #REGBAS * Point to 68HC11 configuration register block LDAA #%0000000 * STAA OC1M, X * Output Compare Mask = 0 for all OCs LDAA #%0000000 * OM2:OL2 = 0:1 STAA TCTL1,X * SET All timers not connected to outputs
LDAA #%1000000 * OM2:OL2 = 0:1 STAA TFLG1,X * Clear any pending,OC2F STAA TMSK1,X * Enable OC2 interrupts CLI * Enable Interrupts
LDX StepPtr * Get our table pointer -> X LDAA 0, X * Get the contents of the table -> Acc A LDX #REGBAS * Get configuration register base address -> X STAA PORTA, X * Store initial Stepper motor position
LDAA #%11111000 STAA OC1D, X STAA CFORC, X
BSET OPTION,x ADPU * Power up the ADC* JSR delay100us * Wait for Charge Pump to stabilise
Variable Speed Stepper Motor (9)
* Start the conversion SCAN=0, MULT=0FOREVER: * Beginning of LOOP-FOREVER LDAA #ADSET * Select ADC input from Port E-4 STAA ADCTL,x * Signal ADC to start conversion
* Wait until conversion doneconvwait: BRCLR ADCTL,x CCF convwait
* Get the input and print it using the BUFFALO Monitor LDAA ADR1, x * Get ADC converted input voltage value
Variable Speed Stepper Motor(10)
PSHA SUBA #$80 STAA ADCVAL * Store for ISR use BPL PlusOne BMI MinusOne LDD #0 BRA StorDirn * If 0, store 0PlusOne: LDD #1 BRA StorDirnMinusOne: NEGA * A = -A STAA ADCVAL * Store for ISR use LDD #-1
Variable Speed Stepper Motor(11)
StorDirn: STD StepDirn
LDAA ADCVAL SUBA #$7F NEGA ASLA LDAB #0 STD HDLY * Speed - save delay PULA TAB * save it (A) in B JSR OUTLHF * output high nybble TBA * restore it to A JSR OUTRHF * output low nybble JSR CRLF * output carriage return - line feed
Variable Speed Stepper Motor(12)
* Clear the TOF to start the delay JSR delay100us
BRA FOREVER * loop forever
Variable Speed Stepper Motor(13)
**** SV5OC2 - Output Compare 2 service routine* Called at each OC2 interrupt.***SV5OC2: LDD HDLY * Get delay time for 1/2 cycle LDX #REGBAS ADDD TOC2,X * Add HDLY to last compare value STD TOC2,X * Update OC2 (schedule next edge) BCLR TFLG1,X $BF * Clear OC2F
LDD StepPtr * X = Table Pointer ADDD StepDirn * 1, 0 or -1 XGDX
Variable Speed Stepper Motor(14)
CPX #StepEnd * If at end of table, then wrap to start BLT NoWrap LDX #StepTable * by Re-Loading the starting address of table BRA StorePtrNoWrap: CPX #StepTable * If before start of table, then wrap back to end BGE NoWrapBack LDX #StepEnd-1 * by Loading the ending address of tableNoWrapBack:StorePtr: STX StepPtr * Save next address LDAA 0, X * A = Next Stepper Value
Variable Speed Stepper Motor(15)
* LDX #REGBAS STAA REGBAS+PORTA * activate next stepper coil
RTI ** Return from OC2 service **
Variable Speed Stepper Motor(16)
* ------------------------------------------------------------------------------------* This subroutine delays (a little over) 100 micro-seconds* ------------------------------------------------------------------------------------delay100us: PSHA * save Accumulator A* * Generate a "short" delay > 100 microsec LDAA #40 * 40 loops for 200 clock cycles at 0.5 micro seconds/clockDELAYLOOP: DECA * BNE DELAYLOOP PULA * restore Accumulator A RTS *
Analog to Digital Converter
• Analog to Digital Converter section of 68HC11
• Requires 32 E-clock cycles to complete a conversion
• 8-bit successive approximation converter.
• Uses Charge re-distribution for manufacturability reasons.
• As it is based upon capacitance it automatically includes Sample & Hold functionality
Analog to Digital Converter
• Analog switches are used to provide ADC internal capacitor switching and input multiplexor selection switching.
• Uses internal charge pump -> 7 to 8V– Provides high gate voltages to operate analog switches -
guarantees low impedance.
– must be enabled (disabled at reset)
– A/D Power Up (ADPU) control bit
– after starting charge pump, must delay 100us before using ADC
Analog to Digital Converter
• Uses clock sources - must be selected
• Four channels are converted in sequence with the results provided in registers
ADC - Input Sample
In the sample phase of the conversion:
VX, the input voltage, is used to charge the bottom plate of the capacitors relative to the VL low reference (top plate).
VX
ADC - Sample
Time is allowed to elapse for 12 cycles, sufficient time for VC, the voltage on the capacitors, to charge to VX - VL.
The charge remains on the capacitors, and the capacitors bottom plate (reference) is shifted to VL.
QH = - 16 Vi (assuming VL =0). Now Vi = - (VX - VL).
ADC - Conversion (1)
ADC - Conversion (2)
In the Successive Approximation phase of the conversion:
The voltage on the capacitors, is re-distributed between the 1 unit capacitor, and the VH reference voltage.
The ratio of capacitance determines Vi = (VH/VL) CSEL/C1.
The resulting comparator input voltage is set reflects the input
Resistive losses and timing are ignored to simplify analysis.
ADC - Conversion (3)
Starting with the 8 unit capacitor (MSB), it is switched VH.
The charge is Q = 8 (VH - Vi) + 8 (VL - Vi).
Q = 8VH - 16Vi assuming Vi = 0.
The ratio of capacitance determines Vi = (VH/VL) CSAR/C1.
The resulting comparator input voltage is set reflects the input ratio.
If the VX < 8/16 (VH - VL) then Vi > VL and the comparator will output a 1. C8 is set to VH, and a 1 is saved in the MSB of the Successive Approximation register (SAR).
Conversely if VX > 8/16 (VH - VL) then the comparator will output a 0. C8 is set to VL, And a 0 is saved in the MSB of the Successive Approximation register.
ADC - Conversion (4)
Next the 4 unit capacitor (MSB), the capacitor is switched VH.
The resulting comparator input voltage is set reflects the input ratio.
And the SAR will save the value of the next most significant bit.
The ADC continues through the rest of the bits until all capacitors have been set and the SAR holds the value of the conversion.
Upon conversion completion:
VX = (VH - VL) x (SAR / 256)
ADC - OPTION register
Setting the ADPU bit = 1 turns on the on-chip charge pump.
The CSEL Control Bit selects which charge pump is activated:
0 - ADC (highest ADC accuracy)
1 - EEPROM (needed for EEPROM efficiency)
ADC - ADCTL register
The ATCTL Control Register Specifies Channel Assignments
The CCF flag is set to 1 upon completion of 4 conversions, so we can wait for conversion complete using the BRCLR instruction.
If the SCAN bit = 1, continuous conversions occur and the CCF bit is always 1.
CCF can only be read. Bits 0..5 are read/write.
ADC - SCAN bit
• SCAN - Continuous Scan Control
– If SCAN=0, four conversions are performed, filling the four result registers.
– If SCAN=1, then the A-D conversion continues in a round-robin fashion, and the result registers are updated (but the CCF bit remains set).
– CD = 0, CC=0 -> AN0..AN3 in ADR1..ADR4
– CD=0, CC = 1 -> AN4..AN7 in ARD1..ADR4
ADC - MULT bit
• MULT - Multiple Channel Control
– If the MULT bit=0, then a single channel is converted and the result stored.
– If MULT=1, then a conversion is performed on each channel in a group of 4 channels
ADC - Channel Assignments
ADRx - AD Result Registers
• The ADRx Results registers receive the converted level from the ADC.
– ADR1 - $1031
– ADR2 - $1032
– ADR3 - $1033
– ADR4 - $1034
ADC Code (1)
REGS EQU $1000 ; RegistersTOF EQU %10000000 ; Timer overflow flagN1 EQU 3030 ; times for one secTFLG2 EQU $25OPTION EQU $39ADCTL EQU $30ADR1 EQU $31ADSET EQU %00000100 ; A/D input on PE-4CCF EQU %10000000
; Conversion complete flagADPU EQU %10000000 ; A/D power up bit
ADC Code (2)
; Monitor EquatesOUTLHF EQU $FFB2 Print left halfOUTRHF EQU $FFB5 Print right halfCRLF EQU $FFC4 Print CRLF