Latch and Flip-flop

CHAPTER 3 Sequential Logic/ Circuits

Concept of Sequential LogicLatch and Flip-flops (FFs) Shift Registers and ApplicationCounters (Types, Application & Design)Sequential Circuits Design (State diagram, State Table, K-Map, Circuit)

Sequential vs Combinational Output of any combinational logic circuit depends directly on the input. Generally, in a sequential logic circuit, the output is dependent not only on the input but also on the stored state. Latch is used for the temporary storage of a data bit FF form the basis for most types of sequential logic, such as registers and counters. Also, two types of timing circuits; (1)one-shot and (2) 555 timer

Sequential vs Combinational Combinational circuits.Output determined solely by inputs.Can draw solely with left-to-right signal paths.

Sequential circuits.Output determined by inputs XXX previous outputs.Feedback loop.Comb. Cct.inputoutputSeq. Cct.inputoutput

Flip-flop & Register

Latches Edge-triggered flip-flops Master-slave flip-flops Flip-flop operating characteristics Flip-flop applications One-shots The 555 timer

IntroductionLatches and FFs are the basic single-bit memory elements used to build sequential circuit with one or two inputs/outputs, designed using individual logic gates and feedback loops.Latches:The output of a latch depends on its current inputs and on its previous output and its change of state can happen at any time when its inputs change. FFs:The output of a flip-flop also depends on current inputs and its previous output but the change of state occurs at specific times determined by a clock input.

Latches:D, S-R LatchGate S-R Latch Gate D-Latch

FFs:Edge-Triggered Flip-Flop (S-R, J-K, D)Asynchronous InputsMaster-Slave Flip-FlopFlip-Flop Operating CharacteristicsFlip-Flop Applications: One-shots & The 555 Timer

IntroductionA bistable logic circuit that can store a binary 1 or 0Similar to latch except that it can change state only on the occurrence of one edge of a clock pulse.

LatchesType of temporary storage device that has two stable (bi-stable) states Similar to flip-flop the outputs are connected back to opposite inputsMain difference from flip-flop is the method used for changing their stateIncludes: S-R latch, Gated/Enabled S-R latch and Gated D latch

S-R (SET-RESET) LatchActive-HIGH input S-R Latch Active-LOW input S-R Latch

Truth table for an active-LOW input S-R latch

Assume that Q is initially LOWWaveforms1345672

A gate input is added to the S-R latch to make the latch synchronous. In order for the set and reset inputs to change the latch, the gate input must be active (high/Enable). When the gate input is low, the latch remains in the hold condition. Gated S-R Latch

SRGQQ000QQHold100QQHold010QQHold110QQhold001QQhold10110set01101reset11100not allowed

The D (data) latch has a single input that is used to set and to reset the flip-flop. When the gate is high, the Q output will follow the D input. When the gate is low, the Q output will hold.

The output follows the input when the gate is high but is in a hold when the gate is low.

All the above flip-flops have the triggering input called clock (CLK/C)

Clock Signals & Synchronous Sequential CircuitsA clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals.

(d) S=1, R=1is invalid or not allowed

Example:

DCLK/CQQ_________________ 1 10SET (stores a 1)0 01 RESET (stores a 0)

Example:

JK CLKQQ00Q0Q0Hold0101Reset1010Set11Q0Q0Toggle (opposite state)

The edge-triggered J-K will only accept the J and inputs during the active edge of the clock. The small triangle on the clock input indicates that the device is edge-triggered. A bubble on the clock input indicates that the device responds to the negative edge. no bubble would indicate a positive edge-triggered device.

Edge-triggered J-K flip-flop

For D , J-K FFs, the inputs are called synchronous input because the state of this inputs control the output only on the triggering edge of clock pulse. (with synch. clock) Most IC FFs also have asynchronous inputs that change the output w/o a clock pulse. (work independently of clock) Two Asynch. Inputs: preset (PRE) and clear (CLR) Some cases called direct set (SD) and direct reset (RD) When PRE is active, FF is SET regardless of the When CLR is active, FF is RESET other inputs. Usually, asynch. inputs are active-LOW inputs, indicated with an overbar on the variable & a bubble on the FF symbol

Clock pulse 1,2,3 PRE is LOW, keeping FF SET regardless J-K inputs. Clock pulse 4,5,6,7 - toggle operation occurs bcos J-K are HIGH and both preset and clear are HIGH (inactive). Clock pulse 8,9 - clear is LOW, keeping FF RESET regardless of J-K inputs.

The J-K flip-flop has a toggle mode of operation when both J and K inputs are HIGH. Toggle means that the Q output will change states on each active clock edge. J, K and Cp are all synchronous inputs. The master-slave flip-flop is constructed with two latches. The master latch is loaded with the condition of the J-K inputs while the clock is high. When the clock goes low, the slave takes on the state of the master and the master is latched. The master-slave is a level-triggered device. The master-slave can interpret unwanted signals on the J-K inputs.Master-Slave J-K Flip-flop:Edge-triggered flip-flop logic symbols

JKCLKQQ00Q0Q0Hold0101Reset1010Set11Q0Q0Toggle (opposite state)

Flip-Flop Applications Parallel Data Storage Frequency Division Counting

Flip-Flop Operating CharacteristicsPropagation Delay TimesSet-up TimeHold TimeMaximum Clock FrequencyPulse WidthPower Dissipation

2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed

Propagation delay time is specified for the rising and falling outputs. It is measured between the 50% level of the clock to the 50% level of the output transition. Flip-flop Characteristics50% point on triggering edge50% point50% point on LOW-to-HIGH transition of QtPLHtPHLCLKCLKQQ50% point on HIGH-to- LOW transition of QThe typical propagation delay time for the 74AHC family (CMOS) is 4 ns. Even faster logic is available for specialized applications.


Another propagation delay time specification is the time required for an asynchronous input to cause a change in the output. Again it is measured from the 50% levels. The 74AHC family has specified delay times under 5 ns.Flip-flop Characteristics50% pointtPHLtPLHQ50% point50% point50% pointQPRECLR


Set-up time and hold time are times required before and after the clock transition that data must be present to be reliably clocked into the flip-flop.Flip-flop CharacteristicsSetup time is the minimum time for the data to be present before the clock for reliable data entry. Hold time is the minimum time for the data to remain after the clock for reliable data entry. CLKDCLKDSet-up time, tsHold time, tH

There are several other parameters that will also be listed in a manufacturers data sheet. Maximum frequency (Fmax) - The maximum frequency allowed at the clock input. Clock pulse width (LOW) [tW(L)] - The minimum width that is allowed at the clock input during the LOW level. Clock pulse width (HIGH) [tW(H)] - The minimum width that is allowed at the clock input during the high level. Set or Reset pulse width (LOW) [tw(L)] - The minimum width of the LOW pulse at the set or reset inputs.

Comparison of operating parameters for 4 IC families of flip-flop of the same type

Basic operation of a 555 TimerThresholdControl VoltageTriggerDischargeResetOutput

tw = 1.1R1C1 = 1.1(2000)(1F) = 2.2ms


One-ShotsThe one-shot or monostable multivibrator is a device with only one stable state. When triggered, it goes to its unstable state for a predetermined length of time, then returns to its stable state.For most one-shots, the length of time in the unstable state (tW) is determined by an external RC circuit.TriggerCEXTREXT+VCXRX/CXQtWTriggerQ


The 555 timerThe 555 can be configured as a basic astable multivibrator (pulse oscillator) with the circuit shown. In this circuit C1 charges through R1 and R2 and discharges through only R2. The output frequency is given by:The frequency and duty cycle are set by these components.RESETDISCHTHRESTRIGGNDCONTOUTVCCC1R1R2+VCC


The 555 timerGiven the components, you can read the frequency from the chart. Alternatively, you can use the chart to pick components for a desired frequency.RESETDISCHTHRESTRIGGNDCONTOUTVCCC1R1R2+VCCC1 (mF)f (Hz)

tH = .7 (R1+R2)C1 =2.1ms tL = .7R2C1 = 0.7mstH = time output hightL = time output low

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Latch and Flip-flop

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