1 1 CHAPTER 7 LATCH AND FLIP-FLOP 2 SEQUENTI AL CIRCUIT Called a circuit with memory. The output signals depend not onlyon the current inputs, but also the past sequence of input variables. Two types of sequential circuits: • Synchronous sequential circuits • Asynchro nous sequential circuit s
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• the output changes state only at a specified point on a triggeringinput called the clock (CLK), which is designated as a control input,C
• That is, the changes in the output occur in synchronization with theclock.
II) ASYNCHRONOUS SEQUENTIAL CIRCUIT
• depends on the inputs at only instance of time, whichthe input change.
• Refer to the events that do not have fixed timerelationship with each other, and generally do not occurat the same time
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TERMINOLOGY
Multivibrator A class of digital circuits in which the output is connectedback to the input to produce either two stable states, onestable states, or no stable states, depending on theconfiguration.
Bistable Having two stable states. Flip-flop and latches are bistablemultivibrators.
Latch An asynchronous bistable multivibrator, used forstoring 1 bit.
Flip-Flop A synchronous bistable multivibrator, used forstoring 1 bit.
Asynchronous There is not fixed timing relationship.
Synchronous There is a fixed timing relationship, usuallythrough the use of a clock pulse
If the and waveforms in figure (a) below are applied tothe inputs of the active-LOW input latch, determine thewaveform that will be observed on the Q output. Assume Q isinitially LOW.
S R
RS
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S-R Latch Application
If the switch bounce,means it is betweenposition 1 & 2,output will high. Aslong as switch DCfrom point 2, outputwill be high
If the switch bounce,means it is betweenposition 1 & 2,output will maintainbecause S-R willboth high, means NC
Given the waveforms in figure (a) below for the D input and theclock, determine the Q output waveform if the flip-flop starts outRESET.
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The Edge-Triggered J-K Flip-Flop
• The J-K flip-flop is versatile and is widely used type of flip-flop.
• The S-R edge-triggered flip-flop can be modified to become J-K edge-triggered flip-flop. The circuit is shown below.
• As can be seen the only changes in the JK flip-flop from the SR flip-flopare the additional feedback lines from the outputs to the oppositesteering gates.
• The difference between the SR flip-flop and JK flip-flop is:
JK flip-flop has no invalid state as does the SR flip flop.
Summarized Truth-table Logic Symbols
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Example
The waveforms in figure (a) below are applied to the J, K andclock inputs as indicated. Determine the Q output, assumingthat the flip-flop is initially RESET.
For a positive edge-triggered JK flip-flop with preset and clearinputs in figure below, determine the Q output for the inputsshown in the timing diagram in part (a) if Q is initially LOW.
Manufactures of IC fl ip-flop will specify several important timingparameters and characteristics that must be considered before a FFis used in any circuit application.
1. Set-up Time (ts)
- is the minimum interval required for the logic levels to bemaintained constantly on the inputs (J and K, S and R or D )prior to the triggering edge of the clock pulse.
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2. Hold Time (th)
- is the minimum interval required for the logic levels to remain onthe inputs after the triggering edge of the clock pulse.
- is the highest frequency that may be applied to the CLK input ofa FF.
- or is the highest rate at which FF can be reliably triggered.
- at clock frequencies above the maximum, the FF would beunable to respond quickly enough, and the operation would beimpaired.
- eg: For 7470 J-K flip-flop IC, its f MAX fall in the range 20 to 35MHz. So, he will specify the minimum f MAX as 20 MHz. Thismeans that; he cannot guarantee that the 7470 FF that you put inyour circuit will work above 20MHz. But, if you operate thembelow 20MHz, however; he guarantees that they will all work.
5. Pulse Widths (tw ) / Clock Pulse HIGH and LOW times
- the minimum time duration that the CLK signal must remain
LOW before it goes HIGH, sometimes called tw (L) , and theminimum time that CLK must kept HIGH before it returns LOW.Sometimes called tw (H).
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6. Power Dissipation
- is the total power consumption of the device.
- Example:
If the FF operates on a +5V dc source and draws 5mA of current,the power dissipation is:
- Power dissipation is very important in most applications, inwhich the capacity of dc supply is concern.
- Example:
- It also tells you the output capacity required of the dc supply.
- Example:
If the FF operates on +5V dc, then the amount of current that thesupply must provide is:
In digital systems, dataare normally stored ingroups of bits, thatrepresent numbers,codes or otherinformation.
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3. Frequency Division- Divide (reduce) the frequency of a periodic waveform.
- When a pulse of waveform is applied to the clock input of a J-Kflip-flop that is connected to toggle (J=K=1), the output is asquare wave with one-half the frequency of the clock input.
- Thus, a single flip-flop can be applied as a divide-by-2 device, asillustrated in figure below.
- This results in an output that changes at half the frequency of theclock waveform.