R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group RENESAS MCU REJ03B0293-0100 Rev.1.00 Page 1 of 72 Jun 25, 2010 1. Overview 1.1 Features The R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, and R8C/L3AC Group of single-chip MCUs incorporate the R8C CPU core, which implements a powerful instruction set for a high level of efficiency and supports a 1 Mbyte address space, allowing execution of instructions at high speed. In addition, the CPU core integrates a multiplier for high-speed operation processing. Power consumption is low, and the supported operating modes allow additional power control. These MCUs are designed to maximize EMI/EMS performance. Integration of many peripheral functions, including multifunction timer and serial interface, helps reduce the number of system components. These groups have data flash (1 KB × 4 blocks) with the background operation (BGO) function. 1.1.1 Applications Household appliances, office equipment, audio equipment, consumer products, etc. REJ03B0293-0100 Rev.1.00 Jun 25, 2010
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1.1 FeaturesThe R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, and R8C/L3AC Group of single-chip MCUsincorporate the R8C CPU core, which implements a powerful instruction set for a high level of efficiency andsupports a 1 Mbyte address space, allowing execution of instructions at high speed. In addition, the CPU coreintegrates a multiplier for high-speed operation processing.Power consumption is low, and the supported operating modes allow additional power control. These MCUs aredesigned to maximize EMI/EMS performance.Integration of many peripheral functions, including multifunction timer and serial interface, helps reduce thenumber of system components.These groups have data flash (1 KB × 4 blocks) with the background operation (BGO) function.
1.1.1 ApplicationsHousehold appliances, office equipment, audio equipment, consumer products, etc.
REJ03B0293-0100Rev.1.00
Jun 25, 2010
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 1. Overview
REJ03B0293-0100 Rev.1.00 Page 2 of 72Jun 25, 2010
1.1.2 Differences between GroupsTable 1.1 lists the Differences between Groups, Table 1.2 lists the Programmable I/O Ports Provided for EachGroup, and Table 1.3 lists the LCD Display Function Pins Provided for Each Group. Figures 1.9 to 1.13 showthe Pin Assignment for Each Group, and Tables 1.7 to 1.10 list Product Information. The explanations in the chapters which follow apply to the R8C/L3AC Group only. Note the differences shownbelow.
Note:1. I/O ports are shared with I/O functions, such as interrupts or timers.
Refer to Tables 1.11 to 1.13, Pin Name Information by Pin Number, for details.
Table 1.1 Differences between GroupsItem Function R8C/L35C Group R8C/L36C Group R8C/L38C Group R8C/L3AC Group
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 1. Overview
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Notes:1. The symbol “ ” indicates a programmable I/O port.2. The symbol “-” indicates the settings should be made as follows:
- Set 1 to the corresponding PDi (i = 0 to 7 and 10 to 13) register. When read, the content is 1. - Set 0 to the corresponding Pi (i = 0 to 7 and 10 to 13) register. When read, the content is 0. - Set 0 to the corresponding P10DRR or P11DRR register. When read, the content is 0.
Notes:1. The symbol “−”indicates there is no LCD display function. Select the I/O port function with registers LSE1 to LSE7 for these
pins.2. SEG52 to SEG55 can be used as COM7 to COM4.
The R8C/L35C Group does not have pins SEG52 to SEG55, so 1/8 duty cannot be selected.3. The R8C/L35C Group does not have the VL3 pin, so 1/4 bias cannot be selected. When the internal voltage multiplier is
used, 1/2 bias cannot also be selected.
Table 1.2 Programmable I/O Ports Provided for Each Group
Operating Ambient Temperature -20 to 85°C (N version)-40 to 85°C (D version) (1)
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 1. Overview
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1.2 Product ListsTables 1.7 to 1.10 list Product List for Each Group. Figures 1.1 to 1.4 show the Correspondence of Part No., withMemory Size and Package for Each Group.
Table 1.7 Product List for R8C/L35C Group Current of Jun 2010
Figure 1.1 Correspondence of Part No., with Memory Size and Package of R8C/L35C Group
Part No.Internal ROM Capacity Internal RAM
Capacity Package Type RemarksProgram ROM Data Flash
Part No. R 5 F 2L 3A C C N FPPackage type: FP: LQFP (0.50 mm pin pitch) FA: QFP (0.65 mm pin pitch)
ClassificationN: Operating ambient temperature -20°C to 85°CD: Operating ambient temperature -40°C to 85°C
ROM capacity7: 48 KB8: 64 KBA: 96 KBC: 128 KB
R8C/L3AC Group
R8C/Lx Series
Memory typeF: Flash memory
Renesas MCU
Renesas semiconductor
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 1. Overview
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1.3 Block DiagramsFigure 1.5 shows a Block Diagram of R8C/L35C Group. Figure 1.6 shows a Block Diagram of R8C/L36C Group.Figure 1.7 shows a Block Diagram of R8C/L38C Group. Figure 1.8 shows a Block Diagram of R8C/L3AC Group.
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 1. Overview
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Notes:1. The pin in parentheses can be assigned by a program.2. The number in brackets indicates the pin number for the 100P6F package. 3. Pins AN10 and AN11 are not available in the R8C/L35C, and R8C/L36C Groups.
Table 1.12 Pin Name Information by Pin Number (2)Pin Number
Control Pin Port
I/O Pin Functions for Peripheral Modules
L3AC (Note 2)
L38C L36C L35C Interrupt Timer Serial Interface SSU I2C bus
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 1. Overview
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1.5 Pin FunctionsTables 1.14 and 1.15 list Pin Functions.
I: Input O: Output I/O: Input and outputNote:
1. Contact the oscillator manufacturer for oscillation characteristics.
Table 1.14 Pin Functions (1)Item Pin Name I/O Type Description
Power supply input VCC, VSS − Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog power supply input
AVCC, AVSS − Power supply for the A/D converter.Connect a capacitor between AVCC and AVSS.
Reset input RESET I Driving this pin low resets the MCU.MODE MODE I Connect this pin to VCC via a resistor.Power-off mode exit input
WKUP0 I This pin is provided for input to exit the mode used in power-offmode. Connect to VSS when not using power-off mode.
XIN clock input XIN I These pins are provided for XIN clock generation circuit I/O.Connect a ceramic oscillator or a crystal oscillator between pinsXIN and XOUT. (1) To use an external clock, input it to the XINpin and leave the XOUT pin open.
XIN clock output XOUT O
XCIN clock input XCIN I These pins are provided for XCIN clock generation circuit I/O.Connect a crystal oscillator between pins XCIN and XCOUT. (1)
To use an external clock, input it to the XCIN pin and leave theXCOUT pin open.
XCIN clock output XCOUT O
INT interrupt input INT0 to INT7 I INT interrupt input pins.Key input interrupt KI0 to KI7 I Key input interrupt input pins
Timer RA TRAIO I/O Timer RA I/O pinTRAO O Timer RA output pin
Timer RB TRBO O Timer RB output pinTimer RC TRCCLK I External clock input pin
TRCTRG I External trigger input pinTRCIOA, TRCIOB,TRCIOC, TRCIOD
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 1. Overview
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I: Input O: Output I/O: Input and outputNote:
1. Contact the oscillator manufacturer for oscillation characteristics.
Table 1.15 Pin Functions (2)
Item Pin Name I/O Type Description
I2C bus SCL I/O Clock I/O pinSDA I/O Data I/O pin
SSU SSI I/O Data I/O pin
SCS I/O Chip-select signal I/O pin
SSCK I/O Clock I/O pinSSO I/O Data I/O pin
Reference voltage input
VREF I Reference voltage input pin for the A/D converter and the D/Aconverter
A/D converter AN0 to AN11 I A/D converter analog input pins
ADTRG I A/D external trigger input pin
D/A converter DA0, DA1 O D/A converter output pinsComparator B IVCMP1, IVCMP3 I Comparator B analog voltage input pins
IVREF1, IVREF3 I Comparator B reference voltage input pinsI/O ports P0_0 to P0_7,
P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0, P5_3, P6_0 to P6_7P7_0 to P7_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_3, P13_0 to P13_7
I/O CMOS I/O ports. Each port has an I/O select directionregister, allowing each pin in the port to be directed for inputor output individually.Any port set to input can be set to use a pull-up resistor or notby a program.Ports P10_0 to P10_7 and P11_0 to P11_7 can be used asLED drive ports.
Segment output SEG0 to SEG55 O LCD segment output pinsCommon output COM0 to COM7 O LCD common output pinsVoltage multiplier capacity connect pins
CL1, CL2 O Connect pins for the LCD control voltage multiplier
LCD power supply VL1 I/O Apply the voltage: 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VL4.VL1 can be used as the reference potential input or output pin when setting the voltage multiplier.
VL2 to VL4 I
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 2. Central Processing Unit (CPU)
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2. Central Processing Unit (CPU)Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure aregister bank. There are two sets of register banks.
Figure 2.1 CPU Registers
R2b31 b15 b8b7 b0
Data registers (1)
Address registers (1)
R3R0H (high-order of R0)
R2R3A0A1
INTBHb15b19 b0
INTBL
FB Frame base register (1)
The 4 high-order bits of INTB are INTBH andthe 16 low-order bits of INTB are INTBL.
Interrupt table register
b19 b0
USP
Program counter
ISPSB
User stack pointer
Interrupt stack pointer
Static base register
PC
FLG Flag register
Carry flagDebug flagZero flagSign flagRegister bank select flagOverflow flagInterrupt enable flagStack pointer select flagReserved bitProcessor interrupt priority levelReserved bit
CIPL DZSBOIU
b15 b0
b15 b0
b15 b0b8 b7
Note:1. These registers configure a register bank. There are two sets of register banks.
R1H (high-order of R1)
R0L (low-order of R0)
R1L (low-order of R1)
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 2. Central Processing Unit (CPU)
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2.1 Data Registers (R0, R1, R2, and R3)R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be splitinto high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L areanalogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 isanalogous to R2R0.
2.2 Address Registers (A0 and A1)A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is alsoused for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5 Program Counter (PC)PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch betweenUSP and ISP.
2.7 Static Base Register (SB)SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2 Debug Flag (D)The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5 Register Bank Select Flag (B)Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 2. Central Processing Unit (CPU)
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2.8.7 Interrupt Enable Flag (I)The I flag enables maskable interrupts.Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of softwareinterrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved BitIf necessary, set to 0. When read, the content is undefined.
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 3. Memory
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3. MemoryFigure 3.1 is a Memory Map of each group. Each group has a 1-Mbyte address space from addresses 00000h toFFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. Forexample, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interruptroutine is stored here. The internal ROM (data flash) is allocated addresses 03000h to 03FFFh. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 6-Kbyte internalRAM area is allocated addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but also as astack area when a subroutine is called or when an interrupt request is acknowledged.Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheralfunction control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot beaccessed by users.
Figure 3.1 Memory Map
0FFFFh
0FFDCh
Notes: 1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte). 2. Blank spaces are reserved. No access is allowed.FFFFFh
0FFFFh
0YYYYh
0XXXXh
00400h
002FFh
00000h
Internal ROM(program ROM)
Internal RAM
SFR(Refer to 4. SpecialFunction Registers
(SFRs))
02FFFh
02C00h SFR(Refer to 4. Special Function
Registers (SFRs))
ZZZZZh
Internal ROM(program ROM)
03FFFh
03000hInternal ROM(data flash) (1)
0FFD8h
Reserved area
Undefined instructionOverflow
BRK instructionAddress match
Single stepWatchdog timer, oscillation stop detection, voltage monitor
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 4. Special Function Registers (SFRs)
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4. Special Function Registers (SFRs)An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.16 list SFRInformations and Table 4.17 lists the ID Code Areas and Option Function Select Area. The description offered in thischapter is based on the R8C/L3AC Group.
Table 4.1 SFR Information (1) (1)
X: UndefinedNotes:
1. Blank spaces are reserved. No access is allowed.2. The CWR bit in the RSTFR register is set to 0 after power-on, voltage monitor 0 reset, or exit from power-off mode. Hardware reset, software
reset, or watchdog timer reset does not affect this bit. 3. The CSPROINI bit in the OFS register is set to 0.4. The LVDAS bit in the OFS register is set to 1.5. The LVDAS bit in the OFS register is set to 0.
Address Register Symbol After Reset0000h0001h0002h0003h0004h Processor Mode Register 0 PM0 00h0005h Processor Mode Register 1 PM1 00h0006h System Clock Control Register 0 CM0 00100000b0007h System Clock Control Register 1 CM1 00100000b0008h Module Standby Control Register MSTCR 00h0009h System Clock Control Register 3 CM3 00h000Ah Protect Register PRCR 00h000Bh Reset Source Determination Register RSTFR XXh (2)
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 4. Special Function Registers (SFRs)
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Table 4.13 SFR Information (13) (1)
X: UndefinedNote:
1. Blank spaces are reserved. No access is allowed.
Address Register Symbol After Reset2C00h DTC Transfer Vector Area XXh2C01h DTC Transfer Vector Area XXh2C02h DTC Transfer Vector Area XXh2C03h DTC Transfer Vector Area XXh2C04h DTC Transfer Vector Area XXh2C05h DTC Transfer Vector Area XXh2C06h DTC Transfer Vector Area XXh2C07h DTC Transfer Vector Area XXh2C08h DTC Transfer Vector Area XXh2C09h DTC Transfer Vector Area XXh2C0Ah DTC Transfer Vector Area XXh
: DTC Transfer Vector Area XXh: DTC Transfer Vector Area XXh
2C3Ah DTC Transfer Vector Area XXh2C3Bh DTC Transfer Vector Area XXh2C3Ch DTC Transfer Vector Area XXh2C3Dh DTC Transfer Vector Area XXh2C3Eh DTC Transfer Vector Area XXh2C3Fh DTC Transfer Vector Area XXh2C40h DTC Control Data 0 DTCD0 XXh2C41h XXh2C42h XXh2C43h XXh2C44h XXh2C45h XXh2C46h XXh2C47h XXh2C48h DTC Control Data 1 DTCD1 XXh2C49h XXh2C4Ah XXh2C4Bh XXh2C4Ch XXh2C4Dh XXh2C4Eh XXh2C4Fh XXh2C50h DTC Control Data 2 DTCD2 XXh2C51h XXh2C52h XXh2C53h XXh2C54h XXh2C55h XXh2C56h XXh2C57h XXh2C58h DTC Control Data 3 DTCD3 XXh2C59h XXh2C5Ah XXh2C5Bh XXh2C5Ch XXh2C5Dh XXh2C5Eh XXh2C5Fh XXh2C60h DTC Control Data 4 DTCD4 XXh2C61h XXh2C62h XXh2C63h XXh2C64h XXh2C65h XXh2C66h XXh2C67h XXh2C68h DTC Control Data 5 DTCD5 XXh2C69h XXh2C6Ah XXh2C6Bh XXh2C6Ch XXh2C6Dh XXh2C6Eh XXh2C6Fh XXh
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 4. Special Function Registers (SFRs)
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Table 4.14 SFR Information (14) (1)
X: UndefinedNote:
1. Blank spaces are reserved. No access is allowed.
Address Register Symbol After Reset2C70h DTC Control Data 6 DTCD6 XXh2C71h XXh2C72h XXh2C73h XXh2C74h XXh2C75h XXh2C76h XXh2C77h XXh2C78h DTC Control Data 7 DTCD7 XXh2C79h XXh2C7Ah XXh2C7Bh XXh2C7Ch XXh2C7Dh XXh2C7Eh XXh2C7Fh XXh2C80h DTC Control Data 8 DTCD8 XXh2C81h XXh2C82h XXh2C83h XXh2C84h XXh2C85h XXh2C86h XXh2C87h XXh2C88h DTC Control Data 9 DTCD9 XXh2C89h XXh2C8Ah XXh2C8Bh XXh2C8Ch XXh2C8Dh XXh2C8Eh XXh2C8Fh XXh2C90h DTC Control Data 10 DTCD10 XXh2C91h XXh2C92h XXh2C93h XXh2C94h XXh2C95h XXh2C96h XXh2C97h XXh2C98h DTC Control Data 11 DTCD11 XXh2C99h XXh2C9Ah XXh2C9Bh XXh2C9Ch XXh2C9Dh XXh2C9Eh XXh2C9Fh XXh2CA0h DTC Control Data 12 DTCD12 XXh2CA1h XXh2CA2h XXh2CA3h XXh2CA4h XXh2CA5h XXh2CA6h XXh2CA7h XXh2CA8h DTC Control Data 13 DTCD13 XXh2CA9h XXh2CAAh XXh2CABh XXh2CACh XXh2CADh XXh2CAEh XXh2CAFh XXh
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 4. Special Function Registers (SFRs)
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Table 4.15 SFR Information (15) (1)
X: UndefinedNote:
1. Blank spaces are reserved. No access is allowed.
Address Register Symbol After Reset2CB0h DTC Control Data 14 DTCD14 XXh2CB1h XXh2CB2h XXh2CB3h XXh2CB4h XXh2CB5h XXh2CB6h XXh2CB7h XXh2CB8h DTC Control Data 15 DTCD15 XXh2CB9h XXh2CBAh XXh2CBBh XXh2CBCh XXh2CBDh XXh2CBEh XXh2CBFh XXh2CC0h DTC Control Data 16 DTCD16 XXh2CC1h XXh2CC2h XXh2CC3h XXh2CC4h XXh2CC5h XXh2CC6h XXh2CC7h XXh2CC8h DTC Control Data 17 DTCD17 XXh2CC9h XXh2CCAh XXh2CCBh XXh2CCCh XXh2CCDh XXh2CCEh XXh2CCFh XXh2CD0h DTC Control Data 18 DTCD18 XXh2CD1h XXh2CD2h XXh2CD3h XXh2CD4h XXh2CD5h XXh2CD6h XXh2CD7h XXh2CD8h DTC Control Data 19 DTCD19 XXh2CD9h XXh2CDAh XXh2CDBh XXh2CDCh XXh2CDDh XXh2CDEh XXh2CDFh XXh2CE0h DTC Control Data 20 DTCD20 XXh2CE1h XXh2CE2h XXh2CE3h XXh2CE4h XXh2CE5h XXh2CE6h XXh2CE7h XXh2CE8h DTC Control Data 21 DTCD21 XXh2CE9h XXh2CEAh XXh2CEBh XXh2CECh XXh2CEDh XXh2CEEh XXh2CEFh XXh
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group 4. Special Function Registers (SFRs)
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Table 4.16 SFR Information (16) (1)
X: UndefinedNote:
1. Blank spaces are reserved. No access is allowed.
Table 4.17 ID Code Areas and Option Function Select Area
Notes:1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the option function select area. If the block including the option function select area is erased, the option function selectarea is set to FFh.When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user.When factory-programming products are shipped, the value of the option function select area is the value programmed by the user.
2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh.When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user.When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.
Address Register Symbol After Reset2CF0h DTC Control Data 22 DTCD22 XXh2CF1h XXh2CF2h XXh2CF3h XXh2CF4h XXh2CF5h XXh2CF6h XXh2CF7h XXh2CF8h DTC Control Data 23 DTCD23 XXh2CF9h XXh2CFAh XXh2CFBh XXh2CFCh XXh2CFDh XXh2CFEh XXh2CFFh XXh2D00h
:2FFFh
Address Area Name Symbol After Reset:
FFDBh Option Function Select Register 2 OFS2 (Note 1):
FFDFh ID1 (Note 2):
FFE3h ID2 (Note 2):
FFEBh ID3 (Note 2):
FFEFh ID4 (Note 2):
FFF3h ID5 (Note 2):
FFF7h ID6 (Note 2):
FFFBh ID7 (Note 2):
FFFFh Option Function Select Register OFS (Note 1)
R8C/L36C, R8C/L38C, R8C/L3AC VL1 to VL3 VVL3 VL2 to VL4 VVL4 −0.3 to 6.5 VCL1, CL2 −0.3 to 6.5 VCOM0 to COM7 −0.3 to VL4 VSEG0 to SEG55 −0.3 to VL4 VOther pins −0.3 to VCC + 0.3 V
Pd Power dissipation −40°C ≤ Topr ≤ 85°C 500 mWTopr Operating ambient temperature −20 to 85 (N version) /
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5.2 Recommended Operating Conditions
Notes:1. The average output current indicates the average value of current measured during 100 ms.2. This applies when the drive capacity of the output transistor is set to High by registers P10DRR and P11DRR. When the drive
capacity is set to Low, the value of any other pin applies.3. fOCO40M can be used as the count source for timer RC, timer RD, or timer RG in the range of VCC = 2.7 V to 5.5V.
Table 5.2 Recommended Operating Conditions(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter ConditionsStandard
UnitMin. Typ. Max.
VCC/AVCC Supply voltage 1.8 — 5.5 VVSS/AVSS Supply voltage — 0 — VVIH Input “H” voltage Other than CMOS input 4.0 V ≤ VCC ≤ 5.5 V 0.8 VCC — VCC V
2.7 V ≤ VCC < 4.0 V 0.8 VCC — VCC V1.8 V ≤ VCC < 2.7 V 0.9 VCC — VCC V
CMOS input
Input level switching function (I/O port)
Input level selection: 0.35 VCC
4.0 V ≤ VCC ≤ 5.5 V 0.5 VCC — VCC V2.7 V ≤ VCC < 4.0 V 0.55 VCC — VCC V1.8 V ≤ VCC < 2.7 V 0.65 VCC — VCC V
Input level selection: 0.5 VCC
4.0 V ≤ VCC ≤ 5.5 V 0.65 VCC — VCC V2.7 V ≤ VCC < 4.0 V 0.7 VCC — VCC V1.8 V ≤ VCC < 2.7 V 0.8 VCC — VCC V
Input level selection: 0.7 VCC
4.0 V ≤ VCC ≤ 5.5 V 0.85 VCC — VCC V2.7 V ≤ VCC < 4.0 V 0.85 VCC — VCC V1.8 V ≤ VCC < 2.7 V 0.85 VCC — VCC V
VIL Input “L” voltage Other than CMOS input 4.0 V ≤ VCC ≤ 5.5 V 0 — 0.2 VCC V2.7 V ≤ VCC < 4.0 V 0 — 0.2 VCC V1.8 V ≤ VCC < 2.7 V 0 — 0.05 VCC V
CMOS input
Input level switching function (I/O port)
Input level selection: 0.35 VCC
4.0 V ≤ VCC ≤ 5.5 V 0 — 0.2 VCC V2.7 V ≤ VCC < 4.0 V 0 — 0.2 VCC V1.8 V ≤ VCC < 2.7 V 0 — 0.2 VCC V
Input level selection: 0.5 VCC
4.0 V ≤ VCC ≤ 5.5 V 0 — 0.4 VCC V2.7 V ≤ VCC < 4.0 V 0 — 0.3 VCC V1.8 V ≤ VCC < 2.7 V 0 — 0.2 VCC V
Input level selection: 0.7 VCC
4.0 V ≤ VCC ≤ 5.5 V 0 — 0.55 VCC V2.7 V ≤ VCC < 4.0 V 0 — 0.45 VCC V1.8 V ≤ VCC < 2.7 V 0 — 0.35 VCC V
IOH(sum) Peak sum output “H” current
Sum of all pins IOH(peak) — — −160 mA
IOH(sum) Average sum output “H” current
Sum of all pins IOH(avg) — — −80 mA
IOH(peak) Peak output “H” current
Port P10, P11 (2) — — −40 mAOther pins — — −10 mA
IOH(avg) Average output “H” current (1)
Port P10, P11 (2) — — −20 mAOther pins — — −5 mA
IOL(sum) Peak sum output “L” current
Sum of all pins IOL(peak) — — 160 mA
IOL(sum) Average sum output “L” current
Sum of all pins IOL(avg) — — 80 mA
IOL(peak) Peak output “L” current
Port P10, P11 (2) — — 40 mAOther pins — — 10 mA
IOL(avg) Average output “L” current (1)
Port P10, P11 (2) — — 20 mAOther pins — — 5 mA
f(XIN) XIN clock input oscillation frequency 2.7 V ≤ VCC ≤ 5.5 V — — 20 MHz1.8 V ≤ VCC < 2.7 V — — 5 MHz
f(XCIN) XCIN clock input oscillation frequency 1.8 V ≤ VCC ≤ 5.5 V — 32.768 50 kHzfOCO40M When used as the count source for timer RC, timer RD, or
timer RG (3)2.7 V ≤ VCC ≤ 5.5 V 32 — 40 MHz
fOCO-F fOCO-F frequency 2.7 V ≤ VCC ≤ 5.5 V — — 20 MHz1.8 V ≤ VCC < 2.7 V — — 5 MHz
— System clock frequency 2.7 V ≤ VCC ≤ 5.5 V — — 20 MHz1.8 V ≤ VCC < 2.7 V — — 5 MHz
f(BCLK) CPU clock frequency 2.7 V ≤ VCC ≤ 5.5 V — — 20 MHz1.8 V ≤ VCC < 2.7 V — — 5 MHz
REJ03B0293-0100 Rev.1.00 Page 48 of 72Jun 25, 2010
5.3 Peripheral Function Characteristics
Notes:1. The A/D conversion result will be undefined in wait mode, stop mode, power-off mode, when the flash memory stops, and in
low-current-consumption mode. Do not perform A/D conversion in these states or transition to these states during A/D conversion.
2. This applies when the peripheral functions are stopped.3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
Table 5.3 A/D Converter Characteristics(VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
REJ03B0293-0100 Rev.1.00 Page 50 of 72Jun 25, 2010
Notes:1. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one.However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.6. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 5.6 Flash Memory (Program ROM) Characteristics(VCC = 2.7 to 5.5 V and Topr = 0 to 60°C, unless otherwise specified.)
Symbol Parameter ConditionsStandard
UnitMin. Typ. Max.
— Program/erase endurance (1) 1,000 (2) — — times— Byte program time — 80 500 µs— Block erase time — 0.3 — std(SR-SUS) Time delay from suspend request until
suspend— — 5 + CPU clock
× 3 cyclesms
— Interval from erase start/restart until following suspend request
0 — — ms
— Time from suspend until erase restart — — 30+CPU clock × 1 cycle
µs
td(CMDRST-READY)
Time from when command is forcibly terminated until reading is enabled
— — 30+CPU clock × 1 cycle
µs
— Program, erase voltage 2.7 — 5.5 V— Read voltage 1.8 — 5.5 V— Program, erase temperature 0 — 60 °C— Data hold time (6) Ambient temperature = 55°C 20 — — year
REJ03B0293-0100 Rev.1.00 Page 51 of 72Jun 25, 2010
Notes:1. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.6. −40°C for D version.7. The data hold time includes time that the power supply is off or the clock is not supplied.
Figure 5.2 Time delay until Suspend
Table 5.7 Flash Memory (Data flash Block A to Block D) Characteristics(VCC = 2.7 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter ConditionsStandard
UnitMin. Typ. Max.
— Program/erase endurance (1) 10,000 (2) — — times— Byte program time
td(SR-SUS) Time delay from suspend request until suspend
— — 5 + CPU clock × 3 cycles
ms
— Interval from erase start/restart until following suspend request
0 — — ms
— Time from suspend until erase restart — — 30+CPU clock × 1 cycle
µs
td(CMDRST-READY)
Time from when command is forcibly terminated until reading is enabled
— — 30+CPU clock × 1 cycle
µs
— Program, erase voltage 2.7 — 5.5 V— Read voltage 1.8 — 5.5 V— Program, erase temperature −20 (6) — 85 °C— Data hold time (7) Ambient temperature = 55 °C 20 — — year
FST6 bit
Suspend request(FMR21 bit)
Fixed timeClock-dependent
timeAccess restart
FST6, FST7: Bit in FST registerFMR21: Bit in FMR2 register
REJ03B0293-0100 Rev.1.00 Page 52 of 72Jun 25, 2010
Notes:1. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register. 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.3. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.
Notes:1. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register. 2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
Table 5.8 Voltage Detection 0 Circuit Characteristics(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter ConditionStandard
UnitMin. Typ. Max.
Vdet0 Voltage detection level Vdet0_0 (1) 1.80 1.90 2.05 V
Voltage detection level Vdet0_1 (1) 2.15 2.35 2.50 V
Voltage detection level Vdet0_2 (1) 2.70 2.85 3.05 V
Voltage detection level Vdet0_3 (1) 3.55 3.80 4.05 V— Voltage detection 0 circuit response time (3) At the falling of Vcc from 5 V
to (Vdet0_0 − 0.1) V— 6 150 µs
— Voltage detection circuit self power consumption VCA25 = 1, VCC = 5.0 V — 1.5 — µAtd(E-A) Waiting time until voltage detection circuit
operation starts (2)— — 100 µs
Table 5.9 Voltage Detection 1 Circuit Characteristics(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter ConditionStandard
UnitMin. Typ. Max.
Vdet1 Voltage detection level Vdet1_0 (1) At the falling of VCC 2.00 2.20 2.40 V
Voltage detection level Vdet1_1 (1) At the falling of VCC 2.15 2.35 2.55 V
Voltage detection level Vdet1_2 (1) At the falling of VCC 2.30 2.50 2.70 V
Voltage detection level Vdet1_3 (1) At the falling of VCC 2.45 2.65 2.85 V
Voltage detection level Vdet1_4 (1) At the falling of VCC 2.60 2.80 3.00 V
Voltage detection level Vdet1_5 (1) At the falling of VCC 2.75 2.95 3.15 V
Voltage detection level Vdet1_6 (1) At the falling of VCC 2.85 3.10 3.40 V
Voltage detection level Vdet1_7 (1) At the falling of VCC 3.00 3.25 3.55 V
Voltage detection level Vdet1_8 (1) At the falling of VCC 3.15 3.40 3.70 V
Voltage detection level Vdet1_9 (1) At the falling of VCC 3.30 3.55 3.85 V
Voltage detection level Vdet1_A (1) At the falling of VCC 3.45 3.70 4.00 V
Voltage detection level Vdet1_B (1) At the falling of VCC 3.60 3.85 4.15 V
Voltage detection level Vdet1_C (1) At the falling of VCC 3.75 4.00 4.30 V
Voltage detection level Vdet1_D (1) At the falling of VCC 3.90 4.15 4.45 V
Voltage detection level Vdet1_E (1) At the falling of VCC 4.05 4.30 4.60 V
Voltage detection level Vdet1_F (1) At the falling of VCC 4.20 4.45 4.75 V— Hysteresis width at the rising of Vcc in voltage
detection 1 circuitVdet1_0 to Vdet1_5 selected
— 0.07 — V
Vdet1_6 to Vdet1_F selected
— 0.10 — V
— Voltage detection 1 circuit response time (2) At the falling of Vcc from 5 V to (Vdet1_0 − 0.1) V
— 60 150 µs
— Voltage detection circuit self power consumption VCA26 = 1, VCC = 5.0 V — 1.7 — µAtd(E-A) Waiting time until voltage detection circuit operation
REJ03B0293-0100 Rev.1.00 Page 53 of 72Jun 25, 2010
Notes:1. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.2. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Note:1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
Figure 5.3 Power-on Reset Circuit Characteristics
Table 5.10 Voltage Detection 2 Circuit Characteristics(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter ConditionStandard
UnitMin. Typ. Max.
Vdet2 Voltage detection level Vdet2_0 At the falling of VCC 3.70 4.00 4.30 V— Hysteresis width at the rising of Vcc in voltage detection
2 circuit— 0.10 — V
— Voltage detection 2 circuit response time (1) At the falling of Vcc from 5 V to (Vdet2_0 − 0.1) V
— 20 150 µs
— Voltage detection circuit self power consumption VCA27 = 1, VCC = 5.0 V — 1.7 — µAtd(E-A) Waiting time until voltage detection circuit operation
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter ConditionStandard
UnitMin. Typ. Max.
trth External power VCC rise gradient 0 — 50000 mV/msec
Notes:1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit in the User’s Manual: Hardware for details.2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintaintw(por) for 1 ms or more.
Vdet0 (1)
0.5 V
Internalreset signal
tw(por) (2) Voltage detection 0circuit response time
REJ03B0293-0100 Rev.1.00 Page 54 of 72Jun 25, 2010
Note:1. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
Note:1. Waiting time until the internal power supply generation circuit stabilizes during power-on.
Table 5.12 High-speed On-Chip Oscillator Circuit Characteristics(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter ConditionStandard Unit
Min. Typ. Max.— High-speed on-chip oscillator frequency after
reset VCC = 1.8 V to 5.5 V−20°C ≤ Topr ≤ 85°C
38.4 40 41.6 MHz
VCC = 1.8 V to 5.5 V−40°C ≤ Topr ≤ 85°C
38.0 40 42.0 MHz
High-speed on-chip oscillator frequency when the FRA4 register correction value is written into the FRA1 register and the FRA5 register correction value into the FRA3 register (1)
VCC = 1.8 V to 5.5 V−20°C ≤ Topr ≤ 85°C
35.389 36.864 38.338 MHz
VCC = 1.8 V to 5.5 V−40°C ≤ Topr ≤ 85°C
35.020 36.864 38.707 MHz
High-speed on-chip oscillator frequency when the FRA6 register correction value is written into the FRA1 register and the FRA7 register correction value into the FRA3 register
REJ03B0293-0100 Rev.1.00 Page 55 of 72Jun 25, 2010
Notes:1. The voltage is selected with bits LVLS0 to LVLS3 in the LCR1 register. 2. Refer to Table 5.18 DC Characteristics (2), Table 5.20 DC Characteristics (4), and Table 5.22 DC Characteristics (6).3. The VL1 voltage should be VCC or below.
Table 5.15 LCD Drive Control Circuit Characteristics(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter ConditionStandard
UnitMin. Typ. Max.
VLCD LCD power supply voltage VLCD = VL4 2.2 — 5.5 VVL3 VL3 voltage VL2 — VL4 VVL2 VL2 voltage R8C/L35C VL1 — VL4 V
R8C/L36C, R8C/L38C, R8C/L3AC VL1 — VL3 VVL1 VL1 voltage 1 — VL2 (3) V— VL1 internally-generated voltage accuracy
(1)Setting voltage
−0.2
Setting voltage
Setting voltage
+0.2
V
f(FR) Frame frequency 50 — 180 HzILCD LCD drive control circuit current — (Note 2) — µA
Table 5.16 Power-Off Mode Characteristics(VCC = 2.2 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter ConditionStandard
UnitMin. Typ. Max.
— Power-off mode operating supply voltage 2.2 — 5.5 V
REJ03B0293-0100 Rev.1.00 Page 57 of 72Jun 25, 2010
Notes:1. Vcc = 4.0 V to 5.5 V, single chip mode, output pins are open, and other pins are Vss.2. XIN is set to square wave input.3. Vcc = 5.0 V4. VLCD = Vcc, external division resistors are used for VL4 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55 are selected, and segment
and common output pins are open. The standard value does not include the current that flows through external division resistors. 5. The internal voltage multiplier is used, bits LVLS3 to LVLS0 in the LCR1 register = 1011b, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55
are selected, and segment and common output pins are open.
Table 5.18 DC Characteristics (2) [4.0 V ≤ Vcc ≤ 5.5 V](Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter
Condition Standard
UnitOscillation
CircuitOn-Chip Oscillator CPU
Clock
Low-Power-Consumption
SettingOther Min. Typ.
(3)Max
.XIN (2)
XCIN High-Speed
Low-Speed
ICC Power supply current (1)
High-speed clock mode
20 MHz
Off Off 125 kHz
No division
— — 7.0 15 mA
16 MHz
Off Off 125 kHz
No division
— — 5.6 12.5 mA
10 MHz
Off Off 125 kHz
No division
— — 3.6 — mA
20 MHz
Off Off 125 kHz
Divide-by-8
— — 3.0 — mA
16 MHz
Off Off 125 kHz
Divide-by-8
— — 2.2 — mA
10 MHz
Off Off 125 kHz
Divide-by-8
— — 1.5 — mA
High-speed on-chip oscillator mode
Off Off 20 MHz 125 kHz
No division
— — 7.0 15 mA
Off Off 20 MHz 125 kHz
Divide-by-8
— — 3.0 — mA
Off Off 4 MHz 125 kHz
Divide-by-16
MSTIIC = 1MSTTRD = 1MSTTRC = 1MSTTRG = 1
— 1 — mA
Low-speed on-chip oscillator mode
Off Off Off 125 kHz
Divide-by-8
FMR27 = 1VCA20 = 0
— 90 400 µA
Low-speed clock mode
Off 32 kHz
Off Off No division
FMR27 = 1VCA20 = 0
— 100 400 µA
Off 32 kHz
Off Off No division
FMSTP = 1VCA20 = 0
Flash memory offProgram operation on RAM
— 55 — µA
Wait mode
Off Off Off 125 kHz
— VCA27 = 0VCA26 = 0VCA25 = 0VCA20 = 1
While a WAIT instruction is executedPeripheral clock operation
REJ03B0293-0100 Rev.1.00 Page 59 of 72Jun 25, 2010
Notes:1. Vcc = 2.7 V to 4.0 V, single chip mode, output pins are open, and other pins are Vss.2. XIN is set to square wave input.3. Vcc = 3.0 V4. VLCD = Vcc, external division resistors are used for VL4 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55 are selected, and segment
and common output pins are open. The standard value does not include the current that flows through external division resistors. 5. The internal voltage multiplier is used, bits LVLS3 to LVLS0 in the LCR1 register = 1011b, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55
are selected, and segment and common output pins are open.
Table 5.20 DC Characteristics (4) [2.7 V ≤ Vcc < 4.0 V](Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter
Condition Standard
UnitOscillation
CircuitOn-Chip Oscillator CPU
Clock
Low-Power-Consumption
SettingOther Min. Typ.
(3)Max
.XIN (2)
XCIN High-Speed
Low-Speed
ICC Power supply current (1)
High-speed clock mode
20 MHz
Off Off 125 kHz
No division
— — 7.0 14.5 mA
10 MHz
Off Off 125 kHz
No division
— — 3.6 10 mA
20 MHz
Off Off 125 kHz
Divide-by-8
— — 3.0 — mA
10 MHz
Off Off 125 kHz
Divide-by-8
— — 1.5 — mA
High-speed on-chip oscillator mode
Off Off 20 MHz 125 kHz
No division
— — 7.0 14.5 mA
Off Off 20 MHz 125 kHz
Divide-by-8
— — 3.0 — mA
Off Off 10 MHz 125 kHz
No division
— — 4.0 — mA
Off Off 10 MHz 125 kHz
Divide-by-8
— — 1.7 — mA
Off Off 4 MHz 125 kHz
Divide-by-16
MSTIIC = 1MSTTRD = 1MSTTRC = 1MSTTRG = 1
— 1 — mA
Low-speed on-chip oscillator mode
Off Off Off 125 kHz
Divide-by-8
FMR27 = 1VCA20 = 0
— 85 390 µA
Low-speed clock mode
Off 32 kHz
Off Off No division
FMR27 = 1VCA20 = 0
— 90 400 µA
Off 32 kHz
Off Off No division
FMSTP = 1VCA20 = 0
Flash memory offProgram operation on RAM
— 50 — µA
Wait mode
Off Off Off 125 kHz
— VCA27 = 0VCA26 = 0VCA25 = 0VCA20 = 1
While a WAIT instruction is executedPeripheral clock operation
REJ03B0293-0100 Rev.1.00 Page 61 of 72Jun 25, 2010
Notes:1. Vcc = 1.8 V to 2.7 V, single chip mode, output pins are open, and other pins are Vss.2. XIN is set to square wave input.3. Vcc = 2.2 V4. VLCD = Vcc, external division resistors are used for VL4 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55 are selected, and segment
and common output pins are open.The standard value does not include the current that flows through external division resistors. 5. The internal voltage multiplier is used, bits LVLS3 to LVLS0 in the LCR1 register = 1011b, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG55
are selected, and segment and common output pins are open.
Table 5.22 DC Characteristics (6) [1.8 V ≤ Vcc < 2.7 V](Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter
Condition Standard
UnitOscillation
CircuitOn-Chip Oscillator CPU
Clock
Low-Power-Consumption
SettingOther Min. Typ.
(3)Max
.XIN (2)
XCIN High-Speed
Low-Speed
ICC Power supply current (1)
High-speed clock mode
5 MHz
Off Off 125 kHz
No division
— — 2.2 — mA
5 MHz
Off Off 125 kHz
Divide-by-8
— — 0.8 — mA
High-speed on-chip oscillator mode
Off Off 5 MHz 125 kHz
No division
— — 2.5 10 mA
Off Off 5 MHz 125 kHz
Divide-by-8
— — 1.7 — mA
Off Off 4 MHz 125 kHz
Divide-by-16
MSTIIC = 1MSTTRD = 1MSTTRC = 1MSTTRG = 1
— 1 — mA
Low-speed on-chip oscillator mode
Off Off Off 125 kHz
Divide-by-8
FMR27 = 1VCA20 = 0
— 90 300 µA
Low-speed clock mode
Off 32 kHz
Off Off No division
FMR27 = 1VCA20 = 0
— 90 400 µA
Off 32 kHz
Off Off No division
FMSTP = 1VCA20 = 0
Flash memory offProgram operation on RAM
— 45 — µA
Wait mode
Off Off Off 125 kHz
— VCA27 = 0VCA26 = 0VCA25 = 0VCA20 = 1
While a WAIT instruction is executedPeripheral clock operation
REJ03B0293-0100 Rev.1.00 Page 62 of 72Jun 25, 2010
5.5 AC Characteristics
Note:1. 1tCYC = 1/f1(s)
Table 5.23 Timing Requirements of Synchronous Serial Communication Unit (SSU)(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter ConditionsStandard
UnitMin. Typ. Max.
tSUCYC SSCK clock cycle time 4 — — tCYC (1)
tHI SSCK clock “H” width 0.4 — 0.6 tSUCYC
tLO SSCK clock “L” width 0.4 — 0.6 tSUCYC
tRISE SSCK clock rising time
Master — — 1 tCYC (1)
Slave — — 1 µstFALL SSCK clock falling
time Master — — 1 tCYC (1)
Slave — — 1 µstSU SSO, SSI data input setup time 100 — — nstH SSO, SSI data input hold time 1 — — tCYC (1)
tLEAD SCS setup time Slave 1tCYC + 50 — — nstLAG SCS hold time Slave 1tCYC + 50 — — nstOD SSO, SSI data output delay time — — 1 tCYC (1)
tSA SSI slave access time 2.7 V ≤ VCC ≤ 5.5 V — — 1.5tCYC + 100 ns1.8 V ≤ VCC < 2.7 V — — 1.5tCYC + 200 ns
tOR SSI slave out open time 2.7 V ≤ VCC ≤ 5.5 V — — 1.5tCYC + 100 ns1.8 V ≤ VCC < 2.7 V — — 1.5tCYC + 200 ns
REJ03B0293-0100 Rev.1.00 Page 68 of 72Jun 25, 2010
i = 0 to 2
Figure 5.10 Input and Output Timing of Serial Interface
Notes:1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 5.11 Input Timing of External Interrupt INTi and Key Input Interrupt KIi
Table 5.27 Timing Requirements of Serial Interface(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Table 5.28 Timing Requirements of External Interrupt INTi (i = 0 to 7) and Key Input Interrupt KIi (i = 0 to 7)(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group Package Dimensions
REJ03B0293-0100 Rev.1.00 Page 69 of 72Jun 25, 2010
Package DimensionsDiagrams showing the latest package dimensions and mounting information are available in the “Packages” section ofthe Renesas Electronics web site.
INCLUDE TRIM OFFSET.DIMENSION "*3" DOES NOT
NOTE)
DO NOT INCLUDE MOLD FLASH.DIMENSIONS "*1" AND "*2"1.
2.
Detail F
c
A
L1
L
A2
A1
Index mark
x
*3
*1
*2
F
39 27
131
40
52
26
14
ZD
ZE
D
HD
E HE
bp
Terminal cross section
c
bp
c1
b1
Previous CodeJEITA Package Code RENESAS Code
PLQP0052JA-A 52P6A-A
MASS[Typ.]
0.3gP-LQFP52-10x10-0.65
1.0
0.125
0.30
1.1
1.1
0.13
0.200.1450.09
0.370.320.27
MaxNomMin
Dimension in MillimetersSymbol
Reference
10.110.09.9D
10.110.09.9E
1.4A2
12.212.011.8
12.212.011.8
1.7A
0.150.10.05
0.650.50.35L
x
8°0°
c
0.65e
0.10y
HD
HE
A1
bp
b1
c1
ZD
ZE
L1
ey S
S
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group Package Dimensions
REJ03B0293-0100 Rev.1.00 Page 70 of 72Jun 25, 2010
Terminal cross section
b1
c 1
bp
c
2.
1. DIMENSIONS "*1" AND "*2"DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOTINCLUDE TRIM OFFSET.
Index mark
*3
17
32
64
49
1 16
3348
F
*1
*2
xbp
HEE
HD
D
ZD
ZE
Detail F
A cA2
A1
L1
L
P-LQFP64-10x10-0.50 0.3g
MASS[Typ.]
64P6Q-A / FP-64K / FP-64KVPLQP0064KB-A
RENESAS CodeJEITA Package Code Previous Code
1.0
0.125
0.18
1.25
1.25
0.08
0.200.1450.09
0.250.200.15
MaxNomMin
Dimension in MillimetersSymbol
Reference
10.110.09.9D
10.110.09.9E
1.4A2
12.212.011.8
12.212.011.8
1.7A
0.150.10.05
0.650.50.35L
x
8°0°
c
0.5e
0.08y
HD
HE
A1
bp
b1
c1
ZD
ZE
L1
e
y S
S
Terminal cross section
b1
c1
bp
c
2.
1. DIMENSIONS "*1" AND "*2"DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOTINCLUDE TRIM OFFSET.
*3
1 16
17
32
3348
49
64
F
*1
*2
x
Index mark
D
HD
E HE
e bp
ZD
ZE
Detail F
c
A A2
A1
L
L1
Previous CodeJEITA Package Code RENESAS Code
PLQP0064GA-A 64P6U-A/
MASS[Typ.]
0.7gP-LQFP64-14x14-0.80
1.0
0.125
0.35
1.0
1.0
0.20
0.200.1450.09
0.420.370.32
MaxNomMin
Dimension in MillimetersSymbol
Reference
14.114.013.9D
14.114.013.9E
1.4A2
16.216.015.8
16.216.015.8
1.7A
0.20.10
0.70.50.3L
x
8°0°
c
0.8e
0.10y
HD
HE
A1
bp
b1
c1
ZD
ZE
L1
y S
S
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group Package Dimensions
REJ03B0293-0100 Rev.1.00 Page 71 of 72Jun 25, 2010
Detail F
cA
L1
LA1
A2
Index mark
*2
*1
*3
F
80
61
60 41
40
21
201
x
ZE
ZD
E HE
D
HD
e bp
2.
1. DIMENSIONS "*1" AND "*2"DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOTINCLUDE TRIM OFFSET.
Previous CodeJEITA Package Code RENESAS Code
PLQP0080KB-A 80P6Q-A
MASS[Typ.]
0.5gP-LQFP80-12x12-0.50
1.0
0.125
0.18
1.25
1.25
0.08
0.200.1450.09
0.250.200.15
MaxNomMin
Dimension in MillimetersSymbol
Reference
12.112.011.9D
12.112.011.9E
1.4A2
14.214.013.8
14.214.013.8
1.7A
0.20.10
0.70.50.3L
x
10°0°
c
0.5e
0.08y
HD
HE
A1
bp
b1
c1
ZD
ZE
L1
Terminal cross section
c
bp
c 1
b1
y S
S
L1
ZE
ZD
c1
b1
bp
A1
HE
HD
y 0.10
e 0.65
c
0° 8°
x
L 0.35 0.5 0.65
0.05 0.1 0.15
A 1.7
15.8 16.0 16.2
15.8 16.0 16.2
A2 1.4
E 13.9 14.0 14.1
D 13.9 14.0 14.1
ReferenceSymbol
Dimension in Millimeters
Min Nom Max
0.27 0.32 0.37
0.09 0.145 0.20
0.13
0.825
0.825
0.30
0.125
1.0
P-LQFP80-14x14-0.65 0.6g
MASS[Typ.]
FP-80W / FP-80WVPLQP0080JA-A
RENESAS CodeJEITA Package Code Previous Code
INCLUDE TRIM OFFSET.DIMENSION "*3" DOES NOT
NOTE)
DO NOT INCLUDE MOLD FLASH.DIMENSIONS "*1" AND "*2"1.
2.
c1 c
bp
b1
Terminal cross section
A2
c
L
A1
A
L1
Detail F
ZE
ZD
HE
HD
D
E*2
*1
*3
F
80
61
60 41
40
21
201
Index mark
e bp× M
θ
θS
y S
R8C/L35C Group, R8C/L36C Group, R8C/L38C Group, R8C/L3AC Group Package Dimensions
REJ03B0293-0100 Rev.1.00 Page 72 of 72Jun 25, 2010
Terminal cross section
b1
c 1
bp
c
2.
1. DIMENSIONS "*1" AND "*2"DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOTINCLUDE TRIM OFFSET.
Index mark
x
1 25
26
50
5175
76
100
F
*1
*3
*2Z
E
ZD
E
D
HD
HE
bp
Detail F
L1
A2
A1 L
A
c
L1
ZE
ZD
c1
b1
bp
A1
HE
HD
y 0.08
e 0.5
c
0° 8°
x
L 0.35 0.5 0.65
0.05 0.1 0.15
A 1.715.8 16.0 16.2
15.8 16.0 16.2
A2 1.4
E 13.9 14.0 14.1
D 13.9 14.0 14.1
ReferenceSymbol
Dimension in Millimeters
Min Nom Max
0.15 0.20 0.25
0.09 0.145 0.20
0.08
1.0
1.0
0.18
0.125
1.0
Previous CodeJEITA Package Code RENESAS Code
PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6gP-LQFP100-14x14-0.50
e
y S
S
P-QFP100-14x20-0.65 1.8g
MASS[Typ.]
100P6F-APRQP0100JD-B
RENESAS CodeJEITA Package Code Previous Code
0.20.150.13
0.40.30.25
MaxNomMin
Dimension in MillimetersSymbol
Reference
20.220.019.8D
14.214.013.8E
2.8A2
23.122.822.5
17.116.816.5
3.05A
0.20.10
0.80.60.4L
10°0°
c
0.65e
0.10y
HD
HE
A1
bp
ZD
ZE
0.575
0.825
x 0.13
2.
1. DIMENSIONS "*1" AND "*2"DO NOT INCLUDE MOLD FLASH.
All trademarks and registered trademarks are the property of their respective owners.
REVISION HISTORY
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.
Notice1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to
the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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