Amplification & Filtering Flow Diagram Trace Diagram & Two-Layer PCB Virt_gnd_BUFF Virt_gnd_BUFF Virt_gnd_BUFF Virt_gnd_BUFF C69 100n 0 C70 100n Amplifier Amplifier Common Signal Buffer Common Signal Buffer Buffered 2.5 Reference (i.e. "Virtual Ground") ADC Electrode ADC Right Leg Driver High Frequency Filter High Frequency Filter User Input ESD Protection User Input ESD Protection RL Electrode Electrode Electrode 12-Bit 12-Bit Electrode V4 5Vdc 0 0 Voltage Regulator Output 5V Regulated Voltage Voltage Regulation Software Model Not Available Electrode Battery Voltage (4 AA's) V11 1.5Vdc V12 1.5Vdc V13 1.5Vdc V14 1.5Vdc 0 0 C96 .1u 0 C97 10u Virt_gnd_BUFF C98 100n 0 U22 REF3225 1 1 2 2 3 3 4 4 5 5 6 6 0 C99 .47u U23A TLC277/101/TI + 3 - 2 V+ 8 V- 4 OUT 1 R85 100 Vbat 0 U21B TLC277/101/TI + 5 - 6 V+ 8 V- 4 OUT 7 Vbat C92 100n 0 0 Virt_gnd_BUFF C93 100n 0 R84 200k C94 1n C95 1n 0 R59 1.5k - + U19 INA114/BB GS1 2 GS2 15 - 4 + 5 OUT 11 V+ 13 V- 7 REF 10 FB 12 R60 2.2k R61 2.2k Vbat 0 C71 100n C72 100n Virt_gnd_BUFF Virt_gnd_BUFF C73 1u R62 7.5k R63 1Meg C74 220n Virt_gnd_BUFF 0 U20A TLC277/101/TI + 3 - 2 V+ 8 V- 4 OUT 1 U20B TLC277/101/TI + 5 - 6 V+ 8 V- 4 OUT 7 Vbat 0 Vbat 0 R64 100k C75 1n R65 1k U21A TLC277/101/TI + 3 - 2 V+ 8 V- 4 OUT 1 C76 100n C77 1u Vbat 0 C78 100n Virt_gnd_BUFF C79 100n 0 0 Virt_gnd_BUFF C80 100n R66 10k R67 1Meg R68 10k R69 15k C81 33n C82 220n R70 100k R71 8.2k C83 10n Virt_gnd_BUFF Virt_gnd_BUFF Virt_gnd_BUFF C84 100n 0 C85 100n To Digital Board Head Head R72 2.2k R73 2.2k C86 100p C87 10p C88 100p Virt_gnd_BUFF Head Head R74 2.2k R75 2.2k C89 100p C90 10p C91 100p Virt_gnd_BUFF Right Leg Q9 BC547A Q10 BC547A Q11 BC557A Q12 BC557A R76 2.2k R77 2.2k R78 2.2k R79 2.2k Virt_gnd_BUFF R46 2.2k R47 3.4k R48 2.2k Vbat 0 C56 100n C57 100n Virt_gnd_BUFF Virt_gnd_BUFF C58 1u R49 7.5k R50 1Meg C59 220n Virt_gnd_BUFF U16A TLC277/101/TI + 3 - 2 V+ 8 V- 4 OUT 1 0 U16B TLC277/101/TI + 5 - 6 V+ 8 V- 4 OUT 7 Vbat 0 Vbat 0 R51 100k C60 1n R52 1k - + U17 INA114/BB GS1 2 GS2 15 - 4 + 5 OUT 11 V+ 13 V- 7 REF 10 FB 12 U18A TLC277/101/TI + 3 - 2 V+ 8 V- 4 OUT 1 C61 100n C62 1u Vbat 0 C63 100n C64 100n Virt_gnd_BUFF 0 0 Virt_gnd_BUFF C65 100n R53 10k R54 1Meg R55 10k R56 15k Q13 BC547A C66 33n Q14 BC547A C67 220n Q15 BC557A R57 100k Q16 BC557A R58 8.2k C68 10n R80 2.2k R81 2.2k R82 2.2k R83 2.2k Circuit Level Schematic Project 08050 — Remote Monitoring of EEG Signal Through Wireless Sensor Networks Acknowledgements: Dr. Phillips, Dr. Berg M.D., Dr. Hu, Jeffrey G. Lonneville , Rick Tolleson, Ken Snyder, CEMA Lab at CIMS, Vivace Semiconductor, Open EEG Project (http://openeeg.sourceforge.net/doc/) • Design of two-channel analog EEG amplifica- tion and filtering board • Design of wireless communication software ar- chitecture based on mesh networking topology • Design of software for real-time acquisition and display of digitized EEG signals obtained from the analog circuit • Integration of analog and digital systems into a single-supply, low-power device Design Objectives System Level Diagram Analog Design Digital Design Team Leader: Daniel Pontillo Team Members: Ankit Bhutani Jonathan Finamore John Frye Zach McGarvey Project Guide: Dr. Daniel Phillips Project Sponsor: Dr. Fei Hu The analog board acquires EEG signals via passive electrodes from a hu- man subject and processes them through a cascaded amplifier and filter topology as shown in the flow diagram below. The analog design is based on the OpenEEG platform. The schematic is implemented on a two-layer PCB that outputs the processed EEG signals to the ADC on the TelosB. Introduction EEG systems currently used in medical institutions are restricted in their application due to several physical limita- tions. One such limitation involves the signal artifacts created by movement of wires; even small movements of wires within the generated magnetic field causes artifacts of considerable magnitude. As these artifacts obstruct any analysis of procured EEG waveforms, the prevention of these artifacts would significantly improve the ability of medical professionals to perform accurate studies. Consequently, a system in which each electrode functions as a node in wireless mesh network was developed and proposed as a method to eliminate this problem by re- moving the need for wires altogether. Due to the infeasibility of designing such a device to meet all medical stan- dards with the allotted resources, a proof-of-concept system was implemented with the expectation that future it- erations would be miniaturized. Ideally, the system will be small enough to be subdurally implanted in order to improve signal quality. Furthermore, this facilitates long term studies as it is an unobtrusive solution. Results A simulated EEG input of magnitude 100uV is applied to the amplifier in- put. The processed signal is wirelessly transmitted to the base PC and re- constructed. The input and reconstruction are shown. Sampling & Wireless Flow Diagram TelosB The output from the analog hardware is sampled for digitization and wire- less transfer to a base station PC. For this process. a TelosB wireless hard- ware platform is chosen. With its on-board ADC and processor, the analog waveform is captured and encapsulated into transferable packets. A user interface program is created in Java to handle network management and data collection on the base station PC. Custom made GUI showing real time data acquisition