Processor Memory Processor-memory bus I/O Device Bus Adapter I/O Device I/O Device Bus Adapter I/O Device I/O Device Expansion bus I/O Bus.

Computer Architecture CSE 3322

Lecture 25Homework Due May 5: 5.8.4(a), 5.11.1(a)

I/O 1. I/O 2, ( see Handout / Web Site)

Final Exam Thurs May 14 2pm GACB 103

Processor MemoryProcessor-memory bus

I/ODevice

BusAdapter

I/ODevice

I/ODevice

BusAdapter

I/ODevice

I/ODevice

Expansion bus

I/O Bus

The Operating System ( OS) controls I/O processes


1. OS contains the low level programs that control theI/O device. ( Device Drivers, usually provided bythe device manufacturer)


1. OS contains the low level programs that control theI/O device. ( Device Drivers, usually provided bythe device manufacturer)

2. Limits access to Users for Protection and ResourceScheduling. ( Some programs violate this)


1. Contains the low level programs that control theI/O device. ( Device Drivers, usually provided bythe device manufacturer)


3. OS must give commands to devices and readsstatus from Devices




3. OS must give commands to devices and readstatus from Devices

4. Devices must notify the OS of changes





4. Devices must notify the OS of changes5. Data must be transferred between memory and

an I/O device

OS must give commands to devices and readstatus from Devices

1. Special I/O instructions• Store Register xx in Device Address yy


1. Special I/O instructions• Store Register xx in Device Address yy• Device address is put on I/O control lines and

the data is put on the I/O data lines



the data is put on the I/O data lines• Write from Device Address yy to a Register

or Memory location



the data is put on the I/O data lines• Write from Device Address yy to a Register

or Memory location• Constraining for unknown devices


1. Special I/O instructions2. Memory Mapped I/O

• Memory Address Space is assigned to Devices.



• Memory Address Space is assigned to Devices. • A Write to that address goes to a device controller

register and not to the memory ( Commands)




register and not to the memory ( Commands)• A Read of that address comes from a device

controller register and not the memory ( Status)




register and not to the memory ( Commands)• A Read of that address comes from a device

controller register and not the memory ( Status)• Memory Map defined by software for the installed

I/O controllers ( Flexibility and Expandability)

Devices must notify the OS of changes

1. Polling• Processor periodically reads the status of the I/O

Ex: key depressed, print complete, buffer full



Ex: key depressed, print complete, buffer full• Processor is in complete control



Ex: key depressed, print complete, buffer full• Processor is in complete control• Polling loop in OS is overhead



Ex: key depressed, print complete, buffer full• Processor is in complete control• Polling loop in OS is overhead• Effective on slow devices that initiate I/O

Ex: keyboard and Mouse




Ex: keyboard and Mouse




Ex: keyboard and Mouse• Not efficient for fast devices


1. Polling2. Interrupt-driven

• Device controller asserts interrupt signal line andloads interrupt status register.




• Processor checks for interrupt at the start ofeach new instruction ( in parallel)





• Processor recognizes interrupts on a priority basis





• Processor recognizes interrupts on a priority basis• OS services the interrupt based on the Cause

register or vectored interrupt





• Processor recognizes interrupts on a priority basis• OS services the interrupt based on the Cause

register or vectored interrupt• Enables a device to signal that data is ready to be

transferred or an operation has been completed





4. Devices must notify the OS of changes5. Data must be transferred between memory and

an I/O device

Data must be transferred between memory and an I/O device

1. Processor Control• Data and Status transferred by Special Instruction

or Memory Mapped I/O



or Memory Mapped I/O• Polling or Interrupts are used



or Memory Mapped I/O• Polling or Interrupts are used• Fast device with blocks of data can excessively

load processorEx: hard disk and display


1. Processor Control2. Direct Memory Access ( DMA)

• I/O controller transfers block of data between deviceand memory independent of the processor




• DMA transfer process1. Processor initiates the device operation ( memory

address, number of bytes, enable bus master)





address, number of bytes, enable bus master)2. DMA controller directly transfers block of data

between memory and device, under arbitration






between memory and device, under arbitration3. DMA sends interrupt to notify completion or error






between memory and device, under arbitration3. DMA sends interrupt to notify completion or error

• Enables the processor to continue to operate duringdata transfer

CPU/Memory

Control

Data

I/O 1 I/O 2 I/O 3

I/O bus

A bus master controls access to the bus

CPU/Memory

Control

Data

I/O 1 I/O 2 I/O 3

I/O bus

A bus master controls access to the bus• Slaves request bus access

CPU/Memory

Control

Data

I/O 1 I/O 2 I/O 3

I/O bus

A bus master controls access to the bus• Slaves request bus access• The bus master generates controls to make the

transfer

CPU/Memory

Control

Data

I/O 1 I/O 2 I/O 3

I/O bus

A bus master controls access to the bus• Slaves request bus access• The bus master generates controls to make the

transfer• The processor is always a bus master and memory

is always a slave

Typically want multiple bus masters, so need to decidewhich bus master gets control.

Typically want multiple bus masters, so need to decidewhich bus master gets control.

Bus Arbitration

Arbitration schemes are used to grant the bus based on:

1. Priority2. Avoid lockout ( fairness)

I/O and Caches

1. Polling or Interrupt- driven I/O under processorcontrol goes through cache ( virtual and performance)

I/O and Caches


2. DMA goes direct to main memory• Cache coherency problem

( Cache and memory different)Cache flushing with hardware support

I/O and Caches


2. DMA goes direct to main memory• Cache coherency problem

( Cache and memory different)Cache flushing with hardware support

• Page boundaries in virtual memoryStay within page boundaries or use virtualaddresses

Y Counter

X counter

MOUSE

The movement of the Mouseincrements or decrements the X and Y counters

Y Counter

X counter

MOUSE

The movement of the Mouseincrements or decrements the X and Y counters.

If the location of the cursor isupdated 20 times per second it appearssmooth to a human.

Y Counter

X counter

MOUSE

The movement of the Mouseincrements or decrements the X and Y counters.

If the location of the cursor isupdated 20 times per second it appearssmooth to a human.

1. Poll at 40 times per second.2. Polling I/O routine takes 800 clock cycles3. Each counter is 2 Bytes, Sample is 1 Word4. Clock Rate is 500 MHz

GIVEN:


GIVEN:MOUSE

% Processor Usage?Each Polling Cycle is 1/40 sec

Number of clock cycles each polling cycle = 500x106 clock cycles/sec * 1/40 sec = 12.5 x 106


GIVEN:MOUSE


Number of clock cycles each polling cycle = 500x106 clock cycles/sec * 1/40 sec = 12.5 x 106 % Processor Usage = 800 = 64 x 10-6 = 0.0064 % 12.5 x 106


GIVEN:MOUSE


Number of clock cycles each polling cycle = 500x106 clock cycles/sec * 1/40 sec = 12.5 x 106 % Processor Usage = 500 = 40 x 10-6 = 0.004 % 12.5 x 106

Transfer Rate = 4 bytes * 40 times/ sec = 160 bytes / sec

HARD DRIVE

Platters6 Surfaces and Heads Tracks or Cylinders

Sectors

HARD DRIVE


Sectors

Seek Time-Move Headto Track - Min, Max,Ave.

HARD DRIVE


Sectors


Rotational latency –Time for the sectorto rotate to the Head –

Average is ½ rotation time

HARD DRIVE

Given: Average Seek Time = 10 msRotational speed = 5400 RPMSector size = 512 bytesData Rate = 5 MBpsec

What is the average transfer rate?

HARD DRIVE


Sectors


Rotational latency –Time for the sectorto rotate to the Head –

Average is ½ rotation time

HARD DRIVE

Given: Average Seek Time = 10 msRotational speed = 5400 RPMSector size = 512 bytesData Rate = 5 MBps

What is the average transfer rate from the disk?

Time to transfer a sector = 10 ms + ½ (60 sec/min) + 512 bytes

5400 rev/min 5 x 106 bytes/sec

= 10 + 5.56 + 0.102 ms= 15.67 ms

HARD DRIVE

Given: Average Seek Time = 10 msRotational speed = 5400 RPMSector size = 512 bytesData Rate = 5 MBps

What is the average transfer rate from the disk?

Time to transfer a sector = 10 ms + ½ (60 sec/min) + 512 bytes

5400 rev/min 5 x 106 bytes/sec= 10 + 5.56 + 0.102 ms = 15.67 ms

Average transfer rate = 512 bytes = 32.7 KBps from the disk 15.67ms

HARD DRIVE

What is the time to transfer 4 KB from the disk under DMA?Given: 1. OS requires 1000 clock cycles for initial set up and

500 clock cycles to handle completion interrupt 2. Clock is 500 Mhz 3. Average transfer rate from the disk is 32.7 KBps

HARD DRIVE


500 clock cycles to handle completion interrupt 2. Clock is 500 MHz 3. Average transfer rate from the disk is 32.7 KBps

Transfer time for 4 KB = 1000 clocks + 4 K B + 500 clocks

500 MHz 32.7 KBps 500 MHz

HARD DRIVE


500 clock cycles to handle completion interrupt 2. Clock is 500 MHz 3. Average transfer rate from the disk is 32.7 KBps

Transfer time for 4 KB = 1000 clocks + 4 K B + 500 clocks

500 MHz 32.7 KBps 500 MHz

= 0.002 ms + 122.32 ms + 0.001 ms

HARD DRIVE

What is the % Processor usage for this transfer? Given: 1. OS requires 1000 clock cycles for initial set up and

500 clock cycles to handle completion interrupt 2. Clock is 500 MHz 3. Average transfer rate from the disk is 32.7 KBps 4. Time to transfer 4 KB = 122.32 ms

HARD DRIVE



Processor time = 1000 + 500 clocks = 0.003 ms 500 MHz

HARD DRIVE



Processor time = 1000 + 500 clocks = 0.003 ms 500 MHz

% Processor usage = 0.003 = 0.0025 % 122.32 Assuming no

memory contention

A Optical disk transfers data to the processor in 32 bit units and has a data rate of 1M Bytes per sec. No data transfers can be missed. Consider a computer with a 900 MHz clock rate and a polling loop of 1500 clock cycles that includes the cycles to transfer a 32 bit unit.

What is the required polling rate to not miss any data?

A Optical disk transfers data to the processor in 32 bit units and has a data rate of 1M Bytes per sec. No data transfers can be missed. Consider a computer with a 900 MHz clock rate and a polling loop of 1500 clock cycles that includes the cycles to transfer a 32 bit unit.

What is the required polling rate to not miss any data?

Polling Rate = 1M B/s * 8 bits/Byte = 0.25 M units/sec 32 b/sample

What is the % Processor Usage?


Polling period = 1/ 0.25 M = 4 microsec



Processor Time = 1500 Clk Cycles = 1.67 microsec 900 M Hz



Processor Time = 1500 Clk Cycles = 1.67 microsec 900 M Hz

% Processor Usage = 1.67 / 4 = 41.75%

Consider a interrupt driven I/O instead of polling with a interrupt routine of 2000 clock cycles that includes the cycles to transfer a 32 bit unit each interrupt. If the optical disk is active transferring data 5% of the time, what is the % Processor Usage?


Processing time each interrupt = 2000 clock cycles 900 Mhz

= 2.222 microsec



= 2.222 microsecInterrupt period = 32 bits/ unit during transfer 8 bits/byte * 1 M bytes/sec

= 4 microsec/transfer



= 2.222 microsecInterrupt period = 32 bits/ unit during transfer 8 bits/byte * 1 M bytes/sec

= 4 microsec/transfer

% Processor usage = 5% * 2.222x10-6 = 0.125 % 4 x 10-6

Review for Exam III

Chapter 7: Memory Hierarchy

Organization and operation of Caches:Direct, 2-way and 4-way associative with

multiword blocks.Memory Organizations interfacing with

Cache

Review for Exam III


Organization and operation of Caches:Direct, 2-way, 4-way and Fully associative

with multiword blocks.Memory Organizations interfacing with

CacheCache Performance Measures: Ave Memory

Access Time, Hit Rate, Miss Rate, MissPenalty, Effective CPI

Review for Exam III


Organization and operation of Caches:Direct, 2-way and 4-way associative with

multiword blocks.Memory Organizations interfacing with

CacheCache Performance Measures: Ave Memory

Access Time, Hit Rate, Miss Rate, MissPenalty, Effective CPI

Organization and operation of Virtual Memory:Page Tables, TLB, TLB Miss, Page Fault

Review for Exam III

Chapter 8: Input / OutputI/O Busses

Review for Exam III

Chapter 8: Input / OutputI/O BussesPolling, Interrupt Driven, DMA

Review for Exam III

Chapter 8: Input / OutputI/O BussesPolling, Interrupt Driven, DMAPerformance: I/O Rates, % Processor Usage

Processor Memory Processor-memory bus I/O Device Bus Adapter I/O Device I/O Device Bus Adapter I/O Device I/O Device Expansion bus I/O Bus.

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