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EEE 531: Semiconductor Device Theory I – Dragica Vasileska PN Junctions Theory Dragica Vasileska Department of Electrical Engineering Arizona State University 1. PN-Junctions: Introduction to some general concepts 2. Current-Voltage Characteristics of an Ideal PN-junction (Shockley model) 3. Non-Idealities in PN-Junctions 4. AC Analysis and Diode Switching
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Pn Junctions Theory

May 22, 2017

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Page 1: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

PN Junctions TheoryDragica Vasileska

Department of Electrical EngineeringArizona State University

1. PN-Junctions: Introduction to some general concepts

2. Current-Voltage Characteristics of an Ideal PN-junction (Shockley model)

3. Non-Idealities in PN-Junctions4. AC Analysis and Diode Switching

Page 2: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

1. PN-junctions - General Consideration:• PN-junction is a two terminal device.• Based on the doping profile, PN-junctions can be

separated into two major categories:- step junctions- linearly-graded junctions

p-side n-side

AD NN

p-side n-side

AD NN ax

Step junction Linearly-graded junction

Page 3: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(A) Equilibrium analysis of step junctions

(a) Built-in voltage Vbi:

(b) Majority- minority carrier relationship:

CE

VE

iEFE

biqV

W)(x

x-qNA

qND

)(xV

x

biV

)(xE

xmaxE

px nx

+-

p-side n-side

2200

0

0

lnln

expexp

i

DAT

i

npBbi

BFiip

BiFin

niFpFibi

nNNV

n

npqTkV

TkEEnpTkEEnn

EEEEqV

Tbinp

Tbipn

VVnnVVpp

/exp/exp

00

00

Page 4: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(c) Depletion region width: Solve 1D Poisson equation using depletion charge approximation, subject to the following boundary condi-tions:

p-side:

n-side:

Use the continuity of the two solutions at x=0, and charge neutrality, to obtain the expression for the depletion region width W:

0)()(,)(,0)( pnbinp xExEVxVxV

202

)( ps

Ap xx

kqNxV

bins

Dn Vxx

kqNxV

2

02)(

DA

biDAs

nDpA

np

pn

NqNVNNkW

xNxNVV

Wxx)(2)0()0( 0

Page 5: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(d) Maximum electric field:The maximum electric field, which occurs at the metallurgical junction, is given by:

(e) Carrier concentration variation:

)(00max

DAs

DA

x NNkWNqN

dxdVE

105

107

109

1011

1013

1015

0 0.5 1 1.5 2 2.5 3 3.5

n [cm-3]

p [cm-3]

Con

cent

ratio

n [c

m-3

]

Distance [mm]

cmkVEcmkVE

mWcmNN

sim

DC

calc

DA

/93.8/36.9

23.110

)max(

)max(

315

m

Page 6: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

cmkVEcmkVEmWcmNN

simDCcalc

DA/93.8,/36.9,23.1

10

)max()max(

315

m

-1015

-5x1014

0

5x1014

1015

0 0.5 1 1.5 2 2.5 3 3.5

(x)

/q [

cm-3

]

Distance [mm]

-10

-8

-6

-4

-2

0

0 0.5 1 1.5 2 2.5 3 3.5E

lect

ric fi

eld

[kV

/cm

]Distance [mm]

Page 7: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

cmkVEcmkVEmWcmNcmN

simDCcalc

DA/67,/53.49,328.0

10,10

)max()max(

318316

m

-1017

-5x1016

0

5x1016

1017

0.6 0.8 1 1.2 1.4

(x)

/q [

cm-3

]

Distance [mm]

-70

-60

-50

-40

-30

-20

-10

0

10

0.6 0.8 1 1.2 1.4E

lect

ric fi

eld

[kV

/cm

]Distance [mm]

Page 8: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(f) Depletion layer capacitance: Consider a p+n, or one-sided junction, for which:

The depletion layer capacitance is calculated using:

D

bisqN

VVkW 02

02

0 )(21)(2

sD

bi

bi

sDDckqN

VVCVV

kqNdV

dWqNdVdQC

VVbi V

21 C

DNslope 1

Forward biasReverse bias

Measurement setup:

WdW

~

V

vac

Page 9: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(B) Equilibrium analysis of linearly-graded junction:

(a) Depletion layer width:

(c) Maximum electric field:

(d) Depletion layer capacitance:

Based on accurate numerical simulations, the depletion layer capacitance can be more accurately calculated if Vbi is replaced by the gradient voltage Vg:

3/1012

qaVVkW bis

3/120

2

12

VV

qakCbi

s

0

2

max 8

skqaWE

30

2

8ln

32

i

TsTg

qnVkaVV

Page 10: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(2) Ideal Current-Voltage Characteristics:Assumptions:• Abrupt depletion layer approximation• Low-level injection injected minority carrier density

much smaller than the majority carrier density• No generation-recombination within the space-charge

region (SCR)

(a) Depletion layer:

CE

VE

FnEqV

FpE

W

Tnnn

Tppp

Ti

VVpxp

VVnxnVVnnp

/exp)(

/exp)(/exp

0

0

2

px nx

Page 11: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(b) Quasi-neutral regions:• Using minority carrier continuity equations, one arrives at

the following expressions for the excess hole and electron densities in the quasi-neutral regions:

npT

pnT

LxxVVpp

LxxVVnn

eenxn

eepxp/)(/

0

/)(/0

)1()(

)1()(

)(xnp )(xpn

0np0pn

px nx x

Forward bias

Reverse bias

Space-chargeregion W

Page 12: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

• Corresponding minority-carriers diffusion current densities are:

npT

pnT

LxxVV

n

pndiffn

LxxVV

p

npdiffp

eeL

nqDxJ

eeL

pqDxJ

/)(/0

/)(/0

)1()(

)1()(

px nx x

diffpJ minoritydiff

nJ minority

)()( pdiffnn

diffptot xJxJJ

No SCR generation/recombination

driftn

diffn JJ majority drift

pdiffp JJ majority

totJ

Shockley model

Page 13: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(c) Total current density:• Total current equals the sum of the minority carrier diffu-

sion currents defined at the edges of the SCR:

• Reverse saturation current IS:

1)()(

/00

TVV

n

pn

p

np

pdiffnn

diffptot

eLnD

LpD

qA

xIxII

An

n

Dp

pi

n

pn

p

nps NL

DNL

DqAn

LnD

LpD

qAI 200

I

V

Ge Si GaAs

Page 14: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(d) Origin of the current flow:

CE

VE

FnEqV

FpE

W

Forward bias:

CE

VEFnE

qV

FpE

W

Reverse bias:

VVq bi VVq bi

Reverse saturation current is due to minority carriers being collected over a distance on the order of the diffusion length.

Ln

Lp

Page 15: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(e) Majority carriers current:• Consider a forward-biased diode under low-level injection

conditions:

• Total hole current in the quasi-neutral regions:

)(xpn0np

nx x

0nn)(xnn

Quasi-neutrality requires:

This leads to:

)()( xpxn nn

)()( xJDD

xJ diffp

p

ndiffn

)()()()( xJxJxJxJ diffp

driftp

diffp

totp

Page 16: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

• Electron drift current in the quasi-neutral region:

)()(

1)(),(1)( xJxqn

xExJDD

JxJ diffn

n

diffp

p

ntot

diffn m

x)(xJ diff

p

)(xJ diffn

)(xJ driftn

)()()( xJxJxJ driftn

diffn

totn

totJ

)()( xJxJ diffp

diffn

Page 17: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(f) Limitations of the Shockley model:• The simplified Shockley model accurately describes IV-

characteristics of Ge diodes at low current densities.

• For Si and Ge diodes, one needs to take into account several important non-ideal effects, such as:

Generation and recombination of carriers within the depletion region.

Series resistance effects due to voltage drop in the quasi-neutral regions.

Junction breakdown at large reverse biases due to tun-neling and impact ionization effects.

Page 18: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

3. Non-Idealities in PN-junctions:(A) Generation and Recombination Currents

Continuity equation for holes:

Steady-state and no light genera-

tion process:

• Space-charge region recombination current:

scrJ

ppp RG

xJ

qtp

1

0,0 pGtp

n

p

n

p

n

px

xpscr

x

xpppnp

x

xp

dxRqJ

dxRqxJxJxdJ )()()(

Page 19: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

Reverse-bias conditions:• Concentrations n and p are negligible in the depletion

region:

• Space-charge region current is actually generation current:

• Total reverse-saturation current:

TkEE

TkEEn

pnn

RB

tin

B

itpg

g

i

np

i expexp,11

2

Generation lifetime

VVWqn

JWqn

JJ big

igen

g

igenscr

gensVVscrVV

s JJJeJJT

T

1/

Page 20: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

• Generation current dominates when ni is small, which is always the case for Si and GaAs diodes.

I (log-scale)

V (log-scale)sAJ

genAJ

CE

VEFnE

FpE

W

IV-characteristicsunder reverse bias conditions

Generated carriers are swept away from the

depletion region.

Page 21: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

Forward-bias conditions:• Concentrations n and p are large in the depletion region:

• Condition for maximum recombination rate:

• Estimate of the recombination current:

11

/2/2 1

ppnnen

Rennpnp

VViVV

i

TT

nprecVV

rec

i

np

VVi

VVi

TT

T

en

pnen

R

enpn

,2//2

max

2/

TVV

rec

iscr e

WqnJ 2/max

Recombination lifetime

Page 22: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

• Exact expression for the recombination current:

• Corrections to the model:

• Total forward current:

ideality factor. Deviations of from unity represent an important measure for the recombination current.

0

2/ 2,12

,

s

binDnp

npT

VV

rec

iscr k

VVqNEE

VeqnJ T

TrVmV

rec

iscr e

qnJ /

11 /,

//

TTrT VVeffs

VmV

rec

iVVs eJe

qneJJ

Page 23: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

• Importance of recombination effects:

Low voltages, small ni recombination current dominates

Large voltages diffusion current dominates

log(I)

VdAJ

scrAJAJ

Page 24: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(B) Breakdown Mechanisms

• Junction breakdown can be due to:

tunneling breakdown avalanche breakdown

• One can determine which mechanism is responsible for the breakdown based on the value of the breakdown voltage VBD :

VBD < 4Eg/q tunneling breakdown

VBD > 6Eg/q avalanche breakdown

4Eg/q < VBD < 6Eg/q both tunneling and avalanche mechanisms are responsible

Page 25: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

Tunneling breakdown:• Tunneling breakdown occurs in heavily-doped pn-

junctions in which the depletion region width W is about 10 nm.

W

EF

EC

EV

Zero-bias band diagram: Forward-bias band diagram:

W

EFn

EC

EV

EFp

Page 26: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

EFnEC

EV

EFp

Reverse-bias band diagram: • Tunneling current (obtained by using WKB approximation):

Fcr average electric field in the junction

• The critical voltage for tunneling breakdown, VBR, is estimated from:

• With T, Eg and It .

cr

g

g

crt qF

Em

E

VAFqmI

324

exp4

22/3*

2/122

3*

SBRt IVI 10)(

Page 27: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

Avalanche breakdown:• Most important mechanism in junction breakdown, i.e. it

imposes an upper limit on the reverse bias for most diodes.

• Impact ionization is characterized by ionization rates n and p, defined as probabilities for impact ionization per unit length, i.e. how many electron-hole pairs have been generated per particle per unit length:

- Ei critical energy for impact ionization to occur- Fcr critical electric field- mean-free path for carriers

cr

ii Fq

Eexp

Page 28: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

EFnEC

EV

EFp

Expanded view of thedepletion region

Avalanche mechanism:

Generation of the excess electron-hole pairs is due to impact ionization.

Page 29: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

• Description of the avalanche process:

dxJJ nnn dxnJ

dxJJ nnp pJ

Impact ionization initiated by electrons.

dxJJ ppn dxnJ

dxJJ ppp pJ

Impact ionization initiated by holes.

.

0,0

constJJJ

dxdJ

dxdJ

dxdJ

dxdJ

pn

pn

pn

-

Multiplication factors forelectrons and holes:

)()0(

,)0()(

WJJ

MJ

WJM

p

pp

n

nn

Page 30: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

• Breakdown voltage voltage for which the multiplication rates Mn and Mp become infinite. For this purpose, one needs to express Mn and Mp in terms of n and p:

W dx

pp

W dx

nn

ppnnp

ppnnn

dxeM

dxeM

JJdx

dJ

JJdx

dJ

xpn

xpn

0

'

0

'

0

0

11

11

The breakdown condition does not depend on whichtype of carrier initiated the process.

Page 31: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

• Limiting cases:

(a) n=p (semiconductor with equal ionization rates):

(b) n>>p (impact ionization dominated by one carrier):

W

W

p

ppp

W

W

n

nnn

dxMdx

M

dxMdx

M

0

0

0

0

1

111

1

111

W

n

dx

n dxeM

Wn

010

Page 32: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

Breakdown voltages:

(a) Step p+n-junction

pW nW

p n

)(xFmaxF

• For one sided junction we can make the following approximation:

• Voltage drop across the depletion region on the n-side:

• Maximum electric field:

• Empirical expression for the breakdown voltage VBD:

npn WWWW

WFVWFV BDnn maxmax 21

21

x

2max

0

0max 2

FqNk

Vk

WqNF

D

sBD

s

D

cmkVNE

V DgBD 16

2/3

101.160

Page 33: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(b) Step p+-n-n+ junction

pW 1W

p n

)(xFmaxF

• Extension of the n-layer large:

• Extension of the n-layer small:

• Final expression for the punch-through voltage VP:

mBD WFV max21

11max 21

21 WWFWFV mmP

x

mW

n

1F

mmBDP W

WWW

VV 11 2

Page 34: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(4) AC-Analysis and Diode Switching

(a) Diffusion capacitance and small-signal equivalent circuit• This is capacitance related to the change of the minority

carriers. It is important (even becomes dominant) under forward bias conditions.

• The diffusion capacitance is obtained from the device impedance, and using the continuity equation for minority carriers:

• Applied voltages, currents and solution for pn:p

nnp

n p

dx

pdD

dtpd

2

2

0110

0110,)(,)(

JJeJJtJVVeVVtV

ti

ti

ti

nnsn expxptxp )()(),( 1

Page 35: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

• Equation for pn1(x):

• Boundary conditions:

• Final expression for pn1(x):

0)(

0)(1

2'

12

12

121

2

p

nnn

pp

pn

L

xp

dx

pdxp

Di

dx

pd

TT

nn

T

ti

nn

nnn

VV

VVp

pV

eVVptp

pptp

0101

100

10

exp)0(exp),0(

0)(),(

'

0101 expexp),(

pTT

nn L

xVV

VVp

txp

Page 36: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

• Small-signal hole current:

• Low-frequency limit for the admittance Y:

• RC-constant:

1010

0

11 exp1 YV

VV

iVL

VpAqDdx

dpAqDI

Tp

Tp

np

x

np

pTT

pTp

npdif

TT

VVs

TTp

npd

difdpTTp

np

VI

VV

VLpAqD

C

IdVdI

VI

VeI

VV

VLpAqD

G

CiGiVV

VLpAqD

Y

T

21exp

21

current Forward,exp

211exp

00

/00

00

0

2p

difdCR

The characteristic time constant is on the order of the minority carriers lifetime.

Page 37: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

• Equivalent circuit model for forward bias:

• Bias dependence:

deplC

difC

dd G

R 1

sR sL

C

aV

difC

deplC

Page 38: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

(b) Diode switching

• For switching applications, the transition from forward bias to reverse bias must be nearly abrupt and the transit time short.

• Diode turn-on and turn-off characteristics can be obtained from the solution of the continuity equations:

p

ppp

p

pp

p

p

npDpp

n

Qdt

dQtItI

QtI

dtdQ

px

Jq

RJqdt

pd

)()()(

11 1

Valid for p+n diodeQp(t) = excess hole charge

Page 39: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

Diode turn-on:

• For t<0, the switch is open, and the excess hole charge is:

• At t=0, the switch closes, and we have the following boundary condition:

0)0()0( pp QtQ

0)0()0( pp QQ

p+ n

t=0

IF

pp tFp

tp eIBeAtQ

//1)(

• Final expression for the excess hole charge:

Page 40: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

S

FTa

VVpnp

LxVVnn

II

VV

eLAqpQeepxp TapTa

1ln

11)( /0

//0

• Graphical representation:

• Steady state value for the bias across the diode:

)(tQp

t

Fp I

),( txpn

x0np

t increasing

Slope almost constant

Page 41: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

Diode turn-off:

• For t<0, the switch is in position 1, and a steady-state situation is established:

• At t=0, the switch is moved to position 2, and up until time t=t1 we have:

• The current through the diode until time t1 is:

RV

I FF

0),0( 0 ann Vptp

p+ n

t=0

VF

R

VR

R

1 2

RV

I RR

Page 42: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

• To solve exactly this problem and find diode switching time, is a rather difficult task. To simplify the problem, we make the crucial assumption that IR remains constant even beyond t1.

• The differential equation to be solved and the initial condition are, thus, of the form:

• This gives the following final solution:

• Diode switching time:

Fpppp

ppR IQQ

Qdt

dQI

)0()0(,

ptRFpRpp eIIItQ

/)(

R

Fprrrrp I

IttQ 1ln0)(

Page 43: Pn Junctions Theory

EEE 531: Semiconductor Device Theory I – Dragica Vasileska

• Graphical representation:

),( txpn

x0np

t=0

Slope almostconstant

t=ts

ttrr

)(tVa

FI

RI

stRI1.0

rrt

RV

t

t

ts switching timetrr reverse recovery time