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LECTURE 050 - PN JUNCTIONS AND CMOS TRANSISTORSLECTURE ORGANIZATION
Outline• pn junctions• MOS transistors• Layout of MOS transistors• Parasitic bipolar transistors in CMOS technology• High voltage CMOS transistors• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 29-43
PN JUNCTIONSHow are PN Junctions used in CMOS?• PN junctions are used to electrically isolate one semiconductor region from another• PN diodes• ESD protection• Creation of the thermal voltage for bandgap purposes• Depletion capacitors – voltage variable capacitors (varactors)
Components of a pn junction:1.) p-doped semiconductor – a semiconductor having atoms containing a lack ofelectrons (acceptors). The concentration of acceptors is NA in atoms per cubiccentimeter.2.) n-doped semiconductor – a semiconductor having atoms containing an excess ofelectrons (donors). The concentration of these atoms is ND in atoms per cubiccentimeter.
W1 = Depletion width on p side W2 = Depletion width on n side
1. Doped atoms near the metallurgical junction lose their free carriers by diffusion.2. As these fixed atoms lose their free carriers, they build up an electric field, which
opposes the diffusion mechanism.3. Equilibrium conditions are reached when:
Current due to diffusion = Current due to electric field
Influence of Doping Level on the Depletion RegionsIntuitively, one can see that the depletion regions are inversely proportional to the dopinglevel. To achieve equilibrium, equal and opposite fixed charge on both sides of thejunction are required. Therefore, the larger the doping the smaller the depletion regionon that side of the junction.The equations that result are:
W1 = 2 ( o -vD)
qNA 1 +NAND
1
NA
and
W2 = 2 ( o -vD)
qND 1 +NDNA
1
ND
Assume that vD = 0, o = 0.637V and ND = 1017 atoms/cm3. Find the p-side depletionregion width if NA = 1015 atoms/cm3 and if NA = 1019 atoms/cm3:
For NA = 1015 atoms/cm3 the p-side depletion width is 0.90 μm.
For NA = 1019 atoms/cm3 the p-side depletion width is 0.9 nm.
Forward-Biased PN JunctionsWhen the pn junction is forward-biased, the potential barrier is reduced and significantcurrent begins to flow across the junction. This current is given by:
iD = Is expvDVt
- 1 where Is = qADppno
Lp +Dnnpo
Ln qAD
L ni
2
N = KT 3exp-VGO
Vt
Graphically, the iD versus vD characteristics are given as:
-40 -30 -20 -10 0 10 20 30 40vD/Vt
iDIs
10
8
6
4
2
0
x1016
x1016
x1016
x1016
x1016
-5
0
5
10
15
20
25
-4 -3 -2 -1 0 1 2 3 4
iDIs
vD/Vt
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ln(iD/Is)
vD
Decade currentchange/60mV or Octave currentchange/18mV
Physical Structure of MOS Transistors in an n-well Technology
p+ p p- Metal Salicide n- n n+ Oxide Poly
070322-02
Polycide Gate Ox
n+
n-well
n+
p-well
n+
Substrate
n+
Substrate Salicide Substrate Salicide
Shallow Trench
Isolation
Well Salicide
p+ p+
Shallow Trench
Isolation
n+ n+
W
L
W
L
Width (W) of the MOSFET = Width of the source/drain diffusionLength (L) of the MOSFET = Width of the polysilicon gate between the S/D diffusionsNote that the MOSFET is isolated from the well/substrate by reverse biasing theresulting pn junction
Enhancement MOSFETsThe channel of an enhancement MOSFET is formed when the proper potential is appliedto the gate of the MOSFET. This potential inverts the material immediately below thegate to the same type of impurity as the source and drain forming the channel.
060205-06
VDS<VDS(sat)VGS=0V
S G DVDS
VDS<VDS(sat)0V<VGS<VT
S G DVDS
VDS<VDS(sat)
S G DVDS
VGS>VT
Cutoff Weak Inversion Strong Inversion
VT = Gate-bulk work function ( MS) + voltage to change the surface potential (-2 F)+ voltage to offset the channel-bulk depletion charge (-Qb/Cox)+ voltage to compensate the undesired interface charge (-Qss/Cox)
Depletion Mode MOSFETThe channel is diffused into the substrate so that a channel exists between the source anddrain with no external gate potential.
Fig. 4.3-4n+ n+
p substrate (bulk)
Channel Length, L
n-channel
Polysilicon
Bulk Source Gate Drain
p+
Chann
el W
idth,
W
The threshold voltage for a depletion mode NMOS transistor will be negative (a negativegate potential is necessary to attract enough holes underneath the gate to cause thisregion to invert to p-type material).
Weak inversion operation occurs when the appliedgate voltage is below VT and occurs when the surfaceof the substrate beneath the gate is weakly inverted.
Regions of operation according to the surfacepotential, S.
S < F : Substrate not inverted
F < S < 2 F : Channel is weakly inverted(diffusion current)
Thermal and Stress Effects• Oxide gradients – use common centroid geometry layout• Stress gradients – use proper location and common centroid geometry layout• Thermal gradients – keep transistors well away from power devices and use common
centroid geometry layout with interdigitated transistorsExamples of Common Centroid Interdigitated transistor layout:
MOS Transistor LayoutPhotolithographic invariance (PLI) are transistors that exhibit identical orientation. PLIcomes from optical interactions between the UV light and the masks.Examples of the layout of matched MOS transistors:1.) Examples of mirror symmetry and photolithographic invariance.
The voltage drop from drain to source is,VDS = Vp + Vd = 0.5(Emaxxp + Emaxxd) = 0.5Emax(xp + xd)
Emax and xp are limited by hot carrier generation and channel length modulationrequirements whereas these limitations do not exist for xd.Therefore, to get extended voltage transistors, make xd larger.
High Voltage ArchitecturesThe objective is to create a lightly doped, extended drain region where the high voltageof the drain can drop down to a level that will not cause the gate oxide to breakdown.LOCOS Architecture:
Lateral DMOS (LDMOS) Using LOCOS CMOS TechnologyThe LDMOS structure is designed to provide sufficient lateral dimension and to preventoxide breakdown by the higher drain voltages.One possible implementation using LOCOS technology:
n well
p substrate
p epi p epi
n+ n+
071025-01
xd xdp-bodyp-body
Drain DrainGate Source/Bulk Gate
n+ n+ p+
• Structure is symmetrical about the source/bulk contact• Channel is formed in the p region under the gates• The lightly doped n region between the drain side of the channel and the n+ drain
contact (xd) increases the depletion region width on the drain side of the channel/drainpn junction resulting in larger values of vDS.
Lateral DMOS (LDMOS) Using DSM CMOS TechnologyCross-section of anNLDMOS using DSMtechnology:
Differences between an NLDMOS and NMOS:• Asymmetry• Non-uniform channel• Current flow (not all at the surface)• No self-alignment (larger drain-gate overlap
capacitance)• Note the extended drift region on the drain side of the
- Electrical isolation, pn diodes, ESD protection, depletion capacitors• Depletion region widths are inversely proportional to the doping• Depletion region widths are proportional to the reverse bias voltage• Ohmic metal-semiconductor junctions require a highly doped semiconductor• MOSFETs can be:
- Enhancement – the applied gate voltage forms the channel- Depletion – the channel is physically constructed in fabrication
• The threshold voltage of MOSFETs consists of the following components:- Gate bulk work function ( MS)- Voltage to change the surface potential (-2 F)- Voltage to offset the channel-bulk depletion charge (-Qb/Cox)- Voltage to compensate the undesired interface charge (-Qss/Cox)
• Weak inversion is MOSFET operation with the gate-source voltage less than thethreshold voltage
• Layout of the MOSFET is important to its performance and matching capabilities• Extended drain regions lead to higher voltage capability MOSFETs