Pipelined Datapath and Control (Lecture #15) ECE 445 – Computer Organization The slides included herein were taken from the materials accompanying Computer Organization and Design, 4 th Edition, by Patterson and Hennessey, and were used with permission from Morgan Kaufmann Publishers.
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Pipelined Datapath and Control (Lecture #15) ECE 445 – Computer Organization The slides included herein were taken from the materials accompanying Computer.
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Pipelined Datapath and Control
(Lecture #15)
ECE 445 – Computer Organization
The slides included herein were taken from the materials accompanying Computer Organization and Design, 4th Edition, by Patterson and Hennessey,
and were used with permission from Morgan Kaufmann Publishers.
Fall 2010 ECE 445 - Computer Organization 2
Material to be covered ...
Chapter 4: Sections 5 – 9, 13 – 14
Fall 2010 ECE 445 - Computer Organization 3
Hazards
Situations that prevent starting the next instruction in the next cycle
Structure hazards A required resource is busy
Data hazard Need to wait for previous instruction to complete its
data read/write Control hazard
Deciding on control action depends on previous instruction
Fall 2010 ECE 445 - Computer Organization 4
Control Hazards What happens when a branch statement is
encountered?
Branch determines flow of control Fetching next instruction depends on branch
Data Hazards for Branches If a comparison register is a destination of 2nd
or 3rd preceding ALU instruction
…
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
add $4, $5, $6
add $1, $2, $3
beq $1, $4, target
Can resolve using forwarding
Fall 2010 ECE 445 - Computer Organization 14
Data Hazards for Branches If a comparison register is a destination of
preceding ALU instruction or 2nd preceding load instruction Need 1 stall cycle
beq stalled
IF ID EX MEM WB
IF ID EX MEM WB
IF ID
ID EX MEM WB
add $4, $5, $6
lw $1, addr
beq $1, $4, target
Fall 2010 ECE 445 - Computer Organization 15
Data Hazards for Branches If a comparison register is a destination of
immediately preceding load instruction Need 2 stall cycles
beq stalled
IF ID EX MEM WB
IF ID
ID
ID EX MEM WB
beq stalled
lw $1, addr
beq $1, $0, target
Fall 2010 ECE 445 - Computer Organization 16
Dynamic Branch Prediction
In deeper and superscalar pipelines, branch penalty is more significant
Use dynamic prediction Branch prediction buffer (aka. branch history table) Indexed by recent branch instruction addresses Stores outcome (taken/not taken) To execute a branch
Check table, expect the same outcome Start fetching from fall-through or target If wrong, flush pipeline and flip prediction
Fall 2010 ECE 445 - Computer Organization 17
1-Bit Predictor
Use a single bit to indicate whether a branch should be taken or should not be taken.