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68000 Microprocessor
Module 10: Memory Interfacing
Types of memoryIndustry-standard memory pinouts6800068000 asynchronous bus signalsGlue logic design
Memory control signal generatory g gDTACK generatorBus error generator
ROM : Read-Only MemoryNon-volatile (data retained even without power)E i llExists on all computersFunctions on embedded systems: power-on self test, monitor program, application program.Functions on general-purpose computer: power-on self test, basic input/output system (BIOS), monitor program, etc
RAM : Random Access MemoryyVolatile (data disappears without power)Functions on general purpose computer: main memory for running operating system and application programoperating system and application programFunctions on embedded systems: scratch-pad memoryMay not be required on very simple embedded systems
MROM : Mask-programmed read-only memoryProgrammed (contents set) at the factoryL iLow cost per unitHigh NRE (non-recurring engineering) cost
PROM : Programmable ROMgProgrammable once
EPROM : erasable programmable ROMProgrammable & erasable 1000xMust be erased using ultra-violet (UV) light before reprogrammingDevice uses expensive ceramic package & has a quartz window to p p g qallow UV to pass throughUsed for prototyping. When design is sold to customers, cheaper OTPROM is used instead.
EEPROM : Electrically-erasable PROMReprogrammable 1000xC b d l l b b bCan be erased completely or byte-by-byteExpensiveCan be reprogrammed in-system (without removing from circuit board)
Flash memoryElectrically erasable block-by-blockReprogrammable 10 000xReprogrammable 10,000xVery high densityCheapest type of non-volatile memory, used in thumb drives
OTPROM : One-time programmable ROMUses the same “die” as EPROM but uses a plastice package so it cannot be erased
cannot be erasedUsed in embedded systems which will never be reprogrammed
68000 Microprocessor
Types of RAM
SRAM : Static Random Access Memory upside: fast and no refresh required d id d d hdownside: not so dense and not so cheap often used for caches Easy to interface. We’ll use this type.
DRAM : Dynamic Random Access Memory upside: very dense (1 transistor per bit) and inexpensive downside: requires refresh circuit and often not the fastest accessdownside: requires refresh circuit and often not the fastest access times often used for main memories M l O f h f hiMore complex. Out of the scope of this course.
Number of address and data lines on a memory chip is related to how bits are arranged internally
Address bus
13yNumber of locations = 2 ^ address lines
Example: 27C64 chip has 13 lines numbered from A0 through A12
It h 213 23 210 8 kil 8192 l tiA0-A12
It has 213 = 23 x 210 = 8 x kilo = 8192 locationsNumber of bits per location = data lines
Example: 27C64 chip has 8 data lines numbered from D0 through D7
27C648K x 8
EPROMfrom D0 through D7Memory organization is a shorthand notation to describe all the information stated aboveMemory organization is 2 ^ (address lines) x
8 kilo locations x 8 = 8192 x 8 = 65536 bits total bus
68000 Microprocessor
JEDEC
Joint Electronic Device Engineering CouncilSt d d i t fStandard pinout for many related memoriesInterchangeability of d i f diff tdevices from different vendors
If OE and WE are active at the same time, a write operation be performed
68000 Microprocessor
SRAM Read Timing ParameterstRC (Read cycle time)
shortest time allowed between 2 consecutive readst ( Address access time)tAA ( Address access time)
how long it takes to get stable output after a change in addresstCE (Chip select to output)
how long it takes to get valid data after CE is asserted.tOE (output enable time):
how long it takes for valid data to become available on data pins when OE and CS are both asserted.
tOH (output-hold time)length of time data stays valid on data pins after address changeslength of time data stays valid on data pins after address changes
tOZ (output-disable time): how long it takes for the three-state output buffers to enter high-impedance state after OE or CS are negated
Glue LogicList of circuits we need to interface 68000 with memory
Memory control circuitGenerates OE* and WE* signals required by memory chipsGenerates OE and WE signals required by memory chips
Address decoder – covered next chapterGenerate CE* signalsE d l d i t lk t th CPU t tiEnsures one and only one device talks to the CPU at any time
DTACK* GeneratorInforms the 68000 that the current bus cycle is completeOne DTACK* source for every deviceSome 68000 peripherals has built-in DTACK* generator (68681 DUART, 68230 PIT, 68901 MFP etc)
BERR* G t ( ti l)BERR* Generator (optional)Informs the 68000 that there is a problem current bus cycleEnables the 68000 to retry the memory access or shut down the offending program
The basic 68000 asynchronous operation isThe 68000 puts an address on the address bus and asserts Address Strobe (AS*) to signal memory and I/O devices that a valid address isStrobe (AS*) to signal memory and I/O devices that a valid address is available on the busThe memory or I/O device asserts Data Transfer Acknowledge (DTACK*) to signal the 68000 that(DTACK*) to signal the 68000 that
Valid data is available on the data bus during a read operation (the 68000 latches data when DTACK* is asserted)Data has been successfully written to the memory or I/O deviceData has been successfully written to the memory or I/O device
Asynchronous operation allows the 68000 to interface with slow memory or I/O memory devicesA 68000 memory access takes a minimum of eight clock states numbered from clock states S0 to S7
When reading a byte, 68k will read only the correct byte, and ignore the other byte. Refer to Slide 10-14.
68000 Microprocessor
6264 ConnectionsConnect all low address lines directly to memory chip the rest to address decoderConnect all low address lines directly to memory chip, the rest to address decoderConnect lower address bus to Odd Memory, upper address to Even memory
Wait StatesDepending on the speed of your processor, the access times of your memory and peripheral chips, it may be necessary to add a few clock cycles into the 68000’s bus cycle. cyc es o e 68000 s bus cyc eThe extra cycles are called wait statesThis gives slower devices time to respond. Wait states are used only for the slow devices; fast devices still run at full speedthe slow devices; fast devices still run at full speed.For 68000, DTACK* input high causes the processor to wait. To insert a wait state for a given device…
d t d t t t th t d iwe need to detect an access to that device…and hold DTACK* inactive for the required additional clock cycles.
In other words, use the chip select for a given device to delay DTACK* i lgoing low.
Today fast memory is cheap, so knowing how generate DTACK delay is
p g gIf DTACK* is high when sampled, 68k will keep inserting wait states
68000 Microprocessor
Relation of DTACK* with tac
Access time is from address ready (latest by rising edge of S2) and data ready (sampled by 68k on falling edge of S6)Effectively, 68k gives memory 2.5 clock cycles to prepare requested dataFor 68k operating at 10 MHz, this is equiv. 100 ns x 2.5 = 250 ns.