MULTI-CORE MICROPROCESSOR INTERFACE (PROPELLER) Final Scope of the Project Presented to The Faculty of Department of General Engineering San Jose State University In Partial Fulfillment Of the Requirements for the Degree Master of Science in Engineering by Byron Ogada Krunal Patel Sanket Shah (Group 8) December 11, 2009 i
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APPENDIX A .................................................................................................................................... 53
APPENDIX B ..................................................................................................................................... 54
APPENDIX C ..................................................................................................................................... 55
APPENDIX D ..................................................................................................................................... 71
APPENDIX E ..................................................................................................................................... 73
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List of Figure Figure 1: Example of Multi-core Processing…………………………………………….. 2 Figure 2: Schematic of Propeller Circuit………………………………………………… 4 Figure 3: Block Diagram of the Microprocessor……………………………………….. 10 Figure 4: Block Diagram of the Central Hub…………………………………………… 11 Figure 5: Main Memory Structure……………………………………………………… 14 Figure 6: Cog Memory Structure……………………………………………………….. 15 Figure 7: Flow Chart of Propeller Design in Verilog…………………………………... 19 Figure 8: Block Diagram of Single Cog………………………………………………... 20 Figure 9: Block Diagram of Single Block (Shift Right)………………………………... 22 Figure 10: Comparison Chart of Micro-component Market……………………………. 28 Figure 11: Comparison Chart of Micro Component Market in Percentage…………….. 28 Figure 12: Percentages of Processor Revenue………………………………………….. 29 Figure 13: Competitive Embedded Controller Market in Year 2008…………………... 30 Figure 14: Comparative Salaries……………………………………………………….. 33 Figure 15: Estimation of Variable Cost……………………………………………….... 34 Figure 16: Breakeven Analysis………………………………………………………..... 37 Figure 17: Funding Profile over Time………………………………………………….. 37 Figure 18: Cumulative Funding over Time…………………………………………….. 40 Figure 19: Returns on Investment (%)………………………………………………….. 40 Figure 20: Yearly Distribution of Profit/Loss…………………………………………... 41 Figure 21: Profit/Loss for Q3’09 to Q2’10……………………………………………... 42 Figure 22: Profit/Loss for Q3’10 to Q2’11……………………………………………... 43 Figure 23: Profit/Loss for Q3’11 to Q2’12……………………………………………... 44 Figure 24: Profit/Loss for Q3’12 to Q2’13……………………………………………... 45 Figure 25: Quarterly Breakeven Analysis………………………………………………. 45 Figure 26: Project Schedule for ENGR 298……………………………………………. 47
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List of Table Table 1: Clock Register Pin Structure………………………………………………….. 13 Table 2: Pin Description of Propeller Architecture…………………………………….. 16 Table 3: Fixed Costs……………………………………………………………………. 32 Table 4: Employment Wages………………………………………………………….... 33 Table 5: Variable Costs……………………………………………………………….… 34 Table 6: SWOT Assessment………………………………………………………….… 36 Table 7: Department Allocation………………………………………………………… 38 Table 8: Business and Revenue Model……………………………………………….… 39 Table 9: Business Revenue Model for Q3’09 to Q2’10………………………………... 41 Table 10: Business Revenue Model for Q3’10 to Q2’11………………………………. 42 Table 11: Business Revenue Model for Q3’11 to Q2’12………………………………. 43 Table 12: Business Revenue Model for Q3’12 to Q2’13………………………………. 44
1.0 Objective: Increasing popularity of embedded products has given rise to demand for systems with
real time output. Hence the objective is to analyze the Propeller chip and design the
architecture for a multi-core microprocessor interface. This task will be accomplished
using Verilog EDA tool. The goal is to increase the latency of the embedded micro-
processor.
2.0 Introduction: As humanity evolves automation control is rapidly becoming the norm in daily human
life. This means that a majority of devices we interact with are controlled by some form
of computer. Aircrafts, cars, cell phones, modern refrigerators, automated doors, vacuum
cleaners, and medical devices are examples of products that have embedded
microprocessors. This means that the average individual utilizes/interacts with an
embedded system more than they realize.
As the use of embedded systems processors grow, their computing tasks become
more intensive and thus a need for improved processors arises. Multi-core processors
combine two or more microprocessor cores in order to crunch instructions in parallel
resulting in improved latency. Alternative methods for increasing performance of
processors have become necessary. This is because the old ways of increasing clock
cycle and making smaller transistors are approaching a roadblock as Moore’s law is set to
The company has decided to reach customers by hiring a proven marketing team.
The importance of the sales and marketing group is about to be same as that of
ent and engineering. Table 4 presents the comparative employment wages up to
7.12 Business and Revenue Model: BSK Incorporated Design Comp y is a uniq company i this segment by providing a
breakthrough eight core process design. Th ompany’s rketing team has developed
o sell the IP designs and c arge ~$1.29 r every ch sold.
achieving this goal. This team plans to use advertisement in technical news papers,
managem
five years.
an ue n
or e c ma
a plan t h fo ip
The company has intends to sell about 1 million IP designs by 2012 which is
~0.20% (fraction of 1%) market share. The marketing and sales teams are committed to
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technical social networking sites/forums, magazines, and representation in technical
conferences. Table 8 illustrates projected business and revenue model of the company for
five years.
able 8
Business and Revenue Model
T
2009 2010 2011 2012 2013 Price per IP Unit $1.299 $1.299 $1.299 $1.299 $1.299 # of Units Sold 0 200000 600000 1200000 1800000 IP Revenue 0 $259800 $779400 $1558800 $2338200 Total Expenses $446500 $501752 $895884 $1276428 $1740500
7.13 Strategic Alliance/Partners:
In order to position the company on firm ground, BSK Inc. reached out to Parallax and
offer to redes
ign their other architectures using Verilog. BSK, Inc. requested to have
riety source codes for these architectures. In exchange BSK will get ~30% of
edesigned chips are sold (30% of $1.29≈0.38).
The benefit for Parallax is they will be able to reach custom at they ad
ecaus ols. They will als des e
o hire s. The benefit for BSK will
e gaining access to Parallax customers and designs since they are already an established
million
their prop
the royalty amount when these r
ers th never h
access to before b e of their choice of to o get there ign remad
without having t new ngineers or investing in new tool e
b
company.
7.14 Profit & Loss:
Estimated expenses and sales are evaluated in the profit and loss statement. The
company’s expenses are calculated in cost the summary statement and they include fixed
costs and predicted variable costs. The company will spend approximately $1.5
39
dollars before generating any profit. Norden Rayleigh’s estimation in fig 18 illustrates the
spending profile and hence to keep tracking on financial flow of the company.
Figure 18 Cumulative Funding over Time
Return on Investment (ROI) graph in figure 19 shows profit, loss and expenses of
the company. The formula for Return on investment is:
% ROI = [(Total Income – Total Expense)/Total Expense] x 100
Figure 19 Returns on Investment (%)
40
Figu ncome and
total expenses of the respected year.
re 20 presents the profit/loss for every year by taking the total i
Figure 20 Yearly Distribution of Profit/Loss
The company generates their profit/loss statement each quarter to demonstrate the
financial performance. Table 9 demonstrates the profit/loss for Q3’09 to Q2’10. During
these quarters, this start up company invested the first round of funds from the bank.
Table 9
Business Revenue Model for Q3’09 to Q2’10
Total Expected IP sell for Royalty
Revenue Fixed Variable Total Cost= Profit/Lossfrom Royalty
Quarterly break even analysis up to June 2013 is demonstrated in figure 25.
Figure 25 Quarterly Breakeven Analysis
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7.15 Exit Strategy: The stakeholders at BSK Inc. include three founders and two different venture capital
firms. The stakeholders have decided that in the near future the company will go public
depending on its rate of growth and market conditions. The alternate exit strategy is to
sell the company to a more established rival in the event that they make an offer that BSK
stakeholders cannot refuse.
This being said the soft market brought about by the housing and credit crisis are
slowly improving. BSK, Inc. also foresees a steady growth in revenue and company size
because technology companies have been fairing decently within that past 2 quarters of
2009. The goal is to do a thorough evaluation of the BSK Inc. balance sheet and overall
market conditions in approximately the fourth quarter of 2014. The outcome of this
analysis will determine if the company goes public, gets acquired by another company or
remains privately held.
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8.0 Project Schedule:
The project schedules for final project implementations shown in figure 26.
Figure 26 Project Schedule for ENGR 298
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9.0 Conclusion:
Three SJSU engineering students formed a company called BSK Propeller Inc. and set to
design an eight-core embedded process using standardized electronic design tools. After
researching, reading, writing and testing code, debugging designs, and asking and
receiving help, this company has finished designing an eight-core processor. Using
Verilog to design an eight core was made easier by the fact that there were an abundance
of materials and instructions on how to design using Verilog. This is because it is a
standard tool. With the verification of a working design, the company is ready to start
marketing its first design. According to break even analysis, BSK Propeller Inc. should
start being profitable from the first quarter of year 2012. Given the success of the design,
the company anticipates that propeller multi-core controller designed using Verilog will
be successful in the market.
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10.0 Future Work: Future designs include a processor modified with 16 cogs that will perform tasks up to
four times faster than our current design. This job is more complicated and time
consuming than the present design. This future design will run each cog at 160 MIPS
(Million Instructions per Second) and increase clock speed up to 160 MHz.
The present architecture is designed using a four stage pipeline concept. If
successful, this design with full pipelining capability will quadruple the propeller speed.
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11.0 References: Abu A., I. M. (2004). Evalution of Application Specific Multiprocessor Mobile System. Florida: Department of Computer science and Engineering, Florida Atlantic University. Advanced Micro Devices. (2005). MULTI-CORE PROCESSORS—THE NEXT EVOLUTION IN COMPUTING. Retrieved October 2, 2009, from AMD: http://multicore.amd.com/Resources/33211A_Multi-Core_WP_en.pdf Benoliel, I. (2002, May 27). How to Calculate Your Breakeven Point . Retrieved October
15, 2009, from Entreprenur: http://www.entrepreneur.com/money/moneymanagement/financialmanagementcolumnistpamnewman/article52102.html
Centrell, T. (2006). Mind Mannered Propeller Processor. 80-84. Clarke, P. (2008, March 3). Actual data show January chip sales fell on annual basis.
Retrieved November 15, 2009, from EE Times: http://www.eetimes.com/showArticle.jhtml?articleID=206901795
Davey, M. (2008, March 3). Parallax Propeller Chip Overview. Retrieved October 25, 2009, from Chibots: http://www.chibots.org/?q=node/463 Electronic News. (2008, December 8). Multi-core MPU market to skyrocket, iSuppli says.
Retrieved November 16, 2009, from Electronicsweekly: http://www.electronicsweekly.com/Articles/2005/12/08/37147/Multi-core-MPU-market-to-skyrocket-iSuppli-says.htm
Electronics.ca Research Network. (2009, March 29). Embedded Processors Top 10
Billion Units in 2008. Retrieved November 28, 2009, from Electronics.cs publications: http://www.electronics.ca/presscenter/articles/1078/1/Embedded-Processors-Top-10-Billion-Units-in-2008/Page1.html
Fiveash, K. (2008, February 26). EU throws €5.5bn at embedded chips and nanotech.
Retrieved November 15, 2009, from The register: http://www.theregister.co.uk/2008/02/26/eu_joint_technology_initiatives/
Gaudin, S. (2008, November 19). Analysts Predict Global Drop in 2008 Chip Sales.
Retrieved October 25, 2009, from PCWorld: http://www.pcworld.com/businesscenter/article/154186/analysts_predict_global_drop_in_2008_chip_sales.html
Harrison, D. M. (2005, Faburary 19). Microprocessor Interfacing Techniques. Retrieved
October 15, 2009, from UPSCALE: http://www.upscale.utoronto.ca/ Holland, C. (2008, October 14). Market for MCUs, eMPUs and DSPs to reach $8.6B .
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Retrieved October 28, 2009, from EE India Times: http://www.eetindia.co.in/ART_8800547831_1800001_NT_48e47d8a.HTM
Inc., P. (2008). Propeller Information. Retrieved August 24, 2009, from Parallax:
http://www.parallax.com/tabid/407/Default.aspx Intel. (2009). Intel® System Controller Hub US15W. Retrieved September 26, 2009, from
Intel: http://download.intel.com/design/chipsets/embedded/prodbrf/319545.pdf Ledger, J. (2007). The Propeller cook book (Vol. 1.4). Propeller Protoboard
Experimenter Designs. Merritt, R. (2009, March 20). Multicore CPUs face slow road in comms. Retrieved
October 31, 2009, from EETimes: http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=215901460
Merritt, R. (2009, March 17). Tool puts parallelism in embedded code. Retrieved October
31, 2009, from EETimes: http://www.eetimes.com/showArticle.jhtml;jsessionid=P05OCMTDWOICEQSNDLOSKH0CJUNN2JVN;?articleID=215900594
Microcomponents shows mixed market conditions . (2007, August 29). Retrieved
November 15, 2009, from EE Times India: http://www.eetindia.co.in/ART_8800477607_1800001_NT_7ee5e201.HTM
Niccolai, J. (2008, December 16). Chipmakers face longest decline in history, Gartner
says. Retrieved November 3, 2009, from InfoWorld: http://www.infoworld.com/t/hardware/chipmakers-face-longest-decline-in-history-gartner-says-664
Nollet, R. T. (n.d.). The new Propeller Chip from Parallax. Retrieved November 2, 2009
, from R. T. Nollat Austrilia: http://www.nollet.com.au/propeller.htm Palnitkar, S. (1996). Verilog HDL: A guide to Digital Design and Synthesis. SunSoft
Press. Parallax Propeller. (2006, July 7). Retrieved August 24, 2009, from Parallax:
reg [3:0] condition; reg [8:0] sourceadd,destadd,source1,dvalue2,dvalue3; reg [4:0] source; reg [22:0] dvalue1,dvalue4; reg [31:0] data [0:511]; wire [1:0] count; wire [8:0] Rsource,jmpaddress,addaddress,muxnzaddress,muxzaddress,muxncaddress,muxcaddress,roladdress,roraddress,minaddress,maxaddress,maxsaddress,ORaddress,EXORaddress,testaddress,testnaddress,shraddress,shladdress,saraddress,revaddress,movsaddress,movdaddress,moviaddress,minsaddress,rcraddress,rcladdress; wire Zjmp,Zadd,Padd,Zmins,Gmins,Zmaxs,Gmaxs,Zmin,Gmin,Zmax,Gmax,Ztest,Ptest,Ztestn,Ptestn,ZOR,POR,ZEXOR,Pmuxz,Zmuxz,PEXOR,Pmuxc,Zmuxc,Pmuxnc,Zmuxnc,Pmuxnz,Zmuxnz; wire [31:0] Rdest,Rjmp,Radd,Rmuxnz,Rmuxnc,Rror,Rrol,Rshr,Rshl,Rsar,Rrev,Rmovs,Rmovd,Rmovi,Rmins,Rrcr,Rrcl,Rmaxs,Rmin,Rmax,Rtest,Rmuxz,Rtestn,Ror,Rexor,Rmuxc; initial begin $readmemh ("in_file.txt",data); end initial begin PC = 9'h000; C_flag = 1'b0; Z_flag = 1'b0; v = 1'b1; end //RAM r0 (data_out,dataout,clock,we,I_in,re,raddress); counter0 c0 (count,clock,reset); // FETCH THE INSTRUCTION IN R1 always @ (posedge clock)begin if (count == 2'b11)begin IR= data[PC]; if (v == 1'b1)begin PC = PC +1; end end
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end // DECODE THE INSTRUCTION IN R1 always @ (posedge clock)begin if (count == 2'b00)begin operation = IR [31:26]; condition = IR [21:18]; sourceadd = IR [8:0]; destadd = IR [17:9]; c = IR [24]; z = IR [25]; r = IR [23]; i = IR [22]; end end // SET THE CONTROL BITS TO FETCH THE DESTINATION VALUE always @ (posedge clock)begin if (count == 2'b10)begin dbit = 1'b0; end else if (count == 2'b00)begin dbit = 1'b1; end end // FETCH THE DESTINATION VALUE AND STORE IN THE REGISTER always @ (posedge clock)begin if (count ==2'b01)begin if (dbit == 1'b1)begin dvalue = data[destadd]; dvalue1 = dvalue [31:9]; dvalue2 = dvalue [31:23]; dvalue3 = dvalue [8:0]; dvalue4 = dvalue [22:0]; end end end // SET THE CONTROL BIT TO FETCH THE SOURCE VALUE always @ (posedge clock)begin if (count == 2'b01)begin sbit=1'b1; end else if (count == 2'b11)begin
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sbit = 1'b0; end end // FETCH THE SOURCE VALUE AND STORE IN THE REGISTER always @ (posedge clock)begin if (count ==2'b10)begin if (sbit == 1'b1)begin case (operation) 6'b001000:begin //ROR svalue = data [sourceadd]; source = i == 1'b1 ? sourceadd [4:0] : svalue [4:0]; end 6'b001001:begin //ROL svalue = data [sourceadd]; source = i == 1'b1 ? sourceadd [4:0] : svalue [4:0]; end 6'b001010:begin //SHR svalue = data [sourceadd]; source = i == 1'b1 ? sourceadd [4:0] : svalue [4:0]; end 6'b001011:begin //SHL svalue = data [sourceadd]; source = i == 1'b1 ? sourceadd [4:0] : svalue [4:0]; end 6'b001110:begin //SAR svalue = data [sourceadd]; source = i == 1'b1 ? sourceadd [4:0] : svalue [4:0]; end 6'b001111:begin // REV svalue = data [sourceadd]; source = i == 1'b1 ? sourceadd [4:0] : svalue [4:0]; end 6'b001100:begin //RCR svalue = data [sourceadd]; source = i == 1'b1 ? sourceadd [4:0] : svalue [4:0]; end 6'b001101:begin //RCL svalue = data [sourceadd]; source = i == 1'b1 ? sourceadd [4:0] : svalue [4:0]; end 6'b010100:begin //MOVS svalue = data [sourceadd]; source1 = i == 1'b1 ? sourceadd : svalue [8:0]; end 6'b010101:begin //MOVD
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svalue = data [sourceadd]; source1 = i == 1'b1 ? sourceadd : svalue [8:0]; end 6'b010110:begin //MOVI svalue = data [sourceadd]; source1 = i == 1'b1 ? sourceadd : svalue [8:0]; end 6'b010000:svalue = i == 1'b1 ? sourceadd : data [sourceadd]; // MINS 6'b010001:svalue = i == 1'b1 ? sourceadd : data [sourceadd]; // MAXS 6'b010010:svalue = i == 1'b1 ? sourceadd : data [sourceadd]; //MIN 6'b010011:svalue = i == 1'b1 ? sourceadd : data [sourceadd]; //MAX 6'b011000:svalue = i == 1'b1 ? sourceadd : data [sourceadd]; //TEST 6'b011001:svalue = i == 1'b1 ? sourceadd : data [sourceadd]; //TESTN 6'b011010:svalue = i == 1'b1 ? sourceadd : data [sourceadd]; //OR 6'b011011:svalue = i == 1'b1 ? sourceadd : data [sourceadd]; //EXOR 6'b011100:svalue = i == 1'b1 ? sourceadd : data [sourceadd]; //MUXC 6'b011101:svalue = i == 1'b1 ? sourceadd : data [sourceadd]; //MUXNC 6'b011110:svalue = i == 1'b1 ? sourceadd : data [sourceadd]; //MUXZ 6'b011111:svalue = i == 1'b1 ? sourceadd : data [sourceadd]; //MUXNZ 6'b100000:svalue = i == 1'b1 ? sourceadd : data [sourceadd]; //ADD 6'b010111:begin svalue = data [sourceadd]; //JUMP source1 = i == 1'b1 ? sourceadd : svalue [8:0]; PC = source1; end endcase /*if (i == 1'b1)begin svalue = data[sourceadd]; source1 = sourceadd; source = sourceadd[4:0]; end else begin svalue = data[sourceadd]; source = svalue[4:0]; source1 = svalue[8:0]; end*/ end end end //SET THE EXECUTION BIT ACCORDING THE OPERATION TO BE PERFORMED always @ (posedge clock)begin if (count == 2'b10)begin v = operation == 6'b010111 ? 1'b0 : v; end end
6'b011000:extest=1'b0; 6'b011001:extestn=1'b0; 6'b011010:exOR=1'b0; 6'b011011:exEXOR=1'b0; 6'b011100:exmuxc=1'b0; 6'b011101:exmuxnc=1'b0; 6'b011110:exmuxz=1'b0; 6'b011111:exmuxnz=1'b0; 6'b100000:exadd=1'b0; 6'b010111:exjmp=1'b0; endcase end end // PERFORM THE OPERATION ror r0 (clock,exror,Rror,dvalue,source,condition,roraddress,destadd,c,z); rol r2 (clock,exrol,Rrol,dvalue,source,condition,roladdress,destadd,c,z); shr sh1 (clock,exshr,Rshr,dvalue,source,condition,shraddress,destadd,c,z); shl sh2 (clock,exshl,Rshl,dvalue,source,condition,shladdress,destadd,c,z); sar asr (clock,exsar,Rsar,dvalue,source,condition,saraddress,destadd,c,z); rev rv1 (clock,exrev,Rrev,dvalue,source,condition,revaddress,destadd,c,z); movs mv1 (clock,exmovs,Rmovs,dvalue1,source1,condition,movsaddress,destadd,c,z); movd mv2 (clock,exmovd,Rmovd,dvalue2,dvalue3,source1,condition,movdaddress,destadd,c,z); movi mv3 (clock,exmovi,Rmovi,dvalue4,source1,condition,moviaddress,destadd,c,z); rcr rc1 (clock,exrcr,Rrcr,dvalue,source,condition,rcraddress,destadd,c,z,C_flag); rcl rc2 (clock,exrcl,Rrcl,dvalue,source,condition,rcladdress,destadd,c,z,C_flag); mins min1 (clock,exmins,Rmins,dvalue,svalue,condition,minsaddress,destadd,c,z,Zmins,Gmins); maxs max1 (clock,exmaxs,Rmaxs,dvalue,svalue,condition,maxsaddress,destadd,c,z,Zmaxs,Gmaxs); min min2 (clock,exmin,Rmin,dvalue,svalue,condition,minaddress,destadd,c,z,Zmin,Gmin); max max2 (clock,exmax,Rmax,dvalue,svalue,condition,maxaddress,destadd,c,z,Zmax,Gmax); test t1 (clock,extest,Rtest,dvalue,svalue,condition,testaddress,destadd,c,z,Ztest,Ptest); testn t2 (clock,extestn,Rtestn,dvalue,svalue,condition,testnaddress,destadd,c,z,Ztestn,Ptestn); OR or1 (clock,exOR,Ror,dvalue,svalue,condition,ORaddress,destadd,c,z,ZOR,POR); EXOR exor1 (clock,exEXOR,Rexor,dvalue,svalue,condition,EXORaddress,destadd,c,z,ZEXOR,PEXOR); muxc mux1(clock,exmuxc,Rmuxc,dvalue,svalue,condition,muxcaddress,destadd,c,z,C_flag,Zmuxc,Pmuxc);
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muxnc mux2 (clock,exmuxnc,Rmuxnc,dvalue,svalue,condition,muxncaddress,destadd,c,z,C_flag,Zmuxnc,Pmuxnc); muxz mux3 (clock,exmuxz,Rmuxz,dvalue,svalue,condition,muxzaddress,destadd,c,z,Z_flag,Zmuxz,Pmuxz); muxnz mux4 (clock,exmuxnz,Rmuxnz,dvalue,svalue,condition,muxnzaddress,destadd,c,z,Z_flag,Zmuxnz,Pmuxnz); add add1 (clock,exadd,Radd,dvalue,svalue,condition,addaddress,destadd,c,z,Zadd,Cadd); jmp jmp1(clock,exjmp,Rsource,Rdest,source1,dvalue1,condition,jmpaddress,destadd,c,z,Zjmp); // WRITE BACK THE RESULT IN MEMORY // SET THE WRITE BACK CONTROL BIT AS PER THE OPERATION always @ (posedge clock)begin if (count == 2'b11)begin case (operation) 6'b001000:wbror=1'b1; 6'b001001:wbrol=1'b1; 6'b001010:wbshr=1'b1; 6'b001011:wbshl=1'b1; 6'b001110:wbsar=1'b1; 6'b001111:wbrev=1'b1; 6'b010100:wbmovs=1'b1; 6'b010101:wbmovd=1'b1; 6'b010110:wbmovi=1'b1; 6'b010000:wbmins=1'b1; 6'b001100:wbrcr=1'b1; 6'b001101:wbrcl=1'b1; 6'b010001:wbmaxs=1'b1; 6'b010010:wbmin=1'b1; 6'b010011:wbmax=1'b1; 6'b011000:wbtest=1'b1; 6'b011001:wbtestn=1'b1; 6'b011010:wbOR=1'b1; 6'b011011:wbEXOR=1'b1; 6'b011100:wbmuxc=1'b1; 6'b011101:wbmuxnc=1'b1; 6'b011110:wbmuxz=1'b1; 6'b011111:wbmuxnz=1'b1; 6'b100000:wbadd=1'b1; 6'b010111:wbjmp=1'b1; endcase end else if (count == 2'b01)begin
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case (op) 6'b001000:wbror=1'b0; 6'b001001:wbrol=1'b0; 6'b001010:wbshr=1'b0; 6'b001011:wbshl=1'b0; 6'b001110:wbsar=1'b0; 6'b001111:wbrev=1'b0; 6'b010100:wbmovs=1'b0; 6'b010101:wbmovd=1'b0; 6'b010110:wbmovi=1'b0; 6'b010000:wbmins=1'b0; 6'b001100:wbrcr=1'b0; 6'b001101:wbrcl=1'b0; 6'b010001:wbmaxs=1'b0; 6'b010010:wbmin=1'b0; 6'b010011:wbmax=1'b0; 6'b011000:wbtest=1'b0; 6'b011001:wbtestn=1'b0; 6'b011010:wbOR=1'b0; 6'b011011:wbEXOR=1'b0; 6'b011100:wbmuxc=1'b0; 6'b011101:wbmuxnc=1'b0; 6'b011110:wbmuxz=1'b0; 6'b011111:wbmuxnz=1'b0; 6'b100000:wbadd=1'b0; 6'b010111:wbjmp=1'b0; endcase end end // FLIP FLOP THE OPCODE AND RESULT BIT TO USE INTO THE WRITE BACK STAGE always @ (posedge clock)begin if (count==2'b11)begin op=operation; result=r; z1=z; c1=c; end end // WRITE THE RESULT IN MEMORY always @ (posedge clock)begin if (count==2'b00)begin if (wbror==1'b1)begin
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if (op==6'b001000)begin if (result==1'b1)begin I_out = Rror; R3 = Rror; data [roraddress] = Rror; end end end else if (wbrol==1'b1)begin if (op==6'b001001)begin if (result==1'b1)begin I_out = Rrol; R3 = Rrol; data [roladdress] = Rrol; end end end else if (wbshr==1'b1)begin if (op==6'b001010)begin if (result==1'b1)begin I_out = Rshr; R3 = Rshr; data [shraddress] = R3; end end end else if (wbshl==1'b1)begin if (op==6'b001011)begin if (result==1'b1)begin I_out = Rshl; R3 = Rshl; data [shladdress] = Rshl; end end end else if (wbsar==1'b1)begin if (op==6'b001110)begin if (result==1'b1)begin I_out = Rsar; R3 = Rsar; data [saraddress] = R3; end end end else if (wbrev==1'b1)begin if (op==6'b001111)begin if (result==1'b1)begin I_out = Rrev;
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R3 = Rrev; data [revaddress] = R3; end end end else if (wbmovs==1'b1)begin if (op==6'b010100)begin if (result==1'b1)begin data [movsaddress] = Rmovs; I_out = Rmovs; R3 = Rmovs; end end end else if (wbmovd==1'b1)begin if (op==6'b010101)begin if (result==1'b1)begin data [movdaddress] = Rmovd; I_out = Rmovd; R3 = Rmovd; end end end else if (wbmovi==1'b1)begin if (op==6'b010110)begin if (result==1'b1)begin data [moviaddress] = Rmovi; I_out = Rmovi; R3 = Rmovi; end end end else if (wbrcr==1'b1)begin if (op==6'b001100)begin if (result==1'b1)begin data [rcraddress] = Rrcr; I_out = Rrcr; R3 = Rrcr; end end end else if (wbrcl==1'b1)begin if (op==6'b001101)begin if (result==1'b1)begin data [rcladdress] = Rrcl; I_out = Rrcl; R3 = Rrcl; end
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end end else if (wbmins==1'b1)begin if (op==6'b010000)begin if (result==1'b1)begin data [minsaddress] = Rmins; I_out = Rmins; R3 = Rmins; end end end else if (wbmaxs==1'b1)begin if (op==6'b010001)begin if (result==1'b1)begin data [maxsaddress] = Rmaxs; I_out = Rmaxs; R3 = Rmaxs; end end end else if (wbmin==1'b1)begin if (op==6'b010010)begin if (result==1'b1)begin data [minaddress] = Rmin; I_out = Rmin; R3 = Rmin; end end end else if (wbmax==1'b1)begin if (op==6'b010011)begin if (result==1'b1)begin data [maxaddress] = Rmax; I_out = Rmax; R3 = Rmax; end end end else if (wbtest==1'b1)begin if (op==6'b011000)begin if (result == 1'b1)begin data [testaddress] = Rtest; I_out = Rtest; R3 = Rtest; end else begin I_out = Rtest; R3 = Rtest;
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end end end else if (wbtestn==1'b1)begin if (op==6'b011001)begin if (result == 1'b1)begin data[testnaddress] = Rtestn; I_out = Rtestn; R3 = Rtestn; end else begin I_out = Rtestn; R3 = Rtestn; end end end else if (wbOR==1'b1)begin if (op==6'b011010)begin if (result == 1'b1)begin data[ORaddress] = Ror; I_out = Ror; R3 = Ror; end end end else if (wbEXOR==1'b1)begin if (op==6'b011011)begin if (result == 1'b1)begin data[EXORaddress] = Rexor; I_out = Rexor; R3 = Rexor; end end end else if (wbmuxc==1'b1)begin if (op==6'b011100)begin if (result == 1'b1)begin data[muxcaddress] = Rmuxc; I_out = Rmuxc; R3 = Rmuxc; end end end else if (wbmuxnc==1'b1)begin if (op==6'b011101)begin if (result == 1'b1)begin data[muxncaddress] = Rmuxnc; I_out = Rmuxnc;
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R3 = Rmuxnc; end end end else if (wbmuxz==1'b1)begin if (op==6'b011110)begin if (result == 1'b1)begin data[muxzaddress] = Rmuxz; I_out = Rmuxz; R3 = Rmuxz; end end end else if (wbmuxnz==1'b1)begin if (op==6'b011111)begin if (result == 1'b1)begin data[muxnzaddress] = Rmuxnz; I_out = Rmuxnz; R3 = Rmuxnz; end end end else if (wbadd==1'b1)begin if (op==6'b100000)begin if (result == 1'b1)begin data[addaddress] = Radd; I_out = Radd; R3 = Radd; end end end else if (wbjmp==1'b1)begin if (op==6'b010111)begin if (result == 1'b1)begin PC = Rsource; data [jmpaddress] = Rdest; I_out = Rdest; R3 = Rdest; v = 1'b1; end else begin PC = Rsource; v = 1'b1; end end end end end