DSPs for Energy Harvesting Sensors - ECEramirtha/promotion/amirtharajahA20.pdfDSPs for Energy Harvesting Sensors: Applications and Architectures O ... a MEMS variable-capacitor transducer

72 PERVASIVEcomputing Published by the IEEE CS and IEEE ComSoc ■ 1536-1268/05/$20.00 © 2005 IEEE

E N E R G Y H A R V E S T I N G & C O N S E R V A T I O N

DSPs for EnergyHarvesting Sensors:Applications and Architectures

Over the past decade, embeddeddigital electronics have prolifer-ated in both number and variety.Applications such as cellularphones, portable multimedia de-

vices, and sensor networks have kept pace withdramatic increases in comput-ing power and functionality.Battery technology, however,has not. Batteries limit the oper-ating lifetime of portable devicesand add undesirable weight andvolume. They can’t store suffi-cient energy to support long-lifetime embedded applicationssuch as monitoring civil infra-structure or studying the envi-ronment. Their replacementcost poses a major barrier to

scaling wireless sensor networks to hundreds orthousands of nodes.

Energy harvesting from human or environ-mental sources is a promising alternative toaddress these limitations and open new frontiersfor integrating digital computation with sensingand actuation. Several alternative energy har-vesting paradigms are possible, as either a sub-stitute or a complement for batteries. The com-mercial sector has adopted mechanical energyharvesting as a redundant power source. Prod-ucts already on the market include radios, flash-

lights, and cell-phone chargers powered by hand-cranked electrical generators or shake-to-rechargeelectronics. But these mechanisms aren’t suitablefor all applications: first, they have low energyand power densities; second, they require activeuser involvement.

Researchers have explored various passiveenergy-harvesting power sources for portable orwearable devices. These include gravity-drivenand vibration-driven electromagnetic generators,piezoelectric shoe inserts, and thermocouples forharvesting energy from human body thermal gra-dients. Passive power sources for sensor net-works, another target area for energy harvest-ing,1 include ambient mechanical vibration. Oneproject, which some of us worked on, developeda MEMS variable-capacitor transducer andaccompanying chips that could harvest machinevibrations for sensor signal processing.2

Despite a promising start, energy harvesting isstill in its infancy. For current sensor networknodes, vibration-based energy harvesting allowsan RF transmit duty cycle of less than 3 percent,excluding any computation that occurs at thetransmitter.1 Communication typically dominatespower consumption, so many applications mustmaximize the computation done at a particularnode.3 Required off-chip power electronics canincrease system cost and volume, and AC/DCconversion losses can limit energy-harvestingoperation.

Energy harvesting from human or environmental sources shows promiseas an alternative to battery power for embedded digital electronics.Digital signal processors that harvest power from ambient mechanicalvibration are particularly promising for sensor networks.

Rajeevan Amirtharajah, Jamie Collier, and Jeff Siebert University of California, Davis

Bicky Zhou Intel

Anantha Chandrakasan Massachusetts Institute of Technology

Much current work addresses theseproblems from the power generation sideby developing and optimizing energyharvesting transducers. However, thedesire for smaller devices and higher inte-gration levels poses constraints that fun-damentally limit output power. Ourwork addresses the issues from the powerconsumption standpoint by developingdigital signal processing (DSP) architec-tures and circuits that are energy efficient,energy scalable, and robust to transduceroutput-voltage variations.

Two applicationsSensor applications are particularly

well suited to energy harvesting becausethey typically require low throughputs.We explored two such applications forenergy harvesting: computing a fastFourier transform (FFT) to monitor ashipboard gas turbine’s vibrations andusing data from a wearable acoustic bio-medical sensor to analyze a user’s exer-tion state.

Monitoring gas turbine vibrationLarge machinery generates vibrations

during operation. These vibrations offera possible energy source, but the vibra-tion signature can also indicate changesin the machine’s performance or evenimpending failure. The vibration spec-trum supports analysis of sudden shiftsin vibration. An FFT is a computation-ally elegant means of computing thisspectrum.

Each FFT butterfly operation must readfour operands and write back two results.Assuming a flat memory hierarchy (nocaching) and fully serial computation,every operation requires one read-evalu-ate-write cycle. The computation thusrequires a large number of cycles. This is

acceptable, however, because it also hasa low duty cycle, so an application canspread the computation out in time.

This particular application must com-pute one FFT every five minutes. Ofevery 10 FFTs, nine are low-bandwidthcomputations (1.8 kHz) and one is high-bandwidth (18 kHz). Despite the highcycle count, the processor idles with itsclock gated off for significant periodsthanks to the low throughput require-ment. This implies that leakage powerbecomes significant for low-threshold-voltage complementary metal-oxidesemiconductor (CMOS) transistors.Table 1 shows the specifications forboth FFTs, including spectral averaging.

The throughput requirement also setsthe clock rate. Five minutes is a very longtime to perform the computations re-quired, even with the serial approach.

We assume a clock rate for each com-putation equal to the sample rate. Each

FFT has 512 frequency points computedwith 12-bit fixed-point data.

This FFT application is just one exam-ple of computationally intensive signalpreprocessing. Further computation pro-cesses this spectrum into a machine-statediagnosis.

Signal processing for a wearablephysiological monitor

We explored a physiological monitor-ing application that uses a wearablemicrophone as a biomedical sensor todetermine the wearer’s physical condition(exertion state). We estimated that 400µW of power would be available from awearable AA battery-sized electromag-netic generator,4 sufficient for recentlydemonstrated biomedical devices. Figure1 shows the demonstration system.5 Thesystem algorithm first detects heartbeats,then uses them to determine heart rateas the basis for a physiological assess-

JULY–SEPTEMBER 2005 PERVASIVEcomputing 73

TABLE 1FFT specifications for machine vibration monitoring.

Sample FFT size Number of Duty cycle Computation rate (n) n-point FFTs Operations (%)

Low-bandwidth FFT 1.8 kHz 512 13 542,464 2.5

High-bandwidth FFT 18 kHz 512 139 5,800,192 2.7

FFT total 10,682,368 5.2

Figure 1. Wearable biomedical acousticsensor demonstration system.

74 PERVASIVEcomputing www.computer.org/pervasive


ment. We used a similar system to exam-ine the possibility of determining breath-ing rate as a basis for assessment.

Heartbeat detection. The basic algorithmhas three phases. First is preprocessing,which also has three phases:

• Low-pass filtering. The data is band-limited to below 200 Hz to eliminateas much of the voice and breathenergy as possible.

• Matched filtering. The low-pass filter’soutput goes through a matched filterto determine the candidate heartbeatsignals.

• Segmentation. The sensor output isdivided into overlapping segments atleast long enough to contain a fullheartbeat but short enough not to con-tain more than one.

The algorithm’s second phase is fea-ture extraction, which computes a vectorof seven features from the segmented,matched filter output. The features arescalar quantities helpful in recognizingheartbeats—for example, filter outputpeak values.

Finally, the classification phase uses aparametric Gaussian multivariate clas-sifier to classify each feature vector intoa heartbeat or nonheartbeat.

Figure 2 summarizes the algorithm.Assuming that antialiasing band-limitsthe data, the first significant computa-tion is the matched filtering. The matchedfilter impulse response, or filter template,is a denoised version of the acousticheartbeat signature. When convolvedwith the input data, the filter produceslarge correlation peaks at the input heart-beats’ time locations. Figure 2 includesa template and an example correlationpeak.

The segmentation phase localizes theregions of this time series that have cor-relation peaks. The algorithm thenextracts features from these regions,labeled 1, 2, 3, 4, 5, and 7 in the figure,and classifies them. (Feature 6 repre-sents the total energy in the segment, soits label doesn’t appear on the graph.)The preprocessing steps, in particularthe matched filtering, require the mostoperations and consume the most time,as the algorithm specifications in table 2show.

Breath detection. Breath and speechacoustic energy is concentrated in thehigh-frequency (> 200 Hz) portion of thesensor data spectrum. Peaks in the mov-ing average of the energy for narrow-bandpass-filtered versions of the origi-nal signal indicate fairly well whenbreaths are occurring. Peak width indi-cates breath duration. A “popping”noise—indicated by sharp, narrowspikes in the energy time series and prob-ably representing a sensor artifact—con-tributes extra energy in these bands thatmight lead to a misclassification. As withheartbeats, we use a classifier-basedapproach for breath detection.

The algorithm divides the time seriesinto short-duration nonoverlapping seg-ments. Each segment is labeled accord-ing to whether breathing (class 1), “pop-ping” noise or speech (class 3), orbackground noise (class 2) is occurringduring the segment. The extracted fea-tures are basically the signal energy inthree different high-frequency bands,normalized by the energy in the highestband to eliminate misclassification ofbroadband noise. This normalization fac-tor and the total high-frequency energyform the last two candidate features.

These five features are

• normalized energy in the 200 to 600Hz band,

• normalized energy in the 600 Hz to 1kHz band,

• normalized energy in the 1 to 1.4 kHzband,

• normalization factor for energy in the1.4 to 1.8 kHz band, and

• total energy in the 200 Hz to 1.8 kHzband.

The 4 kHz sampling rate sets the upperbound on frequency at 2 kHz, but the sig-nal doesn’t have much energy at the edgeof the antialiasing passband. The featureprobability distributions indicate that

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Figure 2. Heartbeat detection and classification algorithm.

they are basically Gaussian. Therefore,we again use the multivariate Gaussianparametric classifier as the breath detec-tion engine. For simulation purposes, weeliminated the speech and “pop” noiseclasses, since a more sophisticated algo-rithm will probably be needed to handlethese high-energy signals.

The classifier recognition performancefor these candidate features is generallypoor (< 70 percent accurate), particu-larly because the transition times whena breath starts and stops are difficult toclassify accurately solely on the basis ofenergy. However, if we can classify con-secutive breath samples consistently, wecan construct a binary sequence thatdetermines when a breath is occurring.Each breath would consist of several 1sin a row, and each pause in breathing bya string of 0s. Using the 0 to 1 and 1 to0 transitions, we could estimate theduration of the breath and pauses.Counting the pulses of 1s would give agood estimate of the breathing rate. Thiswould constitute a first step toward esti-mating the wearer’s exertion state usingthe breath signals. We could process thisstream of 1-bit samples serially.

Voice stress analysis. Voice stress mightalso be a good indicator of physical exer-tion state. Further research on low-power speech algorithms might show thefeasibility of processing voice stress forlow- to medium-throughput low-powerDSPs. However, this analysis requirescomplex algorithms that we have yet toexplore and might require unreason-ably high performance from the signal-processing engine, given the limitedavailable power.

Implications for architecture Two factors contribute to CMOS

power dissipation P. One is dynamicpower spent in switching capacitancesand the other is static power dissipatedduring constant current flow:

P = �CV2ddf + IstatVdd (1)

where � represents the probability of aparticular node switching, C is the nodecapacitance, Vdd is the supply voltage, fis the clock frequency, and Istat accountsfor static current flowing from the sup-ply to the ground, including analog biascircuits and device leakage.

A second equation

P = Ediss/�t (2)

expresses power as dissipated energyEdiss divided by time �t.

As tables 1 and 2 show, the FFT andheartbeat estimation applications repre-sent two extremes of energy harvestingsensor operation. The FFT applicationrequires a very low duty cycle, so staticpower due to leakage will increase asCMOS technology scales. We candecrease leakage at the cost of increaseddynamic power by employing serialcomputation.

In contrast, the heartbeat detectionalgorithm runs continuously and is dom-inated by preprocessing steps, so a low-power DSP architecture must optimizeits frequent computations.

Sensor DSP architectureBecause of the unknown and time-

varying nature of the power availablefrom energy harvesting, energy scala-bility is a critical feature for energy har-vesting sensor DSPs: they must be able totrade energy dissipation for some qual-ity metric of DSP output. Energy-scalablehardware includes techniques for ap-proximate processing, which treatspower and arithmetic precision as systemparameters that can trade off each other.

We implemented an energy-scalableserial computation technique as part ofa DSP chip. We called the chip Sensor-DSP and measured its performance forheartbeat detection.

Bit-serial computation and distributed arithmetic

Leakage currents are expected to con-tribute an ever larger percentage of totalpower as CMOS technologies scale.6 Wecan address this by using serial arithmetictechniques. Older CMOS processes usedbit-serial techniques to reduce the area oflarge arithmetic structures such as multi-pliers. These techniques use registers todecrease the amount of combinationallogic needed to perform a computation.To maintain a fixed throughput, we mustclock a bit-serial implementation at Ntimes the specified frequency, where N isthe data bitwidth. This increases thedynamic power consumption (equation1). However, the serial implementation’sreduced area and transistor count alsodecrease the static power consumptiondue to leakage currents.

Figure 3 shows the estimated totalpower dissipation for serial and parallelmultipliers as frequency and technologyscale. At high throughputs, the serialimplementation’s dynamic power dom-inates the total power because of higherrequired clock frequencies. At lowthroughputs, the implementation’s lowstatic power consumption presents a sig-nificant advantage. So, it can be seen thatbelow a certain throughput thresholdserial computations have lower totalpower, and this threshold increases astechnology scales due to increased leak-age currents in deep-submicron CMOS.At 130 nanometers, the throughput


TABLE 2Heartbeat detection algorithm specifications.

Computation Sample rate Clock rate Operations Duty cycle (%)

Heartbeat 160 Hz 1.2 kHz 18,170,000 99.8preprocessing

Feature extraction Variable 250 kHz 110,000 0.2 and classification

Heartbeat total 18,280,000 100.0

threshold is just below 100 kHz, aboutfour times faster than the maximumthroughput requirement for the FFTapplication. At 18 kHz, a 130-nm serialmultiplier implementation for the FFTwill have three times less power than atraditional array multiplier.

Serial computation is also an elegantapproximate-processing technique. Byreducing the number of bits shifted induring the computation (truncating theinput data), the dynamic power de-creases linearly with the input bitwidth.The resulting increased truncation erroralso increases the quantization noisethat degrades the computation’s output.Distributed arithmetic, a method ofcomputing vector dot products (equiv-alent to finite-length impulse responsefilters) without multipliers, offers anenergy-efficient serial DSP hardwareimplementation.7 DA reorders the com-putation by considering a bit slicethrough all input samples rather than

each sample individually. Each bit sliceis an M-bit binary number correspond-ing to a unique linear combination offilter coefficients. The programmer pre-computes all 2M possible combinationsand stores them in a lookup table.

The computation addresses the look-up table with successive bit slices, thenshifts and accumulates the table’s readdata until the DA unit consumes all inputdata bits. By truncating the computationbefore reaching this condition, DA fea-tures successive approximation proper-ties. If a single table implemented a typ-ical filter, the lookup table would growexponentially and would be unrealiz-able. Instead, adders can accumulatemultiple smaller DA units’ outputs intothe final result.

This structure enables another powerperformance trade-off. Enabling variousDA units allows the number of filter tapsto vary independently of the input bit-width. The SensorDSP chip has demon-

strated this trade-off in energy harvestingapplications.8

SensorDSP implementation andresults

We developed the SensorDSP chip todemonstrate low-power and energy-scal-able signal processing for wearable bio-medical sensors. Figure 4 shows the chip’sarchitecture, which follows the algorithmdescribed earlier. We used energy-scalableDA to implement the matched filter. Itsoutput feeds a nonlinear/short linear fil-tering unit, which calculates quantitiesused in segmentation. The microcon-troller performs the segmentation, featureextraction, and classification. The bufferprovides synchronization between thefront-end filtering and back-end process-ing and helps reduce power consumption.The filtering front end must run continu-ously to process input samples, whicharrive at a fixed rate. However, the back-end classification must be performed onlyfor each segment, not each sample.

The system first filters the input andwrites results to the buffer. The micro-controller continuously executes a smallloop, checking to see if the preprocess-ing logic has written a full segment to thebuffer. When the microcontroller detectsa segment, it executes the feature extrac-tion and classification code on thebuffered data.

Cycle-level chip simulations show thatthe algorithm spends 99.8 percent of itstime executing the matched filtering andother preprocessing functions. Thesecomputations dominate both time andpower consumption and are optimizedby the specialized functional units. Mul-tiple clock modes meet performance con-straints by running the front-end filtering



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Serial (130 nm)Serial (100 nm)Serial (70 nm)Parallel (130 nm)Parallel (100 nm)Parallel (70 nm)

Figure 3. Estimated power dissipation for serial and parallel multipliers as technology scales.

Distributedarithmetic

unit

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zmicrocontrollerClassification

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Figure 4. SensorDSP chip architecture.

at 1.2 kHz and back-end processing at250 kHz. Because device leakage is notsignificant at the process node for thischip, we used parallel arithmetic struc-tures in the microcontroller to minimizedynamic power.

Figure 5 shows the power versusheartbeat recognition performancetrade-off from measurements of theSensorDSP chip. As the serial input datato the DA unit scales from 8 to 4 to 2bits, the increased noise degrades recog-nition accuracy from about 96 to 86 per-cent. Power consumption when only theDA and the microcontroller are ondecreases from 176 nanoWatts for 8 bitsto 133 nW for 4 bits and finally to 121nW for 2 bits. When all functional unitsare on, the power decreases from 299nW for 8 bits to 239 nW for 4 bits, andlastly to 229 nW for 2 bits.

The figure shows the change in relativepower as quantization is scaled anddemonstrates that the fixed power ofsome functional units limits the system’stotal energy scalability. The heart rate esti-mation algorithm consumes 560 nW totalpower when running on SensorDSP. Thiscorresponds to 26.6 picoJoules of energydissipated per input data sample. Thesame algorithm running on a StrongARMSA-1100 consumes 11 µJ of energy, aboutsix orders of magnitude more.8

These results demonstrate the dra-matic energy efficiency gains enabled bytargeted DSP architectures.

Next-generation DSPs forenergy harvesting

We are exploring new circuits fornext-generation energy harvesting DSPs.

Some applications require a DC supplyvoltage, while others can use the ACenergy harvester output voltage directly.This eliminates the need for power elec-tronics and boosting the power avail-able for computation. Self-timed circuitsoffer a way to improve performance forhigh-speed pipelined data paths and forlow-power applications because theyeliminate the need for power-hungryclock buffers and clock distribution.Self-timed circuit operation is alsorobust to parameter variations, includ-ing supply voltage. This robustness iswhat makes self-timed circuitry apromising design style for data paths inenergy harvesting applications.

Self-timed circuit designFigure 6 shows a self-timed pipeline

that uses a replica critical path ringoscillator to provide the clock. Theinverter chain represents the clockbuffer.

In the SensorDSP chip, the criticalpath consists of a tree of carry chainsfor summing the DA outputs. To scalethe approach to more complicated datapaths, we can use multiplexors to addmore inverter stages to the oscillator.This design style resembles traditionalsynchronous design in that the worst-case performance of the slowest pipestage dictates the operational fre-quency. However, the ring oscillator


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Figure 5. SensorDSP heartbeat recognitionperformance and power scaling with dataquantization.

Logic Logic

Critical path replica

Power-on pulse generatorEnergy harvester

Oscillator startup

Logic resetFigure 6. Self-timed data path currentlyunder development with power-on resetcircuitry.

frequency varies with supply voltage,temperature, and other variables auto-matically to ensure correct operation.

We’ve demonstrated the data path’srobustness to voltage variation in sim-ulation using a ripple-carry adderpipelined into two stages. The self-timed data path’s performance willdegrade as supply voltage decreases,but it will nevertheless operate cor-rectly. In traditional synchronousdesigns, the designer must eliminateall types of timing violations becausethe clock frequency is fixed; other-wise, variations that exceed thedesigned tolerances will cause the datapath to fail.

The self-timing structure in figure 6includes power-on reset blocks. Becausethe vibration’s frequency will periodi-cally lower a vibration-based power sup-ply’s output to zero, the circuit must han-dle frequent power-up/power-downcycles correctly. Conventional power-onreset circuits use a resistor-capacitor net-work to create the delay period.9 We’recurrently designing a power-on pulsegenerator that does not depend oncapacitance and enables functionalityover a wider frequency range. We’re alsoexploring the use of integrated dynamicRAM for storing data between energyharvester output voltage cycles.

Architectural support for energyvariability

Self-timed operation introduces jitterin input sample processing. For manysensor applications, this jitter will besmall compared to the system’s desiredsample rate, and overall signal process-ing performance will not suffer. Theheartbeat example relies on a samplerate of 160 Hz, which is likely to bemuch slower than variations in self-timed circuit operation. Larger jitterslead to nonuniform sampling andrequire more sophisticated processingto compensate for the timing uncer-tainty.10 This might require more flexi-ble functional units in the DSP, includ-ing energy-efficient implementation ofadaptive filters.

Figure 5 shows that fixed power over-head limits the DSP’s total energy scala-bility. Converting more functional unitsto energy-scalable processing (for exam-ple, bit-serial computation) allows alarger fraction of the DSP power to beadjusted through software. The Sensor-DSP chip relied on special registers toconfigure the input data quantization,number of matched filter taps, bufferdepth, and clock frequency. These regis-ters will proliferate as the chip designexposes more energy scalability optionsto the programmer.

Because leakage will dominate totalpower dissipation in the future, next-generation sensor DSPs might requirereduced memory size, perhaps byincreasing computation. Examples in-clude decoding complex instructionstreams and compressing data beforestoring it to memory.

The past decade has seentremendous advances in low-power and energy-efficientdesign techniques for various

processors, including DSPs. As processtechnology scales, power constraints willlimit achievable performance and put apremium on energy-efficient architec-tures.11 This premium will be evenhigher for processors in energy harvest-ing applications.

In general, the lower the processor’speak performance, the higher its energyefficiency. Specialized architectures aretypically more efficient than general-purpose architectures. Figure 7 showssummary energy-efficiency data (ex-pressed as millions of operations per sec-ond per watt (MOPS/W), equivalent toµJ per operation) from a number of gen-eral-purpose processors, DSPs, and theSensorDSP specialized processor. Itshows SensorDSP chip data scaled fromthe original 0.6 µm CMOS implemen-tation to 0.25 µm and 0.18 µm. Thechip’s low peak performance ensures bet-ter energy efficiency than chips targetinghigher performance.

The SensorDSP has greater energy effi-ciency because of its specialized func-tional units, such as the DA module. Thisefficiency motivates our work on a next-generation DSP architecture that com-bines a reconfigurable DA array with a



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Figure 7. Energy efficiency of variousprocessors. Specialized or application-specific architectures, such as the Sensor-DSP chip, exploit low peak performancerequirements to achieve better energyefficiency with decreasing feature size.


low-energy microcontroller. We are tar-geting an energy efficiency of 107

MOPS/W, or 10 teraOPS/W (0.1 pJ/Op).Achieving this unprecedented level ofenergy efficiency will be challenging asleakage power becomes significantbeyond the 130-nm process node andrequires new approaches such as self-timed circuits and bit-serial arithmetic.By exploring such innovative conceptsin circuits and DSP architecture, we hopeto enable the next generation of energyharvesting sensors.

ACKNOWLEDGMENTSThe US Army Research Laboratory supported thiswork under the Advanced Sensors Federated Labprogram, contract no. DAAL01-96-2-0001. Addi-tional funding came from a New Faculty ResearchGrant from the University of California, Davis.

REFERENCES 1. S. Roundy et al., “A 1.9-GHz RF Transmit

Beacon Using Environmentally ScavengedEnergy,” paper presented at 2003 Int’lSymp. Low-Power Electronics and Design(ISLPED 03); http://engnet.anu.edu.au/DEpeople/Shad.Roundy.

2. R. Amirtharajah et al., “A Micropower Pro-grammable DSP Powered Using a MEMS-Based Vibration-to-Electric Energy Con-verter,” Int’l Solid State Circuits Conf.(ISSCC 2000) Digest of Tech. Papers, IEEEPress, 2000, pp. 362–363, 469.

3. A. Wang and A.P. Chandrakasan, “Energy-Efficient DSPs for Wireless Sensor Net-works,” IEEE Signal Processing Magazine,July 2002, pp. 68–78.

4. R. Amirtharajah and A. Chandrakasan,“Self-Powered Signal Processing UsingVibration-Based Power Generation,” IEEEJ. Solid-State Circuits, vol. 33, no. 5, 1998,pp. 687–695.

5. D. Rowe, “Demonstration System for aLow Power Classification Processor,” mas-ter’s thesis, Mass. Inst. of Technology, Feb.2000.

6. K. Roy, S. Mukhopadhyay, and H. Mah-mood-Meimand, “Leakage Current Mech-anisms and Leakage Reduction Techniquesin Deep-Submicrometer CMOS Circuits,”Proc. IEEE, vol. 91, no. 2, 2003, pp.305–327.

7. S.A. White, “Applications of DistributedArithmetic to Digital Signal Processing: ATutorial Review,” IEEE ASSP Magazine,July 1989, pp. 4–19.

8. R. Amirtharajah and A. Chandrakasan, “AMicropower Programmable DSP UsingApproximate Signal Processing Based onDistributed Arithmetic,” IEEE J. Solid-State Circuits, vol. 39, no. 2, 2004, pp.337–347.

9. T. Yasuda, M. Yamamoto, and T. Nishi, “APower-On Reset Pulse Generator for Low

Voltage Applications,” Proc. Int’l Symp.Circuits and Systems (ISCAS 01), vol. 4,IEEE Press, May 2001, pp. 599–601.

10. F.A. Marvasti, A Unified Approach to Zero-Crossings and Nonuniform Sampling,Nonuniform Pub., 1987.

11. M. Horowitz and W. Dally, “How ScalingWill Change Processor Architecture,” Int’lSolid State Circuits Conf. (ISSCC 2004)Digest of Tech. Papers, IEEE Press, 2004,pp. 132–133.

For more information on this or any other comput-ing topic, please visit our Digital Library at www.computer.org/publications/dlib.

the AUTHORS

Rajeevan Amirtharajah is an assistant professor in the Electrical and ComputerEngineering Department at the University of California, Davis. His research interestsinclude low-power VLSI design for sensor applications, powering systems fromambient energy sources, and high-performance circuit and interconnect design. Hereceived his PhD in electrical engineering from the Massachusetts Institute of Tech-nology. He’s a member of the IEEE, AAAS, and Sigma Xi. Contact him at the Dept. ofElectrical and Computer Eng., Univ. of California, One Shields Ave., Davis, CA95616-5294; [email protected].

Jamie Collier is a graduate student in electrical engineering at the University of Cali-fornia, Davis. Her graduate research is in the area of low-power memory and inter-connect for energy harvesting power supplies. She received her BS in electrical engi-neering from Case Western Reserve University. Contact her at the Dept. of Electricaland Computer Eng., Univ. of California, One Shields Ave., Davis, CA 95616-5294; [email protected].

Jeff Siebert is a graduate student in electrical engineering at the University of Cali-fornia, Davis. His graduate research is in circuits for energy harvesting with a focuson pipelined data paths using AC power supplies. He received his BS in electricalengineering from Case Western Reserve University. Contact him at the Dept. of Elec-trical and Computer Eng., Univ. of California, One Shields Ave., Davis, CA 95616-5294; [email protected].

Bicky Zhou is a post-silicon validation engineer at Intel. Her research interests focuson custom hardware design for energy scalability and power trade-offs between ser-ial and parallel computations as CMOS technology scales. She received her MS inelectrical and computer engineering from the University of California, Davis. Contacther at 900 Jackson St., Apt.105, Oakland, CA 94607; [email protected].

Anantha P. Chandrakasan is a professor of electrical engineering and computerscience at the Massachusetts Institute of Technology and a cofounder and chief sci-entist at Engim, a company focused on high-performance wireless communications.His research interests include the ultra-low power implementation of custom andprogrammable digital signal processors, distributed wireless sensors, ultra-widebandradios, and emerging technologies. He received his PhD in electrical engineeringand computer sciences from the University of California, Berkeley. Contact him atMIT, 50 Vassar St., 38-107, Cambridge, MA 02139; [email protected].

DSPs for Energy Harvesting Sensors - ECEramirtha/promotion/amirtharajahA20.pdfDSPs for Energy Harvesting Sensors: Applications and Architectures O ... a MEMS variable-capacitor transducer

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