EE457 Page Table and TLB in x86 Updated: 10/21/2018 Slides and figures extracted from their MindShare_x86_Processor_Platform_Architecture_vB.2.pdf with their permission for use in EE457 and EE560 courses. These slides should not be posted anywhere or shared with anyone.
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EE457Page Table and TLB in x86
Updated: 10/21/2018
Slides and figures extracted from their MindShare_x86_Processor_Platform_Architecture_vB.2.pdfwith their permission for use in EE457 and EE560 courses.These slides should not be posted anywhere or shared with anyone.
In x86, in the 32-bit system, the 32-bit Virtual address is divided into a 20-bit VPN and 12-bit page offset.A 2-level page table is used as shown in the next page.
PDE (Page Directory Entry) and PTE (Page Table Entry) are each 32 bits in size. 1024 entries*32-bits each = 4 KBytes
PTBRPage Table Base Register
PDEPage Directory Entry PTE
Page Table Entry
https://docs.microsoft.com/en-us/windows/desktop/memory/physical-address-extension
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