Overview of Personal Computers

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Historical Overview ofPersonal Computers

In light ofPerformance Parameters


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SEQUENCE

Scope & Objectives Introduction to PCs

Performance Measure

Performance Parameters

Major Limitations

Solutions

Clock Doubling

Cache Memory Pipelining Instructions

Multibus Systems

Historical Overview of Intel PCs

8086 to Pentium-III


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The Scope And Objective is toBriefly Discuss the Technological

Factors Leading to Advancementsin PCs Performance and to Analyze

the Salient Features of PCs over

the Last Two Decades

SCOPE & OBJECTIVE


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Central Processing Unit (CPU)

Memory Unit

Interconnecting Network

Input Output Devices

INTRODUCTION


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Same Hardware Environment

Same Software Environment

Same Operating System

Number of Instructions Executed in a

Specified Time

PERFORMANCE MEASURE


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CPU Fetches Instruction from RAM

CPU Decodes Instruction

CPU Fetches Data (If Required)

CPU Performs required Operation

CPU Stores result back into RAM

STEPS INVOLVED


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CPU Execution Speed

Decoding Time

Operation Time

Memory Read / Write Time

RAM Speed

Bus Speed

PERFORMANCEPARAMETERS


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Single CPU Clock System CPU and Devices have Different Rates

RAM Speed

No where Close to CPU Speed

System Bus Speed

Low Bandwidth (Data Rate) Input / Output Devices Speed

Variety of Devices (FDD, HDD, CDD)

MAJOR LIMITATIONS


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Single CPU Clock System Clock Doubling Concept

RAM Speed

Cache Memory

System Bus Speed

Pipelining Concept (RISC) Input / Output Devices Speed

Multiple Bus Architectures

SOLUTIONS


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High Internal Clock

For CPU

Low External Clocks

For RAM

For Buses

CLOCK DOUBLING


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High Speed Memory

Level - 1 Cache

Level - 2 Cache

Level - 3 Cache

Low Capacity due to High Cost

CACHE MEMORY


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CACHE MEMORY (Contd)

Mother Board of PC

CPU IC Pack

CPU Chip

L-1 Split Cache

L-2 Unified Cache

L-3 Cache RAM


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Information Flow

CACHE MEMORY

I/ODevices

RAMCache

L-3

Cache

L-2

Cache

L-1- I

Cache

L-1- D


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RISC Computers

Five Stages of Instruction Pipelining

Instruction Fetch Instruction Decode

Fetch Operands

Execute Instruction

Store Result

PIPELINING CONCEPT


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PIPELINING CONCEPT

Time

Inst

T-1 T-2 T-3 T-4 T-5 T-6 T-7 T-8

1 Fetch Dec Data Exe





Time for One Inst


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MULTIBUS ARCHITECTURE

Level 2

Cache

CPU

P-II

PCI

Bridge

Main

Memory

ISA

Bridge

SCSI USB

Mouse K/B

VGAIDE

Disk

Mon

itor

Modem Sound

Card

Printer

Cache BusLocal Bus Memory Bus

PCI Bus

ISA Bus

PCISlot

ISA

Slot


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ISA Bus 20 Address Lines 8 Data Lines

8.33 MHz Speed Max BW = 16.7 MB/Sec

Extended ISA Bus

32 Address Lines 16 Data Lines

8.33 MHz Speed

Max BW = 33.3 MB/Sec

BUS CHARACTERISTICS


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PCI Bus

High Speed = 33 MHz

Up to 64 Data Lines

Max BW = 264 MB/Sec

or 2.112 Gbps Backward (ISA) Compatibility

BUS CHARACTERISTICS


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HistoricalOverview


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1978 : 8080 Based PC 16 Bit CPU / System Bus

Speed 4.77 MHz

Hardware (mother board) 8 Bits

1980 : 8088 Based PC

16 Bit CPU Internally 8 Bit Data Bus Externally

Speed 4.77 MHz

Hardware Compatible

Ist Generation PCs


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1982 : 80286 Based PC

16 Bit CPU / System Bus

Speed 6 - 12 MHz Hardware 16 Bits

Four Times Faster Than 8088

Backward Compatible

2nd Generation PCs


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1985 : 80386 Based PC Intel Microprocessor

32 Bit CPU

Speed 16 - 33 MHz

Windows Became Possible

Multitasking Environment

Cloned PCs Emerged

AMD, Cyrix

Speed 40 MHz

3rd Generation PCs


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1985 : 80486 Based PC

32 Bit CPU / System Bus

8 KB L-1 Cache

Pipelining of Instructions

Speed 75 - 100 MHz

4th Generation PCs


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1993 : Pentium PC

Superscalar PC

Parallel Processing

64 Bit Data Processing

16 KB L-1 Cache Speed 100 - 200 MHz

Bus Speed Limited to 66 MHz

5th Generation PCs


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1997 : Pentium MMX PC Superscalar PC

64 Bit Data Processing

32 KB L-1 Cache

New Set of Instructins

57 New Instructions for Graphics Speed 166 - 233 MHz

Bus Speed Limited to 66 MHz

5th Generation PCs


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Pentium Pro PC 4 Stage Parallel Pipelining

256 KB L-2 Cache

New Set of Instructins

RISC Concept with

CISC Backward CompatibilityBus Speed Limited to 100 MHz

6th Generation PCs


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Pentium II PC 7 Stage Pipelining

4 Parallel Execution Units

Two Split 16 KB L-1 Cache

256 KB L-2 Unified Cache

New Set of Instructins MMX Instructions Included

Speed 233 - 300 MHz

6th Generation PCs


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Celeron PC

Same as Pentium II

L-2 Cache Chopped Away

Inexpensive for Low End Users

6th Generation PCs


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Pentium III (Katamai) PC

Katamai New Instructions Set

70 New Instructions

Additional Registers for CPU

Speed 500 - 866 MHz

7th Generation PCs


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Pentium III (CuMine) PC

Katamai New Instructions Set

Integrated L-2 Cache

Operable at Full CPU Speed

Data Bus 256 Bits Speed 600 1000 MHz and Above

System Bus Speeds 100 - 133 MHz

7th Generation PCs


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THANK YOU

Overview of Personal Computers

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