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Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Presentation #9: Smart Cart 525 Stage IX: 16 Mar. 2005 Chip Level Layout
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Overall Project Objective:

Dec 30, 2015

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Presentation #9: Smart Cart 525. Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager : Myron Kwai. Overall Project Objective: - PowerPoint PPT Presentation
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Page 1: Overall Project Objective:

Idongesit Ebong (1-1)Jenna Fu (1-2)

Bowei Gai (1-3)Syed Hussain (1-4)Jonathan Lee (1-5)

Design Manager: Myron Kwai

Overall Project Objective:Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID)

technology while creating a quicker, more convenient shopping experience.

Presentation #9:

Smart Cart 525

Stage IX: 16 Mar. 2005Chip Level Layout

Page 2: Overall Project Objective:

Status Design Proposal

Project chosen Verilog obtained/modified

Architecture Proposal Behavioral Verilog simulated

Size estimates/floorplanning Gate-level implementation simulated in Verilog Floorplan and more accurate transistor count

Schematic Design Component Layout Functional Block Layout

DRC of functional blocks LVS of functional blocks

Chip Level Layout (98.56% Done) 3 Main blocks (each block LVSes) Full chip LVS

Simulations

Page 3: Overall Project Objective:

Design Decisions

Decided to route more wires over the SBOX and use metal 4 to reach registers on the right

Move items in the encryption block higher up and redesign SBOX logic

Page 4: Overall Project Objective:

Previously…

Page 5: Overall Project Objective:

Currently (320.220x293.355)

Page 6: Overall Project Objective:

Updated Transistor Count

Old New

Encryption 13,054 13,904

Multiplier 2042 2126

Adder 544 600

SRAM 2276 2276

Logic 400 594

Registers (inputs/outputs) 2540 2540

Total 20,856 22,040

Page 7: Overall Project Objective:

Updated Floorplan

Area: Old (μm2) New (μm2)

Encryption 68,352 60,983

Multiplier 8856 8420

Adder 3920 3429

SRAM 10,695 8183

Logic/Wiring 14,655 14,655

Registers (inputs/outputs, counters)

4490 4266

Total 110,968 91,365

Density: (transistors/μm2)

Aspect ratio:.191.36

0.261.1

Page 8: Overall Project Objective:

Layer MasksPoly

Page 9: Overall Project Objective:

Layer MasksMetal1

Page 10: Overall Project Objective:

Layer MasksMetal2

Page 11: Overall Project Objective:

Layer MasksMetal3

Page 12: Overall Project Objective:

Layer MasksMetal4

Page 13: Overall Project Objective:

Layout: Multiplier

Page 14: Overall Project Objective:

Layout: SRAM/Adder

Page 15: Overall Project Objective:

Layout: FinalText/Initial Permutation

Page 16: Overall Project Objective:

Layout: Mix Column/Rcon

Page 17: Overall Project Objective:

Layout: Key Expand

Page 18: Overall Project Objective:

Layout: SBOX

Page 19: Overall Project Objective:

Problems & Questions

Registers problematic How can we make the chip smaller? Re-doing many of the blocks, learn from previous

mistakes. Reset signal strength and buffer size needed for

it. White space reduction Simulations take a long time.