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�� Summary of Methods to Reduce AliasingSummary of Methods to Reduce Aliasing
Compaction TechniquesCompaction Techniques
�� Compact multiple output responses into a single resultCompact multiple output responses into a single result�� Counting TechniquesCounting Techniques
��Counting 1s or 0sCounting 1s or 0s��Also called Syndrome AnalysisAlso called Syndrome Analysis��Similar to Berger and BoseSimilar to Berger and Bose--Lin error detection codesLin error detection codes
��Counting lowCounting low--toto--high, highhigh, high--toto--low, or both transitions low, or both transitions ��Hardware: countersHardware: counters
C. Stroud 9/09 Output Response Analysis 2
��Hardware: countersHardware: counters
�� Signature analysisSignature analysis(most common ORA in BIST)(most common ORA in BIST)��Single output Single output -- Signature Analysis Register (SAR)Signature Analysis Register (SAR)��Multiple outputs Multiple outputs -- Multiple Input Signature Register (MISR)Multiple Input Signature Register (MISR)
��Hardware: LFSR (CAR would also work)Hardware: LFSR (CAR would also work)
�� Can be used with concentratorsCan be used with concentrators�� Aliasing Aliasing –– faulty circuit produces good circuit faulty circuit produces good circuit
signature/syndromesignature/syndrome
ConcentratorsConcentrators�� Used to reduce number of outputs to be monitoredUsed to reduce number of outputs to be monitored
��Compacts number of output responsesCompacts number of output responses��Does not compact output responses in timeDoes not compact output responses in time
�� Hardware: tree of XOR gatesHardware: tree of XOR gates��Same as parity generationSame as parity generation
�� Often used with other ORA techniquesOften used with other ORA techniques��Passes any combination of odd errorsPasses any combination of odd errorsNN
Outto ORAOutto ORANOutto ORA
C. Stroud 9/09 Output Response Analysis 3
��Passes any combination of odd errorsPasses any combination of odd errors��Masks any combination of even errorsMasks any combination of even errors
�� Not selfNot self--testingtesting��Can be tested in only 4 vectorsCan be tested in only 4 vectors
��SS⊕⊕T=RT=R��RR⊕⊕S=TS=T��TT⊕⊕R=SR=S
NN to ORAto ORAN to ORA
S T RS T R0 0 00 0 00 1 10 1 11 0 11 0 11 1 01 1 0
S T RS T R0 0 00 0 00 1 10 1 11 0 11 0 11 1 01 1 0
S T RS T R0 0 00 0 00 1 10 1 11 0 11 0 11 1 01 1 0
++++
++
++++++++
In0In1In2In3In4In5In6In7
In0In1In2In3In4In5In6In7
Outto ORAOutto ORA
SS
TTRR
RR
TT
SS
RR
1100 S1010 T0110 R1100 S1010 T0110 R1100 S1010 T
1100 S1010 T0110 R1100 S1010 T0110 R1100 S1010 T
++
+
++++
In0In1In2In3In4In5In6In7
Outto ORA
S
TR
R
T
S
R
1100 S1010 T0110 R1100 S1010 T0110 R1100 S1010 T
ComparatorsComparators�� Works well with known good output responsesWorks well with known good output responses
��From algorithmic TPGFrom algorithmic TPG��Hardware: comparator (w/latch) & extra TPG logic for output responseHardware: comparator (w/latch) & extra TPG logic for output response
��From simulation stored in ROMFrom simulation stored in ROM��Hardware: comparator (w/latch) & ROM with counterHardware: comparator (w/latch) & ROM with counter
��Counter faults are maskedCounter faults are masked
��Outputs of identical circuits with same test patternsOutputs of identical circuits with same test patterns��Hardware: comparator and latchHardware: comparator and latch
C. Stroud 9/09 Output Response Analysis 4
��Hardware: comparator and latchHardware: comparator and latch��Equivalent faults are maskedEquivalent faults are masked
��Latch up mismatches until end of BIST sequenceLatch up mismatches until end of BIST sequence��Should be RS flipShould be RS flip--flopflop
��RS latch susceptible to glitchesRS latch susceptible to glitches
�� Single Pass/Fail indicationSingle Pass/Fail indication��What if it is “stuckWhat if it is “stuck--atat--pass”?pass”?��Not selfNot self--testing testing -- need additional test vectorsneed additional test vectors
Pass/FailPass/Fail
A1
B1
An
Bn
A1
B1
An
Bn
setresetsetreset
BIST startClock
BIST startClock
Pass/Fail
A1
B1
An
Bn
setreset
BIST startClock
1s or 0s counting (Syndrome Analysis)1s or 0s counting (Syndrome Analysis)�� Assume Assume m m input vectorsinput vectors
�� Response Response R R = = rr11, r, r22,..., r,..., rmm
��Multiple countersMultiple counters��Use concentrator to reduceUse concentrator to reduce
��Glitches from combinational logic Glitches from combinational logic outputs could be counted if TD is outputs could be counted if TD is connected to clock input of counterconnected to clock input of counter��FaultFault--free CUT declared faultyfree CUT declared faulty
�� Transition detectors Transition detectors –– digital onedigital one--shotshot
��Note: TD output connects to enable input of counterNote: TD output connects to enable input of counter��Not to clock input since glitches cause incorrect resultsNot to clock input since glitches cause incorrect results
BothBothInputInput
ClockClock
RisingRisingInputInput
ClockClock
FallingFallingInputInput
ClockClock
BothInput
Clock
RisingInput
Clock
FallingInput
Clock
C. Stroud 9/09 Output Response Analysis 7
�� SelfSelf--testing?testing?
��Only if syndrome > 2Only if syndrome > 2nn--11
��Where Where nn = number of bits of counter= number of bits of counter
��Need to toggle MSB of counterNeed to toggle MSB of counter
Probability of Signature Aliasing:Probability of Signature Aliasing:�� ≅≅ 22--nn where where nn = degree of characteristic (size of LFSR)= degree of characteristic (size of LFSR)Reducing the probability of signature aliasing:Reducing the probability of signature aliasing:�� Use a large signature analyzerUse a large signature analyzer
��High degree characteristic polynomialHigh degree characteristic polynomial�� Use primitive polynomialsUse primitive polynomials�� Use long test sequencesUse long test sequences
C. Stroud 9/09 Output Response Analysis 12
�� Use long test sequencesUse long test sequences�� Use multiple polynomialsUse multiple polynomials
��ReRe--apply same test patterns for different polynomialsapply same test patterns for different polynomials�� ReRe--apply the same test patterns in reverse orderapply the same test patterns in reverse order�� Observe intermediate signaturesObserve intermediate signatures�� Use a biUse a bi--directional MISRdirectional MISR
�� rere--apply same patterns after reversing shift directionapply same patterns after reversing shift direction
AccumulationAccumulation�� Same as checksum error detection codesSame as checksum error detection codes�� Three types Three types –– but there are othersbut there are others
�� Single precision Single precision –– ignore carryignore carry--outout�� NN--bit code wordbit code word
�� Residue Residue –– endend--aroundaround--carry (carry added as an LSB)carry (carry added as an LSB)�� NN--bit code wordbit code word
�� Double precision Double precision –– retain all carriesretain all carries�� 22NN--bit code wordbit code word
�� Good for mixedGood for mixed--signal circuits to allow for expected variations in signalssignal circuits to allow for expected variations in signals
C. Stroud 9/09 Output Response Analysis 13
�� Good for mixedGood for mixed--signal circuits to allow for expected variations in signalssignal circuits to allow for expected variations in signals�� Due to temperature, voltage, tolerance of componentsDue to temperature, voltage, tolerance of components
Other ORAsOther ORAs�� CA registers can be used for signature analysisCA registers can be used for signature analysis
��SelfSelf--testingtesting
�� Parity checkParity check
��Can be used with concentrator for multiple outputsCan be used with concentrator for multiple outputs
��Can be viewed as special case ofCan be viewed as special case of��Syndrome analysis: 1s counting with 1Syndrome analysis: 1s counting with 1--bit counterbit counter
C. Stroud 9/09 Output Response Analysis 14
��Checksum: 1Checksum: 1--bit single precision accumulatorbit single precision accumulator