1 EE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces Lecture 24 Case Studies Digital Subscriber Lines Borivoje Nikolic April 15, 2004. 2 Outline Project phase-II specs Wrap up disk-drive signal processing Signal processing for digital subscriber lines
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EE290C - Spring 2004Advanced Topics in Circuit DesignHigh-Speed Electrical Interfaces
Lecture 24Case Studies
Digital Subscriber LinesBorivoje NikolicApril 15, 2004.
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Outline
Project phase-II specsWrap up disk-drive signal processingSignal processing for digital subscriber lines
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EE290C - Spring 2004Advanced Topics in Circuit DesignHigh-Speed Electrical Interfaces
Project Phase #2
Specific Circuit Requirements
Jared Zerbe4/15/04
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Phase-II
Most of this is circuit design of blocksBUT
Your circuit design may have input on your architecture
Result – iterate and modifyFinal phase-II report to include both architecture conclusions/performance and circuit design
Major points of interaction1. Output driver peak-power constraint2. Tx, Rx device parasitics3. Dither jitter and impact on timing budget
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Circuit Blocks
Each group needs to designPLL + CDRTX / TX eq (as appropriate)RX / RX eq (as appropriate)System results
All blocks should include power & performance range
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PLL + CDR : Phase-II expectations
PLLLoop bandwidth, damping factor
Peak-peak jitter
Frequency range
CDRStep-size, latency
dither jitter
BothResponse to power-supply step : ps/mV for transmit & receive clocks
Response to 20Mhz sine wave on power supply
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TX / TX Equalizer (as appropriate)
TXCommon-mode range, swing, swing control method, resolutionPeak power constraint : should keep CS’s saturatedTX induced ISI
0101 + 00110011 + 000111 pattern : p-p jitter
EqualizerCoefficient resolution, # of taps, summing
BothTotal Ci of output needs to be put back into spice to get final channel
EqualizerGain-bandwidth of linear equalizerPower/summing ISI of any DFE
BothTotal Ci of input needs to be put back in spice to get final channel
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System
Final system results should includePeak performance over all 5 channels
BER of each configuration ORVoltage, timing margin (vs. RX requirement) for each configuration
Complete power of TX, RX, PLL/CDRMatlab results showing adaptation of equalizer coefficients
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Design Challenges
One of the first Systems-on-a-Chip (SoC)> 2Gb/s ratePower limited (<2W, preferably 1W), inexpensive (<$2.5)Single step vs. lookahead/parallelReduced SNR, complex detectionIntegration with controller gives opportunities for more powerful coding and processing
Iterative decoders (Turbo, LDPC)
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Architectural Choices
Equalizer6-10 taps, >1Gb/sChoices of interleaving, pipelining, recoding, carry-save“Infinite” speed at the expense of power
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Architectural Choices
Viterbi Decoder16 – 32 state, trellis coded with prostprocessor, variable equalization targetsRadix-2 vs. Radix-4, ACS vs. CSABit-level pipelining
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Future Signal Processing
SNRs will continue to decreaseIterative decoding – LDPC based
Can we control the byte error rate?Complexity?Timing recovery at low SNRs
Vertical recording is already backMulti-track recording?