1 EE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces Lecture #22 Link Budgeting and BER Analysis Vladimir Stojanovic ([email protected]) Stanford University and Rambus Inc. 4/8/2004 2 Agenda Backplane channel review Link system models and noise Performance analysis
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EE290C - Spring 2004Advanced Topics in Circuit DesignHigh-Speed Electrical Interfaces
Lecture #22Link Budgeting and BER AnalysisVladimir Stojanovic ([email protected])Stanford University and Rambus Inc.4/8/2004
2
Agenda
Backplane channel reviewLink system models and noisePerformance analysis
2
3
Backplane Environment - Recap
Line attenuationReflections from stubs (vias)
Back plane connector
Line card trace
Package
On-chip parasitic(termination resistance and device loading capacitance)
Line card via
Back plane trace
Backplane via
Package via
Back plane connector
Line card trace
Package
On-chip parasitic(termination resistance and device loading capacitance)
Line card via
Back plane trace
Backplane via
Package via
4
Backplane ChannelLoss is variable
Same backplaneDifferent lengthsDifferent stubs
Top vs. Bot
Required signal amplitude set by noise
Need to architect the link to work over all channels
Need tools to estimate link performance over all channels
0 2 4 6 8 10
-60
-50
-40
-30
-20
-10
0
frequency [GHz]
Atte
nuat
ion
[dB
]
9" FR4, via stub
26" FR4,via stub
26" FR4
9" FR4
3
5
Inter-symbol Interference (ISI) - RecapChannel is low pass
Middle sample is corrupted by 0.2 trailing ISI (from the previous symbol), and 0.1 leading ISI (from the next symbol) resulting in 0.3 total ISIAs a result middle symbol is detected in error
0 2 4 6 8 10 12 14 16 180
0.2
0.4
0.6
0.8
1
Symbol time
Am
plitu
de
Error!
4
7
CrosstalkDon’t just receive the signal you want
Get versions of signals “close” to youVertical connections have worse coupling
“Close” in these vertical connection regions
Far-end XTALK (FEXT)
Desired signal
Near-end XTALK (NEXT)
Reflections
Sercu, DesignCon03
8
Frequency View of Crosstalk
For this example:> 4GHz, noise is as large as the signal
0 2 4 6 8 10
-60
-50
-40
-30
-20
-10
0
frequency [GHz]
Atte
nuat
ion
[dB
]
FEXT
NEXT
THROUGH
5
9
Agenda
Backplane channel reviewLink system models and noise
Previous standard approachesStatistical modeling
Performance analysis
10
Parameter Definition for VT Based BudgetVoltage parameter definitions
tCE is at 23% of bit timevCE is at 62.5% Vswing (900mV)
12
Fiber Channel – Methodologies for Jitter SpecificationTotal jitter = Deterministic (DJ) + random jitter (RJ)DJ: Non-Gaussian, bounded in amplitude and has specific causes (duty cycle distortion, data dependent, sinusoidal and uncorrelated (power supply noise injection))DJ is measured as a peak-to-peak value and adds linearlyRJ: Gaussian and measured as an RMS valueRJ: Peak-to-peak jitter = 14 * RMS jitter for a BER of 10
-12
Total jitter = peak-to-peak DJ + peak-to-peak RJJitter measurement definitions
Jitter outputJitter transferJitter tolerance (ability of a CDR to successfully recover the data in the presence of jitter)
Create a tolerance mask by examining the CDR lock at different frequencies vs. sinusoidal jitter magnitude
7
13
Jitter measurement definitions
Jitter generation (jitter added by the PLL due to phase and supply noise)Jitter transfer (jitter at the output of the PLL due to refClk noise)Jitter tolerance (ability of a CDR to successfully recover the data in the presence of jitter)
Create a tolerance mask by examining the CDR lock at different frequencies vs. sinusoidal jitter magnitude
Low-pass from reference (input clock)Band-pass from VCO supplyHigh-pass from clock buffer supply
M. Mansuri, C-K.K. Yang, "Jitter optimization based on phase-locked loop design parameters," IEEE Journal Solid-State Circuits, Nov. 2002
16
31
PLL supply noise
Total noise ~ 25mV peak-to-peak3.7% of on-chip VddA (quiet PLL supply)
Deterministic noise still present.
Where is this noise coming from?
E. Alon, V. Stojanovic, M. Horowitz “Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise,” IEEE Symposium on VLSI Circuits, June 2004.
32
Noise Spectrum (1)
Deterministic noise frequency components:200MHz - ASIC core operating frequency.
Noise on link supplies due to ground bounce.400MHz - reference clock, some link logic.4GHz - link data rate.
Data & edge clocks at 2GHz => 4GHz noise.Tail current modulation in diff. pairs.
10MHz 100MHz 1GHz 10GHz-100
-80
-60
-40
-20
0
Frequency
PSD
(dBV
)
10MHz 100MHz 1GHz 10GHz-100
-80
-60
-40
-20
0
Frequency
PSD
(dBV
)
Noise floor Noise floor
Vdd noise VddA noise
17
33
Noise Spectrum (2)
Random noise mostly white.Low frequency peaking in Vdd noise due to underdamped impedance of distribution network.
VddA distribution network more damped because of higher resistance.
10MHz 100MHz 1GHz 10GHz-100
-80
-60
-40
-20
0
Frequency
PSD
(dBV
)
10MHz 100MHz 1GHz 10GHz-100
-80
-60
-40
-20
0
Frequency
PSD
(dBV
)
Noise floor Noise floor
Vdd noise VddA noise
34
Slicer
PD
deserializer
PLL
dataOut
ref Clk
Phasecontrol
Phasemixeredge Clk
data Clk
RX
2x Oversampled Bang-Bang CDR
Generate early/late from dn,dn-1,enSimple 1st order loop, cancels receiver setup time
Now need jitter on data Clk, not PLL output
dn-1
dn
en (late)
dn
en
18
35
Data Clk NoiseModel phase selector and PLL
Base linear PLL jitterAdd non-linear phase selector noise from CDR
Model the CDR loop as a state machineThe current phase position is the stateState transitions are caused by early/lateJitter on input data and PLL means
Possible to be late and get early PD resultOften filter early/late to generate up/down
A.E. Payzin, "Analysis of a Digital Bit Synchronizer," IEEE Transactions on Communications, April 1983.
36
Transition Probabilities
0 50 100 150 200 2500
0.2
0.4
0.6
0.8
1
Accumulate-resetfilter, length 4Pr
obab
ility
Phase count
p-early
p-hold
p-late
p-no-validtransitions
p-up p-dn Example system:CDR loopResidual ISI
At edge -30dBVDesired phase
State = 133
On average move to correct positionBut probability of wrong movement is not smallNeed to find probability of at each phase location
19
37
Bang-Bang CDR Statistical Model
Need steady state probabilities of the statesHave the transition probabilities
Iteratively apply transition probabilities (Markov chain)Results will converge to a steady-state
iφ1−iφ 1+iφ0φ Lφ
iholdp ,
iupp ,
idnp ,
38
0 50 100 150 200 250
-15
-10
-5
0
Phase Count
log 10
Ste
ady-
Stat
e Pr
obab
ility
Bang-Bang CDR Model
Gives the probability distribution of phaseWhich is the CDR jitter distribution
20
39
Noise and Interference SummaryMany important sources of noise and interference
ISI, crosstalk, quantization, estimation, etc.Largest error comes from ISI
By factor of 10xTiming is noisy too
High frequency transmitter jitter is badCDR jitter needs to be considered
Especially if the data input is noisy
What is the impact on performance?
40
Agenda
Backplane channel reviewLink system models and noise
Previous standard approachesStatistical modeling
Performance analysis
21
41
50 60 70 80 90 100 110-300
-200
-100
0
100
200
300
time [ps]
volta
ge [m
V]
-30
-25
-20
-15
-10
-52PAM - lin. eq
ISI and CDR Phase Distributions
In ideal world, there would be only two dotsThis plot shows how these dots spread out
Vertical slice – ISI distribution per time offsetHorizontal weight – CDR phase distribution
42
Putting It All Together
To compare different designsCompare the voltage margin at given BER
Need to include all noise sourcesAccurate ISI distributionTransmit and receive jitterCDR jitterEQ quantization noiseReceiver offset
22
43
0 20 40 60 80 100 120 140 160-150
-100
-50
0
50
100
150
time [ps]
mar
gin
[mV]
-30
-25
-20
-15
-10
-5
BER Contours
Voltage marginMin. distance between the receiver threshold and contours with same BER
0 20 40 60 80 100 120 140 160-150
-100
-50
0
50
100
150
time [ps]m
argi
n [m
V]
-30
-25
-20
-15
-10
-5
5 tap Tx Eq 5 tap Tx Eq + 1 tap DFE
44
BER Contours PAM2 DFE PAM4 linear equalization
0 40 80 120 160250
200
150
100
-50
0
50
100
150
200
250
time [ps]
mar
gin
[mV]
-30
-25
-20
-15
-10
-5
0 40 80 120 160 200 240 280 320-250
-200
-150
-100
-50
0
50
100
150
200
250
time [ps]
mar
gin
[mV]
-30
-25
-20
-15
-10
-5
23
45
Model and measurements
-80-60-40-200 20 40 60 80
-14
-12
-10
-8
-6
-4
-2
0
log1
0(B
ER)
Voltage Margin [mV]
PAM4, 3taps of transmit equalization, 5Gb/s, 26” FR4 channel
46
Example channels
Legacy (FR4) - lots of reflectionsMicrowave engineered (NELCO)
0 5 10 15 20
-100
-80
-60
-40
-20
0
Atte
nuat
ion
[dB
]
frequency [GHz]
26" FR4, via stub
26" NELCO,no stub
(b)
V. Stojanović, A. Amirkhany, M. Horowitz, “Optimal Linear Precoding with Theoretical and Practical Data Rates in High-Speed Serial-Link Backplane Communication,” IEEE International Conference on Communications, June 2004
24
47
Capacity achieving bit loading
0 5 10 15 20 250
1
2
3
4
5
6
7
8
9
10
frequency [GHz]
#bits
/Hz
Capacity with thermal noise
Nelco 105Gb/sFR4 70Gb/s
0 2 4 6 8 10 12 140
2
4
6
8
10Multi-tone data rates with thermal noise
Nelco 64Gb/sFR4 38Gb/s
#bits
/Hz
frequency [GHz]
Capacity is very bigPractical rates lower
low target BER<10-15
peak power constraintThermal noise – the smallest noise source
48
Capacity with link-specific noise
Effective noise from phase noiseProportional to signal energyDecreases expected gains
Still, capacity is much higher than data rates in today’s links (3Gb/s)
NELCO FR4
-25 -20 -15 -10 -5 00
20
40
60
80
100
120
140
Cap
acity
[Gb/
s]
log10(Clipping probability)
thermal noise
thermal noise and LC PLL phase noise
thermal noise and ring PLL phase noise
-25 -20 -15 -10 -5 00
20
40
60
80
100
120
140
Cap
acity
[Gb/
s]
log10(Clipping probability)
thermal noise
thermal noise and LC PLL phase noise
thermal noise and ring PLL phase noise
25
49
Multi-tone with integer bit loading
-25 -20 -15 -10 -5 00
10
20
30
40
50
60
70
80
90D
ata
rate
[Gb/
s] a) NELCOthermal noise
thermal noise and LC PLL phase noise
thermal noise and ring PLL phase noise
log10(Clipping probability)-25 -20 -15 -10 -5 00
10
20
30
40
50
60
70
80
90
Dat
a ra
te [G
b/s] b) FR4
thermal noise
thermal noise and LC PLL phase noise
thermal noise and ring PLL phase noise
log10(Clipping probability)
Peak-power constraint introduces large gap penalty to capacity (can go around with coding, but too expensive)Still pretty high data rates
NELCO FR4
50
Multi-level: Offset and jitter are crucial
thermal noise + offset
thermal noise + offset+ jitter
To make better use of available bandwidth, need better circuitsPAM2/PAM4 robust candidate for next generation links
0 2 4 6 8 10 12 14 16 18 200
5
10
15
20
25
30
Dat
a ra
te [G
b/s]
Symbol rate [Gs/s]
PAM16
PAM8
PAM4
PAM2
0 2 4 6 8 10 12 14 16 18 200
5
10
15
20
25
30
Symbol rate [Gs/s]
Dat
a ra
te [G
b/s]
PAM2
PAM4
PAM8
0 2 4 6 8 10 12 14 16 18 200
5
10
15
20
25
30
35
40
45
Dat
a ra
te [G
b/s]
PAM4
PAM16
PAM8
PAM2
Symbol rate [Gs/s]
thermal noise
26
51
Full ISI compensation too costly
0 2 4 6 8 10 12 14 160
2
4
6
8
10
12
14
16
18
20
Dat
a ra
te [G
b/s]
Symbol rate [Gs/s]
PAM16PAM4
PAM2PAM8
0 2 4 6 8 10 12 14 160
2
4
6
8
10
12
14
16
18
20
Symbol rate [Gs/s]
Dat
a ra
te [G
b/s]
PAM8
PAM4
PAM2
0 2 4 6 8 10 12 14 160
2
4
6
8
10
12
14
16
18
20
Symbol rate [Gs/s]
Dat
a ra
te [G
b/s]
PAM2
PAM4
PAM8
thermal noisethermal noise + offset
thermal noise + offset+ jitter
Today’s links cannot afford to compensate all ISILimits today’s maximum achievable data rates
52
ConclusionsBackplane links limited by the channelISI is large in baseband links
Can’t completely compensate(At least not with reasonable area/power)
Residual ISI also increases CDR jitterGenerally have low BER requirements
Accurate noise statistic important Many of large noise source are bounded
Power constrained transmitterPAM4 and PAM2 with simple DFE are attractive solutions
Still, capacity of these links is very bigSmart multi-tone?