Optical Interconnect Project Phase 2 Status Update Brice Achkir/ Cisco M.Immonen/ TTM Feb. 28 th, 2015 Member Meeting ** X ** Y 1 Definition Stage.

Optical Interconnect Project

Phase 2 Status UpdateBrice Achkir/ Cisco M.Immonen/ TTM

Feb. 28th, 2015

Member Meeting ** X ** Y1

Definition Stage

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Outline

• Status update • Baseline proposal – Phase 2 demonstrator

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Status Update – 1

• Regular meetings every 2-3 wks• Discussion to confirm suppliers/ resources for all needs

• Confirmed: Design, board fab, waveguide materials & fab, optical connectors, electrical connectors, optical TX/RX, logic + Serdes, testing

• Missing/Gaps: -- (none ?)

• Team feels we are ready to move project into design stage, Seagate team/ Richard Pitwon volunteered for layout and Cisco for the overall signal and Power Integrity

• Draft Functional requirements outline – 10-11’2014

• HW schematics, PCB layout, optical – 2-3’2015

• Move to implementation – Q2/2015

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©HDP User Group International, Inc.

Status Update – 2

• New members signed • Trent Uehling/ Freescale – logic

• Reichle de Massari – optical connectors

• Motohito Takezaki/ Hakusan – optical connectors

• Marc Verdiell/ Samtec – optical engines

• Huber Suhner

• Wei Zhao/Sabic – optical materials

• Jonathan Plisco/ PolyOne – optical material

• Parallel discussion with European PhoxTrot for potential collaboration around demonstrator• PhoxTrot is large 19 partner univ.+ industry consortium with

target to develop all-optical data center building blocks

• Meeting w/ HDP & PhoxTrot teams and reached agreement to collaborate

• MOU distributed for HDP team members, Partially approved to go green with collaboration

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Full view of the proposed model

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Optical Interconnection Model

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Terminology1. Chip-to-Waveguide Connector2. On-Card Link3. Card-to-Backplane Connector4. Card-to-Card Link5. Chip-to-Chip/Module Link

6. Logic Chip (PU, SU, FPGA)7. Optical Transceiver (E/O/E)8. Card (Line Card, Switch Card)9. Backplane/ Midplane10. Chip/Module

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66

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3

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CA

RD

CA

RD

BACKPLANE

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2

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Fiber

Waveguide

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OE2.LC1

RF connectorsRF connectors

More suppliers Upgradabile for newer generation when

available Wider testing possibilites

OE2.BP1

OE2.TD1

OE2.MC1

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Nomenoclature

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To better align and avoid any confuse a new nomenclature is introduced:

OE2 - complete demo platform including chassis and cards

OE2.BP1 - backplane (HDPuG)

OE2.TD1 - Test daughtercard

OE2.MC1 - Mezzanine card with Ultracomm engine and high speed RF connectors

OE2.LC1 - Logic card

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Phase-2 Demonstrator Proposal

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Baseline proposal

HDPuG Phase 2 demonstration platform to comprise: 7U subrack chassis with

integrated fan tray and PSU Electro-optical backplane

accommodating a wide variety of optical waveguide connectors to allow extensive comparative characterisation

Multiple electro-optical test daughtercards to allow all permutations of waveguide and fibre coupling to be assessed

Start: Q1/2015, Ready: Q3/2015

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Phase-2 Demonstrator Proposal, cont.

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Test daughtercard Electro-optical circuit board with embedded MM polymer

optical waveguide layer Provisions for midboard transceiver, high RF electrical

connectors and mezzanine card Pluggable edge card connectors Optional: Flexi-rigid polymer waveguide layer with MT

ferrules or Prizm MTs terminated on “edge tongues”. These can then be housed in pluggable edge connectors as shown to allow direct board to board connectivity

Backplane Electro-optical circuit board with embedded MM polymer optical

waveguide layer Power connectors as shown on bottom Provision for varied optical ferrule receptacles assembled onto

waveguide interfaces for Fibre to Board coupling Provision for backplane receptacles for board-to-board coupling Optional: additional flexi-rigid polymer waveguide layer with

flexible “tongues” to allow direct board to board waveguide coupling

HDPuG Phase 2 Demonstrator Proposal

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Backplane Waveguide and Connector Layout

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Coupling element interfaces with PhoxTrot connectors

Optional midboard interfaces for same waveguide layout

PhoxTrot and HDPuG Phase 2 Crossover

Propose HDPuG Phase 2 demo daughtercards adapted to be used in PhoxTrot PhoxDem_MM1C chassis to plug into PhoxDem1C BP

PhoxDem1C BP form factor can be used for HDPuG Phase 2 backplane PhoxDem1C and HDPuG Phase 2 backplanes should be interchangeable

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Needs & Next Steps

• Team to agree on demonstrator scope, implementation, test functions and testing procedures

• Technology provides to provide specification/ data sheets for the parts to allow design team to outline requirements, form factors, BOM etc.

• Confirm plan, schedule & resources to move I-stage

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Interested Participants

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• Testers, Contributors• Cisco• Alcatel-Lucent• Boeing• Celestica• Compass EOS• Ericsson• Fujitsu• Huawei• IBM• Intel• ITEQ• Juniper• National Semicon.• Nihon Superior• Oracle• Panasonic• Philips• Seagate (XR)

• Design• Seagate (former XR)

• Devices• Ultra-Comm• Samtec

• Connectors – optical

• Optical Interlinks

• FCi• Hakusan• Seagate (XR)

• Connectors – electrical

• Amphenol

• FCi

• Molex

• TE

• PCB fabricators• Flextronics/Multek• TTM• Via System

• Waveguides• Optical Interlinks• Dow Corning• Panasonic• MicroChem• SABIC’s Innovative

Plastics Business (former GE Plastics)

• Laminate materials• Hitachi• Isola• Rogers• Quandong Shenghyi

• Assembly

• Flextronics

2014-09-30

©HDP User Group International, Inc.

Contacts

• Jack Fisher (HDP User Group)

– Project Facilitator

– [email protected]

• Brice Achkir (Cisco, USA)

– Project Leader

– [email protected]

• Marika Immonen (TTM, Finland)

– Project Co-Leader

– [email protected]

• Marshall Andrews (HDP User Group)

– Executive Director

– [email protected]

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