Noise and Power Tradeoffs in CMOS Front Ends

Noise and Power Tradeoffs in Noise and Power Tradeoffs in CMOS Front EndsCMOS Front Ends

Paul O’Connor

VIth International Meeting on Front End Electronics Paul O'Connor BNL May 18, 2006 2

AcknowledgementsAcknowledgements

• Gianluigi De Geronimo• Veljko Radeka• Angelo Dragone• Jean-François Pratte


OutlineOutline

• Fundamental limits• Constrained noise optimization

– power– speed

• Figure of merit– analog– digital

• Architecture choices• Summary


• Charge of one electron ENC ≥ 1 electron rms?

What are the fundamental limits?What are the fundamental limits?


• Uncertainty principle?


2( ),

2 pd

d

p

QE t

C

CQ

E·t ≥ ħ/2

Q ≥ 0.06 e- e.g., Cd=1pF, p=1s


• Thermal fluctuations?


2

2 2Q

d

Q d

kT

C

kTC

e.g., at 300K:

Cd ENC0.1pF 126 e-1 400 10 1260



• Channel thermal noise

m T gg C

,

4 dt opt

T p

kTCENC

(T depends on power and level of inversion)

e.g., T = 1GHz, p = 1s, Cd=1pF

ENCt > 25 e-

21

2 )(14

gdpm

t CCg

kTnaENC



• Low frequency (1/f) noise

e.g., Kf = 10-24J, Cd=1pF

ENCf > 16 e-

222

, 2

ff d g

g

f opt f d

KENC a C C

C

ENC K C


Most systems are power-constrainedMost systems are power-constrained

• particle physics services/cooling/material

• space limited power sources

• security (portable) limited power sources

• imaging power density/cooling


Shaping time is not always a free choiceShaping time is not always a free choice

p may be constrained by– pileup– timing precision– ballistic deficit

– parallel noise (noise corner time constant √RsRpCin2)


How can power be reduced without How can power be reduced without sacrificing performance (SNR, pileup)?sacrificing performance (SNR, pileup)?

• design:– optimize M1 and H(s)

• technology:– scaling impact on noise and dynamic range

• architecture:– multiplexing and digitizing strategy


Input transistor (MInput transistor (M11) optimization) optimization

• Optimize for total (white + 1/f) series noise:– adjust W,L while holding Id and tp constant

• Correct modeling of weak, moderate, and strong inversion (EKV model):– dependence of gm, Cg, on operating point

• Low-frequency noise: – dependence on Lg

– spectral dependence

• Predict result of scaling to new technologiesP. O’Connor, Proc. FEE2003 SnowmassG. De Geronimo, P. O’Connor, TNS52(6),3223 (2005)


1

10

100

1000

10 100 1000 10000

Power in 1st transistor [W]

EN

Co

pt [

rms

ele

ctr

on

]

10 ns100ns1us10us

White + 1/f noise vs. MWhite + 1/f noise vs. M11 power power

1

10

100

1000

10 100 1000 10000

Power in 1st transistor [W]

EN

Co

pt [

r.m

.s.

ele

ctro

n] 0.1pF

1pF10pF

vs. detector capacitancevs. detector capacitance vs. peaking timevs. peaking time

Transistor width optimized for each configuration

p=1s Cd=1pF


0

20

40

60

80

100

120

10 100 1000 10000

Power Pd [W]

EN

Co

pt [

r.m

.s. e

lect

ron

s]

Noise models comparedNoise models compared

10-5

10-4

10-3

10-2

0

20

40

60

80

100

120

Pch

Nch

ENC

opt

[r.m

.s. e

lect

rons

]

Power Pd [W]

10-5

10-4

10-3

10-2

0

20

40

60

80

100

120

Pch

Nch

ENC

opt

[r.m

.s. e

lect

rons

]EN

Cop

t[r.

m.s

. ele

ctro

ns]

Power Pd [W]

TSMC 0.25m processCd = 1pFp = 1s

NchPch

More accurate 1/f noise modelSimple 1/f noise model


Choice of filter function Choice of filter function

Shaper Characteristics

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

9th Order (CPX)

4th Order (RC3-CR)5th Order (CPX)

2nd Order (RC-CR)

No

rma

lize

d A

mp

litu

de

Time / Pulse Width

Equal 1% Pulse Width

hu(t) p

w

t

1%

hu(t) p

w

t

1%


0.0 0.1 0.2 0.3 0.4 0.50.6

0.7

0.8

0.9

1.0

5th Order (CPX)

Equal 1% Pulse WidthUniform Charge Collection

4th Order (RC3-CR)

9th Order (CPX)

2nd Order (RC-CR)

No

rma

lize

d A

mp

litu

de

Charge Collection Time / Pulse Width

BALLISTIC DEFICIT

High-order shaper improvementsHigh-order shaper improvements

10 100 1000

200

400

600

800

9th Order(CPX)

Dominant Series Noise

4th Order(RC3-CR)

5th Order(CPX)

2ndOrder (RC-CR)

Power(input MOSFET) [µW]

TSMC 0.25µm CMOSInput PMOSContinuous ResetC

d= 1pF, I = 1nA

Pulse Width 100ns

EN

C (

r.m

.s. e

- )

Noise vs. Power

10 100 1000

200

400

600

800

9th Order(CPX)


4th Order(RC3-CR)

5th Order(CPX)

2ndOrder (RC-CR)



d= 1pF, I = 1nA

Pulse Width 100ns

EN

C (

r.m

.s. e

- )

10 100 1000

200

400

600

800

9th Order(CPX)


4th Order(RC3-CR)

5th Order(CPX)

2ndOrder (RC-CR)



d= 1pF, I = 1nA

Pulse Width 100ns

EN

C (

r.m

.s. e

- )

Noise vs. Power0.25m CMOSCd=1pFw=100ns

• add shaper poles

• improve symmetry

• longer p for same w, lower noise

• small increase in shaper power

• power does more good here than in M1!

• area penalty


Figure of merit for charge amplifiersFigure of merit for charge amplifiers

• Expresses the power cost of achieving SNR and speed

• Can be applied to front ends in any technology• Corresponds to figure of merit for analog-digital

converters:

• Provides guidance for low-power system design

max /d p

CSAQ

PFOM

Q

max /d p

CSAQ

PFOM

Q

2d

ADC ENOBs

PFOM

f


Figure of merit for charge amplifiers Figure of merit for charge amplifiers ((FOMFOMCSACSA) vs. detector capacitance) vs. detector capacitance

0.1 0.2 0.5 1.0 2.0 5.0 10.0 20.0 50.0

1

e-0

31

e

-02

1

e-0

11

e

+0

01

e

+0

1

C, pF

FO

MC

SA, p

J

0.180.250.350.50.81.2hybrid

1.5pJ

Medipix-2Llopart et al., TNS49(2002)2279

PSI-46Erdmannt et al., NIMA549(2005)153


Figure of merit for ADCs (Figure of merit for ADCs (FOMFOMADCADC) vs. ) vs.

dynamic rangedynamic range

Dynamic Range

1 e+02 1 e+03 1 e+04 1 e+05 1 e+06

0.1

1.0

10.0

100.

0

FO

MA

DC, p

J

ALICE-TRDADITINatSemiLT

2.8pJ


Architecture choicesArchitecture choices

• Digital waveform recording of every channel requires ADC to have:– same SNR as charge amplifier – sampling frequency 2X – 20X higher than analog bandwidth

• Guarantees PADC >> PCSA

• Better architecture: capture and buffer the analog information on the FEE ASIC, then steer samples to the ADC

• Switched capacitors or peak detectors can serve as the sampling cells

• Use analog buffers (memory) with simultaneous READ/WRITE to avoid deadtime


Analog vs. digital feature extractionAnalog vs. digital feature extraction

p

Epk

trigger thr. cross

event-to-event time

digital waveform record


sampling onswitched caps

sampling onpeak-detect caps

unbuffered bufferedAnalog storage and buffering schemesAnalog storage and buffering schemes

sample mux

mux


EXAMPLES


• Use FOMCSA ~ 1pJ, calculate most quantities of interest.

• Given Pmax, rate r, what is achievable SNR?

– e.g. P=1mW, r=100kHz, SNR ~ 103

• What power needed to get timing accuracy t?

– e.g. t=2ns, P ~ 50W

Rule-of-thumb estimatesRule-of-thumb estimates

10CSA

PSNR

FOM r

t

CSApVt

FOMP

SNRdtdV ;~

/


TPC Chamber

Double-GEM (gain ~ 500)

Anode PlaneAnode Plane

Pads~7300

Pads~7300

Front-End Electronics

~7300 channels

Front-End Electronics

~7300 channels

Gianluigi De GeronimoJack FriedAnand KandasamyVeljko RadekaBo Yu

Readout of a TPC using analog bufferingReadout of a TPC using analog buffering

Mini-TPC with GEM readout for LEGS experiment at BNL

continuous reset

2nd ordershaper

mux1PD

peak detector

threshold

timing detector

neighbors

mux2TDramp

flagcontinuous reset

2nd ordershaper

mux1PD

peak detector

threshold

timing detector

neighbors

mux2TDramp

flagASIC


TPC Digitization PowerTPC Digitization Power• Npads 8000• Ntimeslices 500• Nvoxels 4x106

• Digitization Energy (12 bit resolution):– 10-12J/bit * 212 * Nvoxels = 16 mJ

• Power (FADC):– 16mJ / 7s = 2000W (250 mW/chan)

• Power (buffer and readout at 2 kHz trigger rate):– 16mJ / 500s = 30W ( 4 mW/chan)

• Compare with 0.75mW/chan for amplifier + 0.6mW/chan for PD + TAC.• With sparsified readout of only occupied channels buffered in PD: PADC ~ 0.6W (75 W/chan).


Biparametric spectrum (signature)Biparametric spectrum (signature)

Channel no.

241Am on CZT

risetimeenergy


All data

Exclude piled-up region

TOT measurement for pileup rejectionTOT measurement for pileup rejection

0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2

10-4

10-3

10-2

10-1

100 Pulse Height Spectrum

PD Amplitude [V]

Nor

mal

ized

Cou

nts

Before correction

After correction

Monochromatic 8keV X-rays on Si pad detector


SummarySummary

• Noise is limited by available power and by the 1/f properties of the technology.

• In addition to optimizing the first transistor, choice of shaping function is also important in noise optimization.

• High-order shapers improve the power/noise tradeoff, and also improve pileup and charge collection performance.

• An empirical figure of merit for charge amplifiers, analogous to that for ADCs, can be used to guide design choices.

• Reducing the number of analog-to-digital conversions (where possible) improves noise by allowing power to be allocated to the front end.


Noise and Power Tradeoffs in CMOS Front Ends

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