NMOS processingAndScaling

1

NMOS Fabrication

2

FabricationThe process used that creates the devices/wires.• Look at how to create:

– Working transistors• ndiff, pdiff, wells, poly, transistors, threshold adjust

implants– Wires

• contacts, metal1, via, metal2

Fabrication is pretty complex.• Give a brief overview of the process, for

background.• Want to understand origin of layout rules / process

parameters– The abstractions of the process for the designers (us).

3

Semiconductor Review

• Create by doping a pure silicon crystal– Diffuse impurity into crystal lattice– Changes the concentration of carriers

• Electrons• Holes

– More doping -> more carriers available

• n-type semiconductor (n or n+)– Majority carrier: electrons– Typical impurity: Arsenic (Column V)

• p-type semiconductor (p or p+)– Majority carrier: holes– Typical impurity: Boron (Column III)

nn+

pp+

4

Other key working materials

• Insulator - Silicon Dioxide (SiO2)– Used to insulate transistor gates (thin oxide)– Used to insulate layers of wires (field oxide)– Can be grown on Silicon or Chemically Deposited

• Polysilicon - polycrystalline silicon– Key material for transistor gates– Also used for short wires– Added by chemical deposition

• Metal - Aluminum (…and more recently Copper)– Used for wires– Multiple layers common– Added by vapor deposition or “sputtering”

5

A transistor gate is formed wherever polysilicon crosses diffusion (semiconductor) with oxide between these layers.

When a Transistor Gate is formed?

Buried contact

When there is no oxide between polysilicon and diffusion.

Here two conducting materials contact one another.

No transistor is formed

6

Power Line

The 5v and 0v power line are implemented by in metal because of its very low resistance.

Contact Cut

In order to allow metal and diffusion to contact, metal is holed downed to the diffusion level and is called contact cut.

7

NMOS Processing (Fabrication)

NMOS Inverter with depletion load transistor

Our objective is to fabricate this Inverter

Vin

5 V

Dep

Vout

Enh

0V

8

NMOS Processing (Fabrication) [Cont]

Diffusion regions surrounding the gate areas are doped with n+ impurity and [Source and drain]

… Transistor is formedVin

5 V

Dep

Vout

Enh

0V

9

NMOS Processing (Fabrication) [Cont]

What should we do?

We need to alter threshold voltage……

Method used depletion implant

Vin

5 V

Dep

Vout

Enh

0V

10

NMOS Processing (Fabrication) [Cont]

PolySi cross Diffusion YES

NO

YES

Transistor Formed

Buried contact

Vin

5 V

Dep

Vout

Enh

0V

11

NMOS Processing (Fabrication) [Cont]

Contact cutVin

5 V

Dep

Vout

Enh

0V

12

NMOS Processing (Fabrication) [Cont]

P-type

Starting Material:

Lightly doped p-type Si substrate

Mask-1: defines all diffusion regions (active areas)- drain

- source

- gate

- any diffusion lines used to interconnect ckts.

Areas external to the active are covered with isolating oxide

Vin

5 V

Dep

Vout

Enh

0V

13

NMOS Processing (Fabrication) [Cont]

P-type

Mask-2:defines depletion implant regions

here n-type implantation used

P-type

Vin

5 V

Dep

Vout

Enh

0V

14

NMOS Processing (Fabrication) [Cont]

P-type

Entire wafer is covered with a thin layer of Oxide

P-type

Mask-3: Define where Oxide is to be removed

P-type

Vin

5 V

Dep

Vout

Enh

0V

15

NMOS Processing (Fabrication) [Cont]

P-type

Covered with PolySi

P-type

Vin

5 V

Dep

Vout

Enh

0V

16

NMOS Processing (Fabrication) [Cont]

P-type

Mask-4 Defines area where PolySi is to be remain all gate areas all PolySi to diffusion connection all PolySi interconnection

P-type

Vin

5 V

Dep

Vout

Enh

0V

17

NMOS Processing (Fabrication) [Cont]

P-type

An unmask n+ diffusion now defines all source and drain regions

P-type

Vin

5 V

Dep

Vout

Enh

0V

18

NMOS Processing (Fabrication) [Cont]

P-type

Wafer is covered with insulating Oxide which will insulate PolySi and diffusion from metal

P-type

Wafer is heated to provide smooth surface and to drive-in the n+ region

Vin

5 V

Dep

Vout

Enh

0V

19

NMOS Processing (Fabrication) [Cont]

P-type

Mask-5 define contact cut where Oxide is to be removed

P-type

Vin

5 V

Dep

Vout

Enh

0V

20

NMOS Processing (Fabrication) [Cont]

Covered with Al

P-type

P-type

Vin

5 V

Dep

Vout

Enh

0V

21

NMOS Processing (Fabrication) [Cont]

Mask-6 specifies regions where Al is to be remain

P-type

P-type

Vin

5 V

Dep

Vout

Enh

0V

22

NMOS Processing (Fabrication) [Cont]

An Oxide overlay is grown to protect the surface

P-type

P-type

Vin

5 V

Dep

Vout

Enh

0V

23

NMOS Processing (Fabrication) [Cont]

P-type

Mask-7 defines the area where overlay is etched away to allow the contact between Al of the input and output pads of the Chip and external circuitry.

Vin

5 V

Dep

Vout

Enh

0V

24

Scaling

Book: Linda’s Book

Page: 56-57

25

Objectives

• Evolution of smaller line widths, feature size and higher packing density.

• So need to understand the effects of scaling.• Characteristics of Micro-electronic technology

– Minimum feature size.– Number of gates on a chip.– Power dissipation.– Maximum Operational frequency– Die size– Production cost.

26

• Improved by shrinking the dimensions of transistors, interconnections and separation between features

• And by adjusting the doping levels and power voltages.

• In practice all dimensions are expressed in terms of λ.

• A value is assigned prior to manufacture.• Advantage of this approach: design rules not

become out dated.

27

Scaling

•The effects of scaling are most easily considered by assuming that all geometric dimensions (horizontal and Vertical) and voltages are reduced by a constant factor “a”.

28

a

WW

orscale_fact

old_width width new

a

DD thicknessnew

29

a

LL length new

a

VpVp tagesupply vol new

30

a

VteVte thresholddevicet enhancemen new

31

Saturation Current

a

IVgsV

DL

WI t

n

2)(2

32

• Current per transistor decreases by a factor “a”.

• a factor “a2” more scaled devices can be placed on a similar sized chip.

• The current drawn from the supply increases by a factor “a”.

• The power supplied to a similar sized chip is unaltered by scaling

33

Capacitor

Circuit capacitances are reduced by factor a

a

C

D

WLC

C

34

Gate delay

• gate delay '

• The gate delay is decreased by a factor a.

'''

LWoutC

35

Gate Power

• gate power ' = =

• Gate power is reduced by a factor a2.

IpV 2a

IVp

36

Speed Power Product

• Speed power product ' =

=

Speed power product reduces by a factor a3.

'''_ IVpdelaygate

3

__

a

productpowerspeed

37

• Apart from the increase in current density on the chip, the other effects of reducing features and voltages are advantageous.

• However, another unwanted effect arises when considering the delay down lines interconnecting gates. Here, the length does not scale as the chip is assumed to be of similar area. Hence, the line length is constant.

38

Line Capacitance

• C i ' = = Ci

• Capacitance remains same.

'

'

D

LW

39

Line Resistance

• Ri

• T ' new conductor depth.

• Ri = a2 Ri

• Line resistance scale up by a factor a2

''TW

L

40

The delay down an interconnection line is proportional to Ri ' C ' i and thus scale up by a factor a2.

Delays in polysilicon and diffusion becomes unacceptably large and delay down metal lines is no longer negligible. This suggest that it will not be sensible to scale all the features an identical factor.

41