NCP1654 - Power Factor Controller for Compact and Robust ...

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© Semiconductor Components Industries, LLC, 2016

August, 2021 − Rev. 71 Publication Order Number:

NCP1654/D

Power Factor Controller forCompact and Robust,Continuous ConductionMode Pre-Converters

NCP1654The NCP1654 is a controller for Continuous Conduction Mode

(CCM) Power Factor Correction step−up pre−converters. It controlsthe power switch conduction time (PWM) in a fixed frequency modeand in dependence on the instantaneous coil current.

Housed in a SO8 package, the circuit minimizes the number ofexternal components and drastically simplifies the PFCimplementation. It also integrates high safety protection features thatmake the NCP1654 a driver for robust and compact PFC stages like aneffective input power runaway clamping circuitry.

Features• IEC61000−3−2 Compliant

• Average Current Continuous Conduction Mode

• Fast Transient Response

• Very Few External Components

• Very Low Startup Currents (< 75 �A)

• Very Low Shutdown Currents (< 400 �A)

• Low Operating Consumption

• ±1.5 A Totem Pole Gate Drive

• Accurate Fully Integrated 65/133/200 kHz Oscillator

• Latching PWM for cycle−by−cycle Duty−Cycle Control

• Internally Trimmed Internal Reference

• Undervoltage Lockout with Hysteresis

• Soft−Start for Smoothly Startup Operation

• Shutdown Function

• Pin to Pin Compatible with Industry Standard

• This is a Pb−Free Device

Safety Features• Inrush Currents Detection

• Overvoltage Protection

• Undervoltage Detection for Open Loop Detection or Shutdown

• Brown−Out Detection

• Soft−Start

• Accurate Overcurrent Limitation

• Overpower Limitation

Typical Applications• Flat TVs, PC Desktops

• AC Adapters

• White Goods, other Off−line SMPS

PIN CONNECTIONS

MARKING DIAGRAM

SO−8D SUFFIXCASE 751

1Ground 8 Driver

2VM

3CS

4Brown−Out

7 VCC

6 Feedback

5 Vcontrol

(Top View)

xx = 65, 133 or 200A = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package

1

8

54BxxALYW

�

1

8

SO−8(Pb−Free)

Device Package Shipping†

ORDERING INFORMATION

NCP1654BD65R2G 2500 / Tape & Reel

†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationBrochure, BRD8011/D.

SO−8(Pb−Free)


SO−8(Pb−Free)


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MAXIMUM RATINGS TABLE

Symbol Pin Rating Value Unit

DRV 8 Output Drive Capability − SourceOutput Drive Capability − Sink

−1.5+1.5

A

VCC 7 Power Supply Voltage, VCC pin, continuous voltage −0.3, +20 V

7 Transient Power Supply Voltage, duration < 10 ms, IVCC < 10 mA +25 V

Vin 2, 3, 4, 5, 6 Input Voltage −0.3, +10 V

PD(SO)R�JA(SO)

Power Dissipation and Thermal CharacteristicsD suffix, Plastic Package, Case 751

Maximum Power Dissipation @ TA = 70°CThermal Resistance Junction−to−Air

450178

mW°C/W

TJ Operating Junction Temperature Range −40 to +125 °C

TJmax Maximum Junction Temperature 150 °C

TSmax Storage Temperature Range −65 to +150 °C

TLmax Lead Temperature (Soldering, 10 s) 300 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. This device series contains ESD protection and exceeds the following tests:

Human Body Model (HBM) 2000 V per JEDEC standard JESD22, Method A114EMachine Model (MM) 200 V (except pin#7 which complies 150 V) per JEDEC standard JESD22, Method A115A.

2. This device contains Latch−up Protection and exceeds ±100 mA per JEDEC Standard JESD78.

TYPICAL ELECTRICAL CHARACTERISTICS TABLE (VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)

Symbol Rating Min Typ Max Unit

GATE DRIVE SECTION

ROH Source Resistance @ Isource = 100 mA − 9.0 20 �

ROL Sink Resistance @ Isink = −100 mA − 6.6 18 �

Tr Gate Drive Voltage Rise Time from 1.5 V to 13.5 V (CL = 2.2 nF) − 60 − ns

Tf Gate Drive Voltage Fall Time from 13.5 V to 1.5 V (CL = 2.2 nF) − 40 − ns

REGULATION BLOCK

VREF Voltage Reference 2.425 2.5 2.575 V

IEA Error Amplifier Current Capability − ±28 − �A

GEA Error Amplifier Gain 100 200 300 �S

IBpin6 Pin 6 Bias Current @ VFB = VREF −500 − 500 nA

VcontrolVcontrol(max)Vcontrol(min)�Vcontrol

Pin5 VoltageMaximum Control Voltage @ VFB = 2 VMinimum Control Voltage @ VFB = 3 V�Vcontrol = Vcontrol(max) − Vcontrol(min)

−−

2.7

3.60.63.0

−−

3.3

V

VOUTL / VREF Ratio (VOUT Low Detect Thresold / VREF) 94 95 96 %

HOUTL / VREF Ratio (VOUT Low Detect Hysteresis / VREF) − 0.5 − %

IBOOST Pin 5 Source Current when (VOUT Low Detect) is activated 190 228 260 �A

CURRENT SENSE BLOCK

VS Current Sense Pin Offset Voltage, (ICS = 100 �A) − 10 − mV

IS(OCP) Overcurrent Protection Threshold 185 200 215 �A

POWER LIMITATION BLOCK

ICS x VBO Overpower Limitation Threshold − 200 − �VA

ICS(OPL1)ICS(OPL2)

Overpower Current Threshold (VBO = 0.9 V, VM = 3 V)Overpower Current Threshold (VBO = 2.67 V, VM = 3 V)

18662

22275

308110

�A

PWM BLOCK

Dcycle Duty Cycle Range − 0−97 − %


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TYPICAL ELECTRICAL CHARACTERISTICS TABLE (VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)

Symbol UnitMaxTypMinRating

OSCILLATOR / RAMP GENERATOR BLOCK

fsw Switching Frequency65 kHz133 kHz200 kHz

58120180

65133200

72146220

kHz

BROWN−OUT DETECTION BLOCK

VBOH Brown−Out Voltage Threshold (rising) 1.22 1.30 1.38 V

VBOL Brown−Out Voltage Threshold (falling) 0.65 0.7 0.75 V

IIB Pin 4 Input Bias Current @ VBO = 1 V −500 − 500 nA

CURRENT MODULATION BLOCK

IM1IM2

IM3IM4

Multiplier Output Current (Vcontrol = Vcontrol(max), VBO = 0.9 V, ICS = 25 �A)Multiplier Output Current (Vcontrol = Vcontrol(max), VBO = 0.9 V, ICS = 75 �A)

(@ 0 � 125°C)(@ −40 � 125°C)

Multiplier Output Current (Vcontrol = Vcontrol(min) + 0.2 V, VBO = 0.9 V, ICS = 25 �AMultiplier Output Current (Vcontrol = Vcontrol(min) + 0.2 V, VBO = 0.9 V, ICS = 75 �A

−

1.51.5−−

1.9

4.74.728.184.4

−

8.89.8−−

�A

OVERVOLTAGE PROTECTION

VOVP / VREF Ratio (Overvoltage Threshold / VREF) 103 105 107 %

TOVP Propagation Delay (VFB – 107% VREF) to Drive Low − 500 − ns

UNDERVOLTAGE PROTECTION / SHUTDOWN

VUVP(on)/VREF UVP Activate Threshold Ratio (TJ = 0°C to +105°C) 4 8 12 %

VUVP(off)/VREF UVP Deactivate Threshold Ratio (TJ = 0°C to +105°C) 6 12 18 %

VUVP(H) UVP Lockout Hysteresis − 4 − %

TUVP Propagation Delay (VFB < 8% VREF) to Drive Low − 500 − ns

THERMAL SHUTDOWN

TSD Thermal Shutdown Threshold 150 − − °C

HSD Thermal Shutdown Hysteresis − 30 − °C

VCC UNDERVOLTAGE LOCKOUT SECTION

VCC(on) Start−Up Threshold (Undervoltage Lockout Threshold, VCC rising) 9.6 10.5 11.4 V

VCC(off) Disable Voltage after Turn−On (Undervoltage Lockout Threshold, VCC falling) 8.25 9.0 9.75 V

VCC(H) Undervoltage Lockout Hysteresis 1.0 1.5 − V

DEVICE CONSUMPTION

ISTUPICC1ICC2

ISTDN

Power Supply Current:Start−Up (@ VCC = 9.4 V)Operating (@ VCC = 15 V, no load, no switching)Operating (@ VCC = 15 V, no load, switching)Shutdown Mode (@ VCC = 15 V and VFB = 0 V)

−−−−

−3.74.7300

755.06.0400

�AmAmA�A

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit

characterization has been performed.

NOTE: IM �Ics � VBO

4 � �Vcontrol � Vcontrol(min)�


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DETAILED PIN DESCRIPTIONS

Pin Sym-bol

Name Function

1 GND Ground −

2 Vin MultiplierVoltage

This pin provides a voltage VM for the PFC duty cycle modulation. The input impedance ofthe PFC circuits is proportional to the resistor RM externally connected to this pin. The deviceoperates in average current mode if an external capacitor CM is connected to the pin.Otherwise, it operates in peak current mode.

3 CS Current SenseInput

This pin sources a current ICS which is proportional to the inductor current IL. The sensecurrent ICS is for overcurrent protection (OCP), overpower limitation (OPL) and PFC dutycycle modulation. When ICS goes above 200 �A, OCP is activated and the Drive Output isdisabled.

4 VBO Brown−Out / In Connect a resistor network among the rectified input voltage, BO pin, and ground. Andconnect a capacitor between BO pin and ground. BO pin detects a voltage signalproportional to the average input voltage.When VBO goes below VBOL, the circuit that detects too low input voltage conditions(brown−out), turns off the output driver and keeps it in low state until VBO exceeds VBOH.This signal which is proportional to the RMS input voltage Vac is also for overpower limitation(OPL) and PFC duty cycle modulation.

5 Vcontrol Control Voltage/ Soft−Start

The voltage of this pin Vcontrol directly controls the input impedance. This pin is connected toexternal type−2 compensation components to limit the Vcontrol bandwidth typically below 20Hz to achieve near unity power factor.The device provides no output when Vcontrol < Vcontrol(min). When it starts operation, thepower increases slowly (soft−start).

6 VFB Feed−Back /Shutdown

This pin receives a feedback signal VFB that is proportional to the PFC circuits outputvoltage. This information is used for both the output regulation, the overvoltage protection(OVP), and output undervoltage protection (UVP) to protect the system from damage atfeedback abnormal situation.When VFB goes above 105% VREF, OVP is activated and the Drive Output is disabled.When VFB goes below 8% VREF, the device enters a low−consumption shutdown mode.

7 VCC Supply Voltage This pin is the positive supply of the IC. The circuit typically starts to operate when VCCexceeds 10.5 V and turns off when VCC goes below 9 V. After start−up, the operating rangeis 9 V up to 20 V.

8 DRV Drive Output The high current capability of the totem pole gate drive (±1.5 A) makes it suitable toeffectively drive high gate charge power MOSFET.


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-+

-+

105% Vref

8% Vref with 4% VrefHysteresis

UVP

OVP

UndervoltageLock−Out

ReferenceBlock

Bias Block

Iref Vdd

Vref

Vcc

DRV

GND

OutputBuffer 8

7

1

UVL-O

B-O

+- OTA

±28 �AVcontrolVref

OPL Vdd

Off+-

95% Vref

6

5

QR

S

Vdd

+-

Current Mirror

BO

4

BO

ThermalShutdown

+-Vref

+ -

Vm

Figure 1. Functional Block Diagram

Ics > 200 �A

Ics

Ics

C-S

3

Vd-d

Vd-d

C1 S1

Divi-sion 2

65/133/200 kHzOscillator

Vref/10%Vref

Vd-d

Iref

+

Im = (Ics*Vbo) / (4*(Vcontrol − Vcontrol(min))

Ics*Vbo > 200 �VA

Q

R

R S

PW-M

Latc-h

O-L

OPL

OCP

IcsVbo

Faul-t

OVPVboH / VboLVboH = 1.3 V, VboL = 0.7 V

FB

200 �A

Vout Low Detect

Vin

++

−

IN

RM

CM

OutputVoltage(VOUT)

EMIFilter

ACInput

IinL IL

ILRSENSE

Cbulk

RZ

CP

CZ

RCS

RboU

RfbL

RfbU

CBO

RboL

Vcontrol(min)

+

Cfilter

SoftStart

OL

Vramp

UVP B-O


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TYPICAL CHARACTERISTICS

Figure 2. Gate Drive Resistance vs.Temperature

Figure 3. Reference Voltage vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

10075 12550250−25−500

2

4

6

8

10

1251007550250−25−502.40

2.45

2.50

2.55

2.60

Figure 4. Source Current Capability of theError Amplifier vs. Temperature

Figure 5. Sink Current Capability of the ErrorAmplifier vs. Temperature


10075 12550250−25−5020

22

24

26

28

30

32

−32

−30

−28

−26

−24

−22

−20

Figure 6. Error Amplifier Gain vs. Temperature Figure 7. Feedback Pin Current vs.Temperature (@Vfb = VREF)


100

150

200

250

300

−150

−100

−50

0

50

100

150

RO

H &

RO

L, G

AT

E D

RIV

E R

ES

IS-

TAN

CE

(�

)

VR

EF (

V)

I EA

_sou

rce

(A)

I EA

_sin

k (A

)

GE

A (�S

)

I Bpi

n6 (

nA)

ROH

ROL

10075 12550250−25−50

1251007550250−25−50 10075 12550250−25−50


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Figure 8. Vcontrol Maximum Voltage vs.Temperature

Figure 9. Vcontrol Maximum Swing (�VCONTROL)vs. Temperature


10075 12550250−25−503.3

3.4

3.5

3.6

3.7

3.8

3.9

4.0

10075 1255025

0−25

−502.7

2.8

2.9

3.0

3.1

3.2

3.3

Figure 10. Ratio (VOUT Low Detect Threshold /VREF) vs. Temperature

Figure 11. Pin 5 Source Current when (VOUTLow Detect) is Activated vs. Temperature


1007550 125250−25−5094.3

94.4

94.5

94.6

94.8

94.9

95.0

95.1

190

200

210

220

230

240

250

260

Figure 12. Over−Current Protection Thresholdvs. Temperature

Figure 13. Over−Power Current Threshold(@VBO = 0.9 V & Vm = 3 V) vs. Temperature


185

190

195

200

205

210

215

186

206

226

246

266

286

306

VC

ON

TR

OL(

max

) (V

)

�V

CO

NT

RO

L (V

)

Vou

tL /

VR

EF (

%)

I Boo

st (�A

)

I S(O

CP

) (�A

)

I CS

(OP

L1) (�A

)

94.7

10075 12550250−25−50

10075 1255025

0−25

−50 0−25 10075 1255025−50


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Figure 14. Over−Power Current Threshold(@VBO = 2.67 V & Vm = 3 V) vs. Temperature

Figure 15. Maximum Duty Cycle vs.Temperature


1251007550250−25−5060

70

80

90

100

110

95

96

97

98

99

100

Figure 16. Switching Frequency vs.Temperature (65 kHz Version)


TJ, JUNCTION TEMPERATURE (°C)

10075 12550250−25−5058

60

62

64

66

68

70

72


I CS

(OP

L2) (�A

)

MA

XIM

UM

DU

TY

CY

CLE

(%

)

f SW

(kH

z)

1251007550250−25−50


10075 12550250−25−50126

128

130

132

134

136

138

140

f SW

(kH

z)


10075 12550250−25−50180

185

190

195

200

205

210

f SW

(kH

z)


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Figure 19. Brown−Out Voltage Threshold(Rising) vs. Temperature

Figure 20. Brown−Out Voltage Threshold(Falling) vs. Temperature



10075 12550250−25−502.58

2.60

2.62

2.64

2.66

Figure 21. Multiplier Output Current (Vcontrol =VCONTROL(max), Vbo = 0.9 V, ICS = 75 �A) vs.

Temperature

Figure 22. Over Voltage Threshold vs.Temperature


10075 12550250−25−500

2

4

6

10

12

14

16

Figure 23. Ratio (Over Voltage Threshold /VREF) vs. Temperature

Figure 24. UVP Activate and DeactivateThreshold Ratio vs. Temperature

VO

VP (

V)

VU

VP

(on)

/ V

RE

F a

nd V

UV

P(o

ff) /

VR

EF (

%)

10075 12550250−25−50103

104

105

106

VO

VP /

VR

EF (

%)

107

8


2.5

3.5

4.5

5.5

6.5

7.5

I m2

(�A

)

1251007550250−25−50


0.65

0.70

0.75

VB

OL

(L)

10075 12550250−25−50


10075 12550250−25−501.20

1.25

1.30

1.35

1.40

VB

OH

(V

)


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Figure 25. VCC Start−Up Threshold (VCCRising) vs. Temperature

Figure 26. VCC Disable Voltage after Turn−On(VCC Falling) vs. Temperature



1251007550250−25−500

10

20

30

40

50

1251007550250−25−50200

250

300

350

400

Figure 27. VCC UVLO Hysteresis vs.Temperature


I ST

UP (�A

)

I ST

DN

(�A

)

OP

ER

AT

ING

CU

RR

EN

T (

mA

)

1251007550250−25−500

1

2

3

4

ICC2, No Load, Switching

ICC1, No Load, No Switching

Figure 28. Supply Current in Startup Mode vs.Temperature

Figure 29. Supply Current in Shutdown Modevs. Temperature

Figure 30. Operating Supply Current vs.Temperature


1251007550250−25−501.0

1.2

1.4

1.6

1.8

2.0

VC

C(H

) (V

)


10075 12550250−25−508.3

8.5

8.7

8.9

9.1

9.3

9.5

9.7

VC

C(o

ff) (

V)


10075 12550250−25−509.6

9.8

10.0

10.4

10.6

11.0

11.2

11.4

VC

C(o

n) (

V)

10.2

10.8


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Detailed Operating Description

IntroductionThe NCP1654 is a PFC driver designed to operate in fixed

frequency, continuous conduction mode. The fixedfrequency operation eases the compliance with EMIstandard and the limitation of the possible radiated noise thatmay pollute surrounding systems. In addition, continuousconduction operation reduces the application di/dt and theirresulting interference. More generally, the NCP1654 is anideal candidate in systems where cost−effectiveness,reliability and high power factor are the key parameters. Itincorporates all the necessary features to build a compactand rugged PFC stage:• Compactness and Flexibility: housed in a SO8

package, the NCP1654 requires a minimum of externalcomponents. In particular, the circuit scheme simplifiesthe PFC stage design and eliminates the need for anyinput voltage sensing. In addition, the circuit offerssome functions like the Brown−Out or the true powerlimiting that enable the optimizations of the PFCdesign,

• Low Consumption and Shutdown Capability: theNCP1654 is optimized to exhibit consumption as smallas possible in all operation modes. The consumedcurrent is particularly reduced during the start−up phaseand in shutdown mode so that the PFC stage powerlosses are extremely minimized when the circuit isdisabled. This feature helps meet the more stringentstand−by low power specifications. Just ground theFeed−back pin to force the NCP1654 in shutdownmode,

• Safety Protections: the NCP1654 permanently monitorsthe output voltage, the coil current and the dietemperature to protect the system from possibleover−stresses. Integrated protections (Overvoltageprotection, coil current limitation, thermal shutdown...)make the PFC stage extremely robust and reliable:− Maximum Current Limit: the circuit permanently

senses the coil current and immediately turns off thepower switch if it is higher than the set current limit.The NCP1654 also prevents any turn on of the powerswitch as long as the coil current is not below itsmaximum permissible level. This feature protects theMOSFET from possible excessive stress that couldresult from the switching of a current higher than theone the power switch is dimensioned for. Inparticular, this scheme effectively protects the PFCstage during the start−up phase when large in−rushcurrents charge the output capacitor.

− Undervoltage Protection for Open Loop Protection orShut−down: the circuit detects when the feed−back

voltage goes below than about 8% of the regulationlevel. In this case, the circuit turns off and itsconsumption drops to a very low value. This featureprotects the PFC stage from starting operation in caseof low AC line conditions or in case of a failure in thefeed−back network (i.e. bad connection).

− Fast Transient Response: given the low bandwidth ofthe regulation block, the output voltage of PFC stagesmay exhibit excessive over or under−shoots becauseof abrupt load or input voltage variations (e.g. at startup). If the output voltage is too far from theregulation level:

Overvoltage Protection: NCP1654 turns off thepower switch as soon as Vout exceeds the OVPthreshold (105% of the regulation level). Hencea cost & size effective bulk capacitor of lowervoltage rating is suitable for this application,Dynamic Response Enhancer: NCP1654 drastically speeds up the regulation loop by itsinternal 200��A enhanced current source when theoutput voltage is below 95% of its regulation level.

− Brown−Out Detection: the circuit detects low AC lineconditions and disables the PFC stage in this case.This protection mainly protects the power switchfrom the excessive stress that could damage it in suchconditions,

− Over−Power Limitation: the NCP1654 computes themaximum permissible current in dependence of theaverage input voltage measured by the brown−outblock. It is the second OCP with a threshold that isline dependent. When the circuit detects an excessivepower transfer, it resets the driver outputimmediately,

− Thermal Shutdown: an internal thermal circuitrydisables the circuit gate drive and then keeps thepower switch off when the junction temperatureexceeds 150°C typically. The circuit resumesoperation once the temperature drops below about120°C (30°C hysteresis),

− Soft Start: Vcontrol is pulled low brown−out detectionactivates, or Undervoltage protection activates, andno drive is provided.At start up, the “200 �A enhanced current source” isdisabled. So there is only 28 �A to charge thecompensation components, and makes Vcontrol raisegradually. This is to obtain a slow increasing dutycycle and hence reduce the voltage and current stresson the MOSFET. Hence it provides a soft−startfeature.

• Output Stage Totem Pole: the NCP1654 incorporatesa ±1.5A gate driver to efficiently drive TO220 orTO247 power MOSFETs.


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PRINCIPLE OF NCP1654 SCHEME

CCM PFC BoostA CCM PFC boost converter is shown in Figure 31. The

input voltage is a rectified 50 ro 60 Hz sinusoidal signal. TheMOSFET is switching at a high frequency (typically65/133/200 kHz in NCP1654) so that the inductor current ILbasically consists of high and low−frequency components.

Filter capacitor Cfilter is an essential and very small valuecapacitor in order to eliminate the high−frequencycomponent of the inductor IL. This filter capacitor cannot betoo bulky because it can pollute the power factor bydistorting the rectified sinusoidal input voltage.

Figure 31. CCM PFC Boost Converter

+

Cbulk

Vin

RSENSE

Cfilter

LIin IL Vout

OutputVoltage

PFC MethodologyThe NCP1654 uses a proprietary PFC methodology

particularly designed for CCM operation. The PFCmethodology is described in this section.

Figure 32. Inductor Current in CCM

Time

IinIL

t1 t2

T

As shown in Figure 32, the inductor current IL in aswitching period T includes a charging phase for duration t1and a discharging phase for duration t2. The voltageconversion ratio is obtained in (Equation 1).

VoutVin

�t1 � t2

t2� T

T � t1

(eq. 1)Vin �T � t1

TVout

where

Vout is the output voltage of PFC stage,

Vin is the rectified input voltage,

T is the switching period,

t1 is the MOSFET on time, and

t2 is the MOSFET off time.

The input filter capacitor Cfilter and the front−ended EMIfilter absorbs the high−frequency component of inductorcurrent IL. It makes the input current Iin a low−frequencysignal only of the inductor current.

(eq. 2)Iin � IL�50

where

Iin is the input AC current.

IL is the inductor current.IL−50 supposes a 50 Hz operation. The suffix 50 means it

is with a 50 Hz bandwidth of the original IL.From (Equation 1) and (Equation 2), the input impedance

Zin is formulated.

(eq. 3)Zin �VinIin

�T � t1

TVout

IL�50

where Zin is input impedance.Power factor is corrected when the input impedance Zin in

(Equation 3) is constant or varies slowly in the 50 or 60 Hzbandwidth.

Figure 33. PFC Duty Modulation and Timing Diagram

+-

+

Ich

VM VrefPFC Modula-

tion

VrampCramp

R

S

Q

Clock

0 1

Vramp

Vref

VM

VM withoutFiltering

Clock

Latch Set

Latch Reset

Output

InductorCurrent

The PFC modulation and timing diagram is shown inFigure 33. The MOSFET on time t1 is generated by theintersection of reference voltage VREF and ramp voltageVramp. A relationship in (Equation 4) is obtained.

(eq. 4)Vramp � Vm �Icht1

Cramp� VREF

where


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Vramp is the internal ramp voltage, the positive input of thePFC modulation comparator,

Vm is the multiplier voltage appearing on Vm pin,

Ich is the internal charging current,

Cramp is the internal ramp capacitor, and

VREF is the internal reference voltage, the negative input ofthe PFC modulation comparator.

Ich, Cramp, and VREF also act as the ramp signal ofswitching frequency. Hence the charging current Ich isspecially designed as in (Equation 5). The multiplier voltageVm is therefore expressed in terms of t1 in (Equation 6).

(eq. 5)Ich �CrampVREF

T

(eq. 6)Vm � VREF �t1

Cramp

CrampVREFT

� VREF

T � t1T

From (Equation 3) and (Equation 6), the input impedanceZin is re−formulated in (Equation 7).

(eq. 7)Zin �Vm

VREF

VoutIL�50

Because VREF and Vout are roughly constant versus time,the multiplier voltage Vm is designed to be proportional tothe IL−50 in order to have a constant Zin for PFC purpose. Itis illustrated in Figure 34.

Figure 34. Multiplier Voltage Timing Diagram

Time

Time

TimeVM

IL

Iin

Vin

It can be seen in the timing diagram in Figure 33 that Vmoriginally consists of a switching frequency ripple comingfrom the inductor current IL. The duty ratio can beinaccurately generated due to this ripple. This modulation isthe so−called “peak current mode”. Hence, an externalcapacitor CM connected to the multiplier voltage Vm pin isessential to bypass the high−frequency component of Vm.The modulation becomes the so−called “average currentmode” with a better accuracy for PFC.

Figure 35. External Connection on the MultiplierVoltage Pin

PFC DutyModulation

Vm �RMIcsVbo

4(Vcontrol � VCONTROL(min))

RM CM

Vm Im

2

The multiplier voltage Vm is generated according to(Equation 8).

(eq. 8)Vm �RMIcsVbo

4(Vcontrol � VCONTROL(min))

Where,

RM is the external multiplier resistor connected to Vm pin,which is constant.

Vbo is the input voltage signal appearing on the BO pin,which is proportional to the rms input voltage,

Ics is the sense current proportional to the inductor currentIL as described in (Equation 11).

Vcontrol is the control voltage signal, the output voltage ofOperational Trans−conductance Amplifier (OTA), asdescribed in (Equation 12).

RM directly limits the maximum input power capabilityand hence its value affects the NCP1654 to operate in either“follower boost mode” or “constant output voltage mode”.

Figure 36. External Connection on the Brown Out Pin

Vbo

BO4

+

RboL

Vin

RboU

CBO +-

VboH / VboLVboH = 1.3 V, VboL = 0.7 V

Refer to Figure 36,

(eq. 9)Vbo � KBO(Vin) � KBO � 2 2� Vac

(eq. 10)KBO �RboL

RboU � RboL

where

Vbo is the voltage on BO pin.

KBO is the decay ratio of Vin to Vbo.

<Vin> is the average voltage signal of Vin, the voltageappearing on Cfilter.

Vac is the RMS input voltage.


NCP1654

www.onsemi.com14

RboL is low side resistor of the dividing resistors between Vinand BO pin.

RboU is upper side resistor of the dividing resistors betweenVin and BO pin.

Figure 37. Current Sensing

Gnd

+

RSENSE

IL

RCS

ICS CS

VCS

NCP1654+

−

IL

Refer to Figure 37, sense current Ics is proportional to theinductor current IL as described in (Equation 11). IL consistsof the high−frequency component (that depends on di/dt orinductor L) and low−frequency component (that is IL−50).

(eq. 11)Ics �RSENSE

RCSIL

where

RSENSE is the sense resistor to sense IL.

RCS is the offset resistor between CS pin and RSENSE.

Figure 38. Vcontrol Low−Pass Filtering

+-

VREF OTA

6

5

Vcontrol

±20 �A

Vout

+

+VCONTROL(min)

To Vm Pin

Vfb

RZ

CZ

CP

RfbL

RfbU

Vin

Refer to Figure 38, the Operational Trans−conductanceAmplifier (OTA) senses Vout via the feedback resistordividers, RfbU and RfbL. The OTA constructs a controlvoltage, Vcontrol, depending on the output power and henceVout. The operating range of Vcontrol is from VCONTROL(min)to VCONTROL(max). The signal used for PFC dutymodulation is after decreasing a offset voltage,VCONTROL(min), i.e. Vcontrol−VCONTROL(min).

This control current Icontrol is a roughly constant currentthat comes from the PFC output voltage Vout that is a slowlyvarying signal. The bandwidth of Icontrol can be additionallylimited by inserting the external type−2 compensationcomponents (that are RZ, CZ, and CP as shown in Figure 38).It is recommended to limit fcontrol, that is the bandwidth ofVcontrol (or Icontrol), below 20 Hz typically to achieve powerfactor correction purpose.

The transformer of Vout to Vcontrol is as described in(Equation 12) if CZ is >> CP. GEA is the error amplifier gain.

VcontrolVout

�RfbL � GEARZRfbL � RfbU

�1 � sRZCZ

sRZCZ(1 � sRZCP)(eq. 12)

From (Equation 7) − (Equation 11), the input impedanceZin is re−formulated in (Equation 13).

Zin �2 RMRSENSEVoutVacKBOIL

2�RCS � (Vcontrol � VCONTROL(min)) � VREFIL�50

(eq. 13)

When IL is equal to IL−50, (Equation 13) is re−formulatedin (Equation 14)

Zin �2 RMRSENSEVoutVacKBO

2�RCS � (Vcontrol � VCONTROL(min)) � VREF(eq. 14)

The multiplier capacitor CM is the one to filter thehigh−frequency component of the multiplier voltage Vm.The high−frequency component is basically coming fromthe inductor current IL. On the other hand, the filter capacitorCfilter similarly removes the high−frequency component ofinductor current IL. If the capacitors CM and Cfilter matchwith each other in terms of filtering capability, IL becomesIL−50. Input impedance Zin is roughly constant over thebandwidth of 50 or 60 Hz and power factor is corrected.


NCP1654

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Input and output power (Pin and Pout) are derived in (Equation 15) when the circuit efficiency η is obtained or assumed. Thevariable Vac stands for the rms input voltage.

Pin �Vac

2

Zin�

2�RCS � (Vcontrol � VCONTROL(min)) � VREF � Vac

2 RMRSENSEVoutKBO

(eq. 15)

(Vcontrol � VCONTROL(min))Vac

Vout

Pout � � Pin � �2�RCS � (Vcontrol � VCONTROL(min)) � VREF � Vac

2 RMRSENSEVoutKBO

(eq. 16)

(Vcontrol � VCONTROL(min))Vac

Vout

Follower BoostThe “Follower Boost” is an operation mode where the

pre−converter output voltage stabilizes at a level that varieslinearly versus the ac line amplitude. This technique aims atreducing the gap between the output and input voltages tooptimize the boost efficiency and minimize the cost of thePFC stage (refer to MC33260 data sheet for more details athttp://www.onsemi.com).

The NCP1654 operates in follower boost mode whenVcontrol is constant, i.e. Vcontrol raises to its maximum value

VCONTROL(max). Re−formulate (Equation 16) to become(Equation 17) and (Equation 18) by replace Vcontrol byVCONTROL(max). If Vcontrol is constant based on(Equation 15), for a constant load or power demand theoutput voltage Vout of the converter is proportional to therms input voltage Vac. It means the output voltage Voutbecomes lower when the rms input voltage Vac becomeslower. On the other hand, the output voltage Vout becomeslower when the load or power demand becomes higher.

Pout � �2�RCS � (VCONTROL(max) � VCONTROL(min)) � VREF � Vac

2 RMRSENSEVoutKBO

(eq. 17)

� �2�RCS � �VCONTROL � VREF � Vac

2 RMRSENSEVoutKBO

Vout � �2�RCS � �VCONTROL � VREF

2 RMRSENSEKBO

�VacPout

(eq. 18)

where

VCONTROL(max) is the maximum control voltage.

�VCONTROL is the gap between VCONTROL(max) andVCONTROL(min).

It is illustrated in Figure 39.

Figure 39. Follower Boost Characteristics

Vout (Traditional Boost)

Vout (Follower Boost)

Vin

Pout

Time

Time

Follower Boost BenefitsThe follower boost circuit offers and opportunity to

reduce the output voltage Vout whenever the rms inputvoltage Vac is lower or the power demand Pout is higher.Because of the step−up characteristics of boost converter,

the output voltage Vout will always be higher than the inputvoltage Vin even though Vout is reduced in follower boostoperation. As a result, the on time t1 is reduced. Reductionof on time makes the loss of the inductor and powerMOSFET smaller. Hence, it allows cheaper cost in theinductor and power MOSFET or allows the circuitcomponents to operate at a lower stress condition in most ofthe time.

Reference SectionThe internal reference voltage (VREF) is trimmed to be

±2% accurate over the temperature range (the typical valueis 2.5 V). VREF is the reference used for the regulation. VREFalso serves to build the thresholds of the fast transientresponse, Overvoltage (OVP), brown out (BO), andUndervoltage protections (UVP).

Output FeedbackThe output voltage Vout of the PFC circuits is sensed at Vfb

pin via the resistor divider (RfbL and RfbU) as shown inFigure 38. Vout is regulated as described in (Equation 19).

Vout � VREF

RfbU � RfbLRfbL

(eq. 19)


NCP1654

www.onsemi.com16

The feedback signal Vfb represents the output voltage Voutand will be used in the output voltage regulation,Overvoltage protection (OVP), fast transient response, andUndervoltage protection (UVP)

Output Voltage RegulationNCP1654 uses a high gain Operational Trans−

conductance Amplifier (OTA) as error amplifier. Refer toFigure 38, the output of OTA Vcontrol operating range isfrom VCONTROL(min) to VCONTROL(max).

Fast Transient ResponseGiven the low bandwidth of the regulation block, the

output voltage of PFC stages may exhibit excessive over orunder−shoots because of abrupt load or input voltagevariations (such as start−up duration). As shown inFigure 40, if the output voltage is out of regulation,NCP1654 has 2 functions to maintain the output voltageregulation.

Figure 40. OVP and Fast Transient Response

+-

+-

95%

VREF

VREF

OTA

6

5

Vcontrol

Vout Low Detect

200 �A

Vdd

±20 �A

+-

105%

VREF

Vout

+

OVP

Vfb

RfbU

RfbLCFB

• Overvoltage Protection: When Vfb is higher than 105%of VREF (i.e. Vout > 105% of nominal output voltage),the Driver output of the device goes low for protection.The circuit automatically resumes operation when Vfbbecomes lower than 105% of VREF. If the nominal Voutis set at 390 V, then the maximum output voltage is105% of 390 V = 410 V. Hence a cost & size effectivebulk capacitor of lower voltage rating is suitable forthis application,

• Dynamic response enhancer: NCP1654 drasticallyspeeds up the regulation loop by its internal 200 �Aenhanced current source when the output voltage is

below 95% of its regulation level. Under normalcondition, the maximum sink and source of outputcurrent capability of OTA is around 28 �A. Thanks tothe “Vout low detect” block, when the Vfb is below 95%VREF, an extra 200 �A current source will raise Vcontrolrapidly. Hence prevent the PFC output from droppingtoo low and improve the transient responseperformance. The relationship between current flowingin/out Vcontrol pin and Vfb is as shown in Figure 41.It is recommended to add a typical 100 pF capacitor CFB

decoupling capacitor next to feedback pin to prevent fromnoise impact.

−250

−200

−150

−100

−50

0

50

2 2.2 2.4 2.6 2.8 3Vfb

Figure 41. Vfb vs. Current Flowing in/out from Vcontrol Pin

No DRV whenVfb is above105% VREF

VC

ON

TR

OL

PIN

CU

RR

EN

T (�A

)

200 �A raisesVcontrol rapidlywhen Vfb is below95% VREF


NCP1654

www.onsemi.com17

Soft StartThe block diagram and timing diagram of soft start

function are as shown in Figure 42 and Figure 43. The deviceprovides no output (or no duty ratio) when the Vcontrol islower than VCONTROL(min). Vcontrol is pulled low when:• Brown−out, or

• Undervoltage ProtectionWhen the IC recovers from one of the following

conditions; Undervoltage Lockout, Brown−out orUndervoltage Protection, the 200 �A current source blockkeeps off. Hence only the Operating Trans−conductanceAmplifier (OTA) raises the Vcontrol. And Vcontrol risesslowly. This is to obtain a slow increasing duty cycle andhence reduce the voltage and current stress on the MOSFET.A soft−start operation is obtained.

Figure 42. Soft Start Block Diagram

+-

+-

95%

VREF

VREF

OTA

Vfb6

5

Vcontrol

Vout Low Detect

200 �A

Vdd

±20 �A

Q

Q

S

R

Bias

Vdd Off UVPUVLOBO

UVLOBO

95% VREF

Figure 43. Soft Start Timing Diagram

Period I Period IIUVLO, BO, or UVP

Vdd

Vdd Rising

Vfb

Set

Reset

Q

Vout Low Detect


NCP1654

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Undervoltage Protection (UVP) for Open LoopProtection or Shutdown

Figure 44. Undervoltage Protection

ISTDN

ICC2

Shutdown Operating

8% VREF 12% VREF

Vfb

As shown in Figure 44, when Vfb is less than 8% of VREF,the device is shut down and consumes less than 400 �A. Thedevice automatically starts operation when the outputvoltage goes above 12% of VREF. In normal situation ofboost converter configuration, the output voltage Vout isalways greater than the input voltage Vin and the feedbacksignal Vfb is always greater than 8% and 12% of VREF toenable NCP1654 to operate.

This Undervoltage Protection function has 2 purposes.• Open Loop Protection − Protect the power stage from

damage at feedback loop abnormal, such as Vfb isshorted to ground or the feedback resistor RfbU is open.

• Shutdown mode − Disables the PFC stage and forces alow consumption mode. This feature helps to meetstringent stand−by specifications. Power Factor beingnot necessary in stand−by, the PFC stage is generallyinhibited to save the pre−converter losses. To furtherimprove the stand−by performance, the PFC controllershould consume minimum current in this mode.

Current SenseThe device senses the inductor current IL by the current

sense scheme in Figure 37. The device maintains the voltageat CS pin to be zero voltage (i.e., Vcs ≈ 0 V) so that(Equation 11),

Ics �RSENSE

RCSIL ,

can be formulated.This scheme has the advantage of the minimum number

of components for current sensing. The sense current Icsrepresents the inductor current IL and will be used in the PFCduty modulation to generate the multiplier voltage Vm,Over−Power Limitation (OPL), and Over−CurrentProtection. (Equation 11) would insist in the fact that itprovides the flexibility in the RSENSE choice and that itallows to detect in−rush currents.

Over−Current Protection (OCP)Over−Current Protection is reached when Ics is larger than

IS(OCP) (200 �A typical). The offset voltage of the CS pin istypical 10 mV and it is neglected in the calculation. Hence,the maximum OCP inductor current threshold IL(OCP) isobtained in (Equation 20).

(eq. 20)IL(OCP) �RCSIS(OCP)

RSENSE�

RCSRSENSE

� 200 �A

When over−current protection threshold is reached, theDrive Output of the device goes low. The deviceautomatically resumes operation when the inductor currentgoes below the threshold.

Input Voltage SenseThe device senses the rms input voltage Vac by the sensing

scheme in Figure 45. Vbo senses the average rectified inputvoltage Vin via the resistor divider. An external capacitorCBO is to maintain the Vbo the average value of Vin. Vbo isused for Brown−Out Protection, PFC duty modulation andover−power limitation (OPL).

Brown−Out ProtectionThe device uses the Vbo signal to protect the PFC stage

from operating as the input voltage is lower than expected.Re−formulate (Equation 9) to get (Equation 21). Refer toFigure 45, Vin is different before and after the deviceoperating.• Before the device operates, Vin is equal to the peak

value of rms input voltage, Vac. Hence Vbo is asdescribed in (Equation 21).

(eq. 21)Vbo �RboL

RboL � RboU(Vin) �

RboLRboL � RboU

2 Vac

• After device operates, Vin is the rectified sinusoidalinput voltage. Thanks to CBO, Vbo is the average ofrectified input voltage. Hence Vbo decays to 2/� of thepeak value of rms input voltage Vac as described in(Equation 22).

(eq. 22)Vbo �RboL

RboL � RboU

2 2� Vac


NCP1654

www.onsemi.com19

CBO

Figure 45. Brown−Out Protection

+- BO

4RboL

RboU Vbo

Vin

+Vac+

−

IN

VboH / VboLVboH = 1.3 V, VboL = 0.7 V

After Device OperatesBefore Device Operates

Hence a larger hysteresis of the brown out comparator isneeded, which is 0.7 V typical in this device. When Vbo goesbelow than VBOL (0.7 V typical), the device turns off theDrive output and keeps it off till Vbo exceeds VBOH (1.3 Vtypical). When the device awakes after an off−state(Undervoltage lockout or shutdown), the default thresholdis VBOH.

Overpower Limitation (OPL)This is a second OCP with a threshold that is line

dependent. Sense current Ics represents the inductor currentIL and hence represents the input current approximately.Input voltage signal Vbo represents the rms input voltage.The product (Ics ⋅ Vbo) represents an approximated inputpower (IL ⋅ Vac). It is illustrated in Figure 46.

Figure 46. Over−Power Limitation

Current Mirror

>200 �VA?

OPL

+

RCS ICS CS

Vbo

4

3

RSENSE

Vin

IL

ICS � ILRSENSE

RCS

When the product (Ics ⋅ Vbo) is greater than a permissiblelevel 200 �VA, the device turns off the drive output so thatthe input power is limited. The OPL is automaticallydeactivated when the product (Ics ⋅ Vbo) is lower than the200 �VA level. This 200 �VA level corresponds to theapproximated input power (IL ⋅ Vac) to be smaller than theparticular expression in (Equation 23).

(eq. 23)IcsVbo � 200 �VA

�ILRSENSE

RCS� � �2 2 KBO

� � Vac�� 200 �VA

IL � Vac �RCS � �

RSENSE � KBO� 50 2 �VA

Bias the ControllerIt is recommended to add a typical 1 nF to 100 nF

decoupling capacitor next to the Vcc pin for properoperation. When the NCP1654 operates in follower boostmode, the PFC output voltage is not always regulated at aparticular level under all application range of input voltageand load power. It is not recommended to make alow−voltage bias supply voltage by adding an auxiliarywinding on the PFC boost inductor. Alternatively, it isrecommended to get the Vcc biasing supply from the2nd−stage power conversion stage.


NCP1654

www.onsemi.com20

Vcc Undervoltage LockOut (UVLO)The device incorporates an Undervoltage Lockout block

to prevent the circuit from operating when Vcc is too low inorder to ensure a proper operation. An UVLO comparatormonitors Vcc pin voltage to allow the NCP1654 to operatewhen Vcc exceeds 10.5 V typically. The comparator

incorporates some hysteresis (1.5 V) to prevent erraticoperation as the Vcc crosses the threshold. When Vcc goesbelow the UVLO comparator lower threshold (9 Vtypically), the circuit turns off. It is illustrated in Figure 47.After startup, the operating range is between 9 V and 20 V.

Figure 47. Vcc Undervoltage LockOut (UVLO)

VCC

VCC

ICC

ON

OFF

State

<75 �A

VCC(ON)VCC(OFF)

6 mA

Thermal ShutdownAn internal thermal circuitry disables the circuit gate drive

and then keeps the power switch off when the junctiontemperature exceeds 150°C. The output stage is then

enabled once the temperature drops below typically 120°C(i.e., 30°C hysteresis). The thermal shutdown is provided toprevent possible device failures that could result from anaccidental overheating.


NCP1654

www.onsemi.com21

Figure 48. Application Schematic − 300 W 65 kHzPower Factor Correction Circuit

TB2

390 V

R1

R2

1.8 M

1.8 M

+

C4180 �F, 450 V

1 2

D1 MSR860G

Q1

SPP20N60S5

R4

10 k

R5 10

D2

1N4148

TB3

+15 V +

21

C8

22 �FC9

0.1 �F C10

100 pFR3

23.2 k

C12

2.2 �F

C5

220 nF

NCP1654

R8

47 k

C61 nF

R11

82.5 k

C7

0.47 �F

R10

0

R13

3.3 M

R9

3.3 M

R7

3.6 k

650 �H

5

2

L1 R6 0.1

C3

0.1 �F

DB1

C2

0.47 �F

2 x 6.8 mHL2

L3 150 �H

C1

0.47 �F5 A Fuse

F1

AC InletL N

1

TB1

2 3

IC1

1 2 3 4

8 7 6 5

GN

D

VM CS

BO

DR

V

VC

C

FB

Vco

ntro

l

R1212 k

+

−

GBU8J

8 A600 V


SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

SEATINGPLANE

14

58

N

J

X 45�

K

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

A

B S

DH

C

0.10 (0.004)

SCALE 1:1

STYLES ON PAGE 2

DIMA

MIN MAX MIN MAXINCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B 3.80 4.00 0.150 0.157C 1.35 1.75 0.053 0.069D 0.33 0.51 0.013 0.020G 1.27 BSC 0.050 BSCH 0.10 0.25 0.004 0.010J 0.19 0.25 0.007 0.010K 0.40 1.27 0.016 0.050M 0 8 0 8 N 0.25 0.50 0.010 0.020S 5.80 6.20 0.228 0.244

−X−

−Y−

G

MYM0.25 (0.010)

−Z−

YM0.25 (0.010) Z S X S

M� � � �

XXXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package

GENERICMARKING DIAGRAM*

1

8

XXXXXALYWX

1

8

IC Discrete

XXXXXXAYWW

�1

8

1.520.060

7.00.275

0.60.024

1.2700.050

4.00.155

� mminches

�SCALE 6:1

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

Discrete

XXXXXXAYWW

1

8

(Pb−Free)

XXXXXALYWX

�1

8

IC(Pb−Free)

XXXXXX = Specific Device CodeA = Assembly LocationY = YearWW = Work Week� = Pb−Free Package

*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “�”, mayor may not be present. Some products maynot follow the Generic Marking.

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

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PAGE 1 OF 2SOIC−8 NB

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

STYLE 4:PIN 1. ANODE

2. ANODE3. ANODE4. ANODE5. ANODE6. ANODE7. ANODE8. COMMON CATHODE

STYLE 1:PIN 1. EMITTER

2. COLLECTOR3. COLLECTOR4. EMITTER5. EMITTER6. BASE7. BASE8. EMITTER

STYLE 2:PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #13. COLLECTOR, #24. COLLECTOR, #25. BASE, #26. EMITTER, #27. BASE, #18. EMITTER, #1

STYLE 3:PIN 1. DRAIN, DIE #1

2. DRAIN, #13. DRAIN, #24. DRAIN, #25. GATE, #26. SOURCE, #27. GATE, #18. SOURCE, #1

STYLE 6:PIN 1. SOURCE

2. DRAIN3. DRAIN4. SOURCE5. SOURCE6. GATE7. GATE8. SOURCE

STYLE 5:PIN 1. DRAIN

2. DRAIN3. DRAIN4. DRAIN5. GATE6. GATE7. SOURCE8. SOURCE

STYLE 7:PIN 1. INPUT

2. EXTERNAL BYPASS3. THIRD STAGE SOURCE4. GROUND5. DRAIN6. GATE 37. SECOND STAGE Vd8. FIRST STAGE Vd

STYLE 8:PIN 1. COLLECTOR, DIE #1

2. BASE, #13. BASE, #24. COLLECTOR, #25. COLLECTOR, #26. EMITTER, #27. EMITTER, #18. COLLECTOR, #1

STYLE 9:PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #13. COLLECTOR, DIE #24. EMITTER, COMMON5. EMITTER, COMMON6. BASE, DIE #27. BASE, DIE #18. EMITTER, COMMON

STYLE 10:PIN 1. GROUND

2. BIAS 13. OUTPUT4. GROUND5. GROUND6. BIAS 27. INPUT8. GROUND

STYLE 11:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. DRAIN 27. DRAIN 18. DRAIN 1

STYLE 12:PIN 1. SOURCE

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 14:PIN 1. N−SOURCE

2. N−GATE3. P−SOURCE4. P−GATE5. P−DRAIN6. P−DRAIN7. N−DRAIN8. N−DRAIN

STYLE 13:PIN 1. N.C.

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 15:PIN 1. ANODE 1

2. ANODE 13. ANODE 14. ANODE 15. CATHODE, COMMON6. CATHODE, COMMON7. CATHODE, COMMON8. CATHODE, COMMON

STYLE 16:PIN 1. EMITTER, DIE #1

2. BASE, DIE #13. EMITTER, DIE #24. BASE, DIE #25. COLLECTOR, DIE #26. COLLECTOR, DIE #27. COLLECTOR, DIE #18. COLLECTOR, DIE #1

STYLE 17:PIN 1. VCC

2. V2OUT3. V1OUT4. TXE5. RXE6. VEE7. GND8. ACC

STYLE 18:PIN 1. ANODE

2. ANODE3. SOURCE4. GATE5. DRAIN6. DRAIN7. CATHODE8. CATHODE

STYLE 19:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. MIRROR 27. DRAIN 18. MIRROR 1

STYLE 20:PIN 1. SOURCE (N)

2. GATE (N)3. SOURCE (P)4. GATE (P)5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 21:PIN 1. CATHODE 1

2. CATHODE 23. CATHODE 34. CATHODE 45. CATHODE 56. COMMON ANODE7. COMMON ANODE8. CATHODE 6

STYLE 22:PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC3. COMMON CATHODE/VCC4. I/O LINE 35. COMMON ANODE/GND6. I/O LINE 47. I/O LINE 58. COMMON ANODE/GND

STYLE 23:PIN 1. LINE 1 IN

2. COMMON ANODE/GND3. COMMON ANODE/GND4. LINE 2 IN5. LINE 2 OUT6. COMMON ANODE/GND7. COMMON ANODE/GND8. LINE 1 OUT

STYLE 24:PIN 1. BASE

2. EMITTER3. COLLECTOR/ANODE4. COLLECTOR/ANODE5. CATHODE6. CATHODE7. COLLECTOR/ANODE8. COLLECTOR/ANODE

STYLE 25:PIN 1. VIN

2. N/C3. REXT4. GND5. IOUT6. IOUT7. IOUT8. IOUT

STYLE 26:PIN 1. GND

2. dv/dt3. ENABLE4. ILIMIT5. SOURCE6. SOURCE7. SOURCE8. VCC

STYLE 27:PIN 1. ILIMIT

2. OVLO3. UVLO4. INPUT+5. SOURCE6. SOURCE7. SOURCE8. DRAIN

STYLE 28:PIN 1. SW_TO_GND

2. DASIC_OFF3. DASIC_SW_DET4. GND5. V_MON6. VBULK7. VBULK8. VIN

STYLE 29:PIN 1. BASE, DIE #1

2. EMITTER, #13. BASE, #24. EMITTER, #25. COLLECTOR, #26. COLLECTOR, #27. COLLECTOR, #18. COLLECTOR, #1

STYLE 30:PIN 1. DRAIN 1

2. DRAIN 13. GATE 24. SOURCE 25. SOURCE 1/DRAIN 26. SOURCE 1/DRAIN 27. SOURCE 1/DRAIN 28. GATE 1

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