1 Multi-Core for Real-Time and Safety-Critical Software: Avoid the Pitfalls Dr. Fridtjof Siebert, CTO, aicas GmbH Dr. James J. Hunt, CEO, aicas GmbH aicas Technology Multicore for Real-Time and Safety-Critical Software: Avoid the Pitfalls Dr. Fridtjof Siebert, CTO, aicas Dr. James J. Hunt, CEO aicas MultiCoreExpo 2011, 5 th May 2011
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1
Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
aicas Technology
Multicore for Real-Timeand Safety-Critical Software:
Avoid the Pitfal ls
Dr. Fridtjof Siebert, CTO, aicasDr. James J. Hunt, CEO aicas
MultiCoreExpo 2011, 5th May 2011
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Agenda
Race conditions
Synchronization
Atomic operations
Memory model
Values out of thin air
Reaching peak performance
CPU affinities
Multicore scheduling
Lock free algorithms
Compare and Swap
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Typical Problems on Mult icore
typical code sequence (C/C++ or Java)
int counter;
void increment(){ counter++; }
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Typical Problems on Mult icore
typical code sequence (C/C++ or Java)
int counter;
void increment(){ counter++; } r1 = counter;
r2 = r1 + 1; counter = r2;
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Typical Problems on Mult icore
typical code sequence (C/C++ or Java)
int counter;
void increment(){ counter++; } r1 = counter;
r2 = r1 + 1; counter = r2;
r1 = counter; r2 = r1 + 1; counter = r2;
Thread 1 Thread 2
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Typical Problems on Mult icore
typical code sequence (C/C++ or Java)
int counter;
void increment(){ counter++; } r1 = counter;
r2 = r1 + 1; counter = r2;
r1 = counter; r2 = r1 + 1; counter = r2;
Thread 1 Thread 2
An increment can get lost!
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Typical Problems on Mult icore
typical code sequence (C/C++ or Java)
int counter;
void increment(){ counter++; }
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Typical Problems on Mult icore
typical code sequence (C/C++ or Java)
int counter;
void increment(){ counter++; }
code lacks synchronization
but on a single core, it practically always works!
on a multicore, chances for failure explode!
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Synchronization
solution: synchronize
int counter;
synchronized void increment(){ counter++; }
Easy, problem solved.
Right? See later.
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Atomic Operations
What is the result of
int a, b; /* 32 bit, initially 0 */
Thread 1 Thread 2 b = a; a = 1;
?
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Atomic Operations
What is the result of
int a, b; /* 32 bit, initially 0 */
Thread 1 Thread 2 b = a; a = 1;
?
b == 0b == 1
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Atomic Operations
What is the result of
long a, b; /* 64 bit, initially 0 */
Thread 1 Thread 2 b = a; a = 1;
?
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Atomic Operations
What is the result of
long a, b; /* 64 bit, initially 0 */
Thread 1 Thread 2 b = a; a = 1;
?
b == 0b == 1b == 4294967296b == 4294967295
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Out of Thin Air
imagine this codeint x = 0, n = 0;
Thread 1 Thread 2 for (i=0; i<n; i++) x = 42; x += f(i); print(x);
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Out of Thin Air
imagine this codeint x = 0, n = 0;
Thread 1 Thread 2 for (i=0; i<n; i++) x = 42; x += f(i); print(x);
can only print 42 in Java
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Out of Thin Air: Introduction of Writes
loop optimization in C/C++int x = 0, n = 0;
Thread 1 Thread 2 tmp = x; for (i=0; i<n; i++) x = 42; tmp += f(i);x = tmp; print(x);
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Out of Thin Air: Introduction of Writes
loop optimization in C/C++int x = 0, n = 0;
Thread 1 Thread 2 tmp = x; for (i=0; i<n; i++) x = 42; tmp += f(i);x = tmp; print(x);
can print 0 in C/C++
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Out of Thin Air
imagine this codeint x = 0, y = 0;
Thread 1 Thread 2 r1 = x; r2 = y;y = r1; x = r2;
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Out of Thin Air
imagine this codeint x = 0, y = 0;
Thread 1 Thread 2 r1 = x; r2 = y;y = r1; x = r2;
Expected result x == 0; y == 0;
Only possible result in Java
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Out of Thin Air: Optimization in C/C++
imagine this codeint x = 0, y = 0;
Thread 1 Thread 2 y = 42; r2 = y;r1 = x; x = r2;if (r1 != 42) y = r1;
Possible results in upcoming C++ MM x == 42; y == 42;
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Performance on Mult icore: Example
Single core application, 3 threads
All threads synchronize frequently on same lock
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Performance on Mult icore: Example
Single core application, 3 threads
All threads synchronize frequently on same lock
while (true) { synchronized (lock) { counter++; } doSomething(); }
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Single core application, 3 threads
Performance on Mult icore: Example
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Single core application, 3 threads
On a multicore
Performance on Mult icore: Example
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Performance on a Mult icore
Frequent synchronization can kill the performance
Typical non-RTOS will use heuristics to improve average performance
spin-lock for a short time
blocking for longer periods
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Performance on a Mult icore
These heuristics introduce priority-inversion and generally destroy predictability
A typical semaphore implementationdoes not take thread priority into account
does not limit worst-case-execution-time
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CPU Affinit ies
OSes provide APIs to lock threads certain CPUs
This limits the decision space of the RTOSa global scheduler for n CPUs would always run the n highest priority threads
with affinities, this may not be possible, e.g., if the two highest priority threads are locked to the same CPU
CPU affinities can introduce priority inversion!
So what are CPU affinities good for?
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CPU Affinit ies: No More interrupts
Locking interrupts to a dedicated CPUprotects all other CPUs from interrupts, and
invalidated cashes
WCETA is simplified considerably
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CPU Affinit ies: No More interrupts
Locking interrupts to a dedicated CPUprotects all other CPUs from interrupts, and
invalidated cashes
WCETA is simplified considerably
non-RT Task
Interrupt
CPU0
CPU1 A A A A A A A A A A A RT Task
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CPU Affinit ies: Separating Threads
Locking thread A to one CPU and threads B, C, ... to other CPUs may increase A's performance.
A will not be preempted by B, C, ..
A will not see its caches invalidated by B, C, ...
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CPU Affinit ies: Separating Threads
Locking thread A to one CPU and threads B, C, ... to other CPUs may increase A's performance.
A will not be preempted by B, C, ..
A will not see its caches invalidated by B, C, ...
non-RT Task
RT Task
CPU0
CPU1
CPU2
A AA A A A
B
B B
B
B
A A A A A
B
B
B
C C C
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CPU Affinit ies: Grouping Threads
Locking threads A and B to the same CPUwill increase shared memory communication between A and B
will avoid performance degradation on locking
will enable simple scheduling analysis (RMA)
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CPU Affinit ies: Grouping Threads
Locking threads A and B to the same CPUwill increase shared memory communication between A and B
will avoid performance degradation on locking
will enable simple schedule feasibility analysis (RMA)
RT Task ACPU0
CPU1
CPU2
BAA B A RT Task B
Other Task
C
C
DD D D
E E E E
E
E
EC C
GG
G
BA
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CPU Affinit ies: Diff icult Decisions
what if A and B both computation intensive and both access the same shared memory?
How can we use idle time?
...
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Multicore Scheduling for Realt ime
A pure priority based scheduler is not sufficient:
Imagine three tasks A, B, C on 2 CPUS
A
B
C
Release Deadline
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Multicore Scheduling for Realt ime
Priorities will cause deadline miss
A pri=10
B pri=10
CPU0
CPU1
C pri=9
Release Deadline
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Multicore Scheduling for Realt ime
Priorities will cause deadline miss
A pri=10
B pri=10
CPU0
CPU1
C pri=9Release Deadline
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Multicore Scheduling for Realt ime
CPU affinities do not help
A pri=10, {CPU0}
B pri=10, {CPU1}
CPU0
CPU1
C pri=9
Release Deadline
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Multicore Scheduling for Realt ime
Round robin could help
ACPU0
CPU1
C B
B A C B A C
A C B
Release Deadline
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
A C B
B A C B A C
A C B
Multicore Scheduling for Realt ime
Round robin could help
Release Deadline
CPU0
CPU1
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Performance on Multicore
Synchronization is expensive
Can synchronization be avoided?
Can lock free algorithms be used?Use compare and swap (CAS) instructions instead
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Lock Free Algorithms
Typical code sequence
do { x = counter; result = CAS(counter,x,x+1); }while (result != x);
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Compare-and-Swap Issues
Typical code sequence
do { x = counter; result = CAS(counter,x,x+1); }while (result != x);
What is the WCET? ∞?
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
On dual core:
# iterations
fre
qu
en
cy
Typical code sequence
do { x = counter; result = CAS(counter,x,x+1); }while (result != x);
What is the WCET? ∞?
Compare-and-Swap Issues
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Lock Free Library Code
Using libraries helpsAtomicInteger counter = new AtomicInteger();void increment(){ (void)counter.incrementAndGet();}
Code is easier and safer
Hand made lock free algorithms are not for normal application development
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Compare-and-Swap Solutions
One way state changes, without retry
Bounded number of retries
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
One Way State Changes Using CAS
Example codefor (i=0; i<N; i++) { new Thread() { public void run() { CAS(state,INIT,STARTING); [..] } }.start(); }
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Bounding Retries for CAS
introduce long enough code sections in between 2 compare-and-swap loops
then, if a retry is required, one other CPU was successful
after n-1 conflicts, one can be sure that all other CPUs are outside the CAS loop
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Bounding Retries for CAS: Example
AtomicInteger counter = new AtomicInteger(); static final int GRANULARITY = 64; [..] new Thread(){ int local_counter; public void incCounter() { local_counter++; if (local_counter >= GRANULARITY) { local_counter = 0; counter.addAndSet(GRANULARITY); } } }.start();
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
Measurements
alloc free sweep available Memory1E-1
1E+0
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E+8
1E+9
1E+10
1E+11
123456789
Number of CAS tries is bounded:
On 8-CPU x86 system (Linux)
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists
List modifaction using CAS, single linked list
next
data
head next
data
next
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A B C
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists
Add
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B CA B C
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists
Add: CAS(head,A,X)
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists
Add: CAS(head,A,X)
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists
Remove: CAS(head,A,B)
head next
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists
Remove: CAS(head,A,B)
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists, ABA Problem
Now, consider concurrent modifications:
next
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists, ABA Problem
next
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists, ABA Problem
next
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CAS(head,A,B)
preempted
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists, ABA Problem
next
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Thread 1remove:
CAS(head,A,B)
preempted
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists, ABA Problem
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists, ABA Problem
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists, ABA Problem
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists, ABA Problem
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add A:CAS(head,C,A)
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists, ABA Problem
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists, ABA Problem
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Thread 1remove:
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
CAS Lists, ABA Problem
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remove:CAS(head,A,B)
add A:CAS(head,C,A)
Thread 1remove:
CAS(head,A,B)
preempted
B was re-introduced!
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
ABA Problem: Solutions
Non solution: In C: free() after remove
Reason: newly allocated block may be sameSolution: In Java: only add new references
Reason: GC ensures old values no longer visibleSolution: Sync all threads before reuse
Example: Phase 1 moves elements from List1 to List2, Phase 2 moves elements back
Solution: Use 64-/128-bit CAS and mod. counter
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
ABA Solved via Modification Counter
next
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preempted
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
ABA Solved via Modification Counter
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B:43)
Thread 1remove:
preempted
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
ABA Solved via Modification Counter
next
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head: 42 next
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head: 43 next
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Thread 2remove:CAS(head,A:42,
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Thread 1remove:
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
ABA Solved via Modification Counter
next
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remove:CAS(head,B:43,
C:44)
Thread 1remove:
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
ABA Solved via Modification Counter
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Thread 2remove:CAS(head,A:42,
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remove:CAS(head,B:43,
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add A:CAS(head,C:44,
A:45)
Thread 1remove:
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
ABA Solved via Modification Counter
next
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head: 42 next
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A B
head: 43 next
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B
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C
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Thread 2remove:CAS(head,A:42,
B:43)
remove:CAS(head,B:43,
C:44)
add A:CAS(head,C:44,
A:45)
Thread 1remove:
CAS(head,A:42,B:43)
retry!
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
ABA Solved via Modification Counter
next
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head: 42 next
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head: 43 next
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Thread 2remove:CAS(head,A:42,
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remove:CAS(head,B:43,
C:44)
add A:CAS(head,C:44,
A:45)
Thread 1remove:
CAS(head,A:42,B:43)
retry!CAS(head,A:45,
C:46)
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Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH
ConclusionCode that runs well on single CPU may fail on multicore
Clear semantics of concurrent code is required for functional correctness
Cost of locking may be prohibitive
CPU affinities may help, but it is difficult to make the application more efficient
Lock free code is very hard to get right
A reliable memory model and good concurrent libraries are basis to avoid pitfalls.
112
Multi-Core for Real-Time and Safety-Critical Software: Avoid the PitfallsDr. Fridtjof Siebert, CTO, aicas GmbHDr. James J. Hunt, CEO, aicas GmbH