M.tech VLSI SEM II MID I ImportantQuestions

8/12/2019 M.tech VLSI SEM II MID I ImportantQuestions

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Department of ECE Course: M.TECH VLSI Regulation: R13

Subject: Low Power VLSI Design

Reference Books:

UNITS:II

PART A Question

1. Explain in-detail Low Power Design through voltage scaling2. How voltage scaling was influenced on Power and delay3. With neat circuit diagram explain variable-Threshold CMOS(VTCMOS) circuit.4. With neat circuit diagram explain multiple-Threshold CMOS(MTCMOS) circuit.5. With relevant equations & circuit diagram explain Pipelining approach for low power design.

PART B Questions

1. With relevant equations and circuit diagram explain Parallel processing approach( hardware replication) forlow power design

2. Explain various switched capacitance minimization approaches3. Explain the concept of system level measures with neat circuit diagram4. With neat circuit diagram explain the concept of circuit level measures5. With neat circuit diagram explain the concept of Mask level measures


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Subject: CAD for VLSI Circuits

Reference Books:

UNITS:I

PART A Question

1. Briefly discuss the VLSI Physical Design Automation2. With neat sketch explain the various stages of VLSI Design Cycle

PART B Questions

1. Explain in detail, new trends in VLSI Design cycle.2. With neat sketch explain VLSI Physical design cycle3. With neat sketch Explain various VLSI Physical design styles4. Explain various system packaging styles.


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Subject:CAD for VLSI CircuitsReference Books:

UNITS:II

PART A Question

1. Explain in-detail various partitioning techniques.2. Explain the following problem formulation schemes: a) Interconnections between partitions b) Delay due to

partitioning c) Number of terminals d) Area of each partition e) Number of partitions.

3. Explain in-detail various Design Style Specific Partitioning Problems.4. Briefly describe Classification of Partitioning Algorithms5. Explain the following group migration algorithms: a) Kernighan-Lin Algorithm b) Extensions of Kernighan-Lin

Algorithm

6. Explain the following in-detail: a) Simulated Annealing b) Simulated Evolution

PART B Questions

1. What are the various factors for Physical VLSI Design?2. Briefly explain the floor planning mechanism, also discuss Design Style Specific Floor planning Problems3. With relevant information classify the Floor planning algorithms.4. Explain the following Floor planning algorithms: a) Constraint based methods b) Integer programming based

methods c) Rectangular dualization based methods d) Hierarchical tree based methods.

5. Explain different levels of placement techniques in physical design6. Explain in-detail performance driven placement problem.7. Explain briefly Design Style Specific Placement Problems.8. With detail explanation classify the placement algorithms9. Explain the following Simulation Based Placement Algorithms: a) Simulated Annealing b) Simulated Evolutionc) Force Directed Placement10.Explain the following Partitioning Based Placement Algorithms11.Explain the following in-detail: a) Cluster Growth b) Quadratic Assignment c) Resistive Network Optimization

d) Branch-and-Bound Technique

12.Explain the concept of Performance Driven Placement.


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Subject: CMOS Mixed Signal Circuit Design

Reference Books:

UNITS:I

PART A Question

1. With neat sketch explain the following basic building blocks of switched-capacitor circuit: a) Op-Amps b)Capacitors c) Switches d) Non-overlapping Clocks

2. With relevant equations explain Resistor Equivalence of a Switched Capacitor circuit.3. What is the equivalent resistance of a 5 pF capacitance sampled at a clock frequency of 100 kHz?4. With neat circuit diagram explain the concept of Parasitic-Sensitive Integrator5. With neat circuit diagram explain the concept of Parasitic-Insensitive Integrators

PART B Question

1. Explain the Signal-Flow-Graph Analysis of Parasitic-Insensitive Integrators.2. With necessary equations explain the concept of Noise In Switched-Capacitor Circuits3. With neat sketch explain First-Order Filters and its signal flow graph analysis.4. Find the capacitance values needed for a first-order switched-capacitor circuit such that its 3-dB point is at

10 kHz when a clock frequency of 100 kHz is used. It is also desired that the filter have zero gain at 50 kHz

and the dc gain be unity. Assume CA = 10 pF

5. Find the capacitance values C3 needed for a first-order low-pass switched-capacitor filter that has C1 = 0 anda pole at the 1/64th sampling frequency using the approximate equations. The low-frequency gain should be

unity.6. With neat sketch explain the following concepts in first order filters: a) Switch sharing b) fully differentialamplifiers

7. With relevant circuit diagrams explain the concept of Biquad filters.


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Subject: CMOS Mixed Signal Circuit Design

Reference Books:

UNITS:II

PART A Question

1. With relevant information explain the concept of PLL2. If the output swing of the XOR in below fig is V0 volts, what is the gain of the circuit as a phase detector? Plot

the input-output characteristic of the PD

3. Explain the basic PLL topology? Implement the PLL using CMOS topology4. A PLL incorporates a VCO and PD having the characteristics shown in the fig.. explain what happens as the

input frequency varies in the locked condition.

5. Explain the concept of dynamics of PLL and linear model of basic PLL


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PART B Question

1. A cellular telephone incorporates a 900 MHz phase-locked loop to generate the carrier frequencies. IfLPF=2X(20 kHz) and the output frequency is to be changed from 901MHz to 901.2 MHz, how long does

the PLL output frequency take to settle within 100 Hz of its final value?

2. Suppose a type-I PLL experiences a frequency step at t=0. Calculate the change i n the phase error.3. Explain in-detail the concept of charge pump PLLs4. Explain the concept of Phase frequency detector and charge pump.5. Explain whether a master-slave D flip-flop can operate as a phase detector or a frequency detector. Assume

the flip-flop provide differential outputs.6. Determine the width of the narrow reset pulses that appear in the QB waveform in fig

7. With neat sketch explain Basic charge pump PLL8. With neat circuit diagram explain the following; a) PFD/CP non idealities b) Jitter in PLLs9. With relevant circuit diagrams explain the concept of Delay Locked Loops


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Subject: Design for Testability

Reference Books:

UNITS:I

PART A Question

1. With an example, explain the testing philosophy.2. Explain in-detail role of testing in VLSI realization process.3. Explain the concept of Digital and Analog VLSI Testing4. Explain the following VLSI Technology testing limitations: a) Rising Chip Clock Rate s b) ATE Cost c) EMI5. Explain the concept of fault modeling and explain the following terms in detail: a) Defects b) Faults c) Errors6. Distinguish functional and structural testing.7. Briefly explain various levels of fault models

PART B Question

1. Explain the following fault models in-detail: a) Assertion fault b) behavioral fault c) branch fault d) bridgingfault e) bus fault f) cross point fault.

2. Explain the following fault models in-detail: a) Defect oriented fault b) Delay fault c) functional fault d) Gate-delay fault e) Hyperactive fault f) Initialization fault

3. Explain the following fault models in-detail: a) Instruction fault b) intermittent fault c) Line delay fault d)Logical faults e) Memory faults f) multiple faults

4. Explain the following fault models in-detail: a) Non classical fault b) Oscillation fault c) Parametric fault d)Path delay fault e) pattern sensitive fault f) permanent fault

5. Explain the following fault models in-detail: a) Physical fault b) Pin fault c) PLA fault d) IDDQ fault e) Racefault f) Redundant fault

6. Explain the following fault models in-detail: a) segment delay fault b) Structural faults c) Stuck at fault d)stuck open and stuck short fault e) transistor fault f) transition fault g) untestable fault

7. With an example Single stuck at fault.8. With relevant equation explain the concept of Fault equivalence9. With relevant information explain the concept of Equivalence of single stuck at fault.10.Explain the concept of Fault Dominance and Checkpoint Theorem.


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Subject: Design for Testability

Reference Books:

UNITS:II

PART A Question

1. With an example, explain the concept of simulation for Design Verification2. With an example, explain the concept of Simulation for Test Evaluation3. Explain in-detail the following Modeling of Circuits for Simulation: a) Modeling Levels and Types of

Simulators b) Hierarchical Connectivity Description c) Gate-level Modeling of MOS Networks d) Modeling

Signal States e) Timing

PART B Question

1. With detailed explanation discuss the following Fault Simulation Algorithms: a) Serial Fault Simulation b)Parallel Fault Simulation

2. With detailed explanation discuss the following Fault Simulation Algorithms: a) Deductive Fault Simulation b)Concurrent Fault Simulation

3. With detailed explanation discuss the following Fault Simulation Algorithms: a) Roth's TEST-DETECTAlgorithm b) Differential Fault Simulation

4. With detailed explanation discuss the following Algorithms for True-Value Simulation: a) Compiled-CodeSimulation b) Event-Driven Simulation


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Subject: Digital Signal Processors and Architectures

Reference Books:

UNITS:I

PART A Question

1. With neat sketch explain the digital signal processing system.2. Explain in detail the sampling process.3. With relevant equations explain Discrete Time Sequences.4. With relevant equations explain the following: a) Discrete Fourier Transform b) Fast Fourier Transform.5. Explain the concept of Digital filters also explain the following: a) Finite Impulse Response (FIR) filter b)

Infinite Impulse Response (IIR) filter.

6. With sufficient consideration design the following filters : a) FIR filter b) IIR Filter7. Explain in detail the decimation and interpolation for DSP operations.

PART B Question

1. Determine the periods for the periodic sequences: a) e-jn/8 b) e-jn3/82. For FIR filter y(n)=[x(n)+x(n-1)+ x(n-2)]/3 determine the a) system function, b) magnitude response

function, c) phase response function, d) impulse response e) step response, f) poles and zeros

3. For IIR filter H(z)=

determine the a) magnitude response function, b) phase response function,

c) impulse response, d) step response and e) poles and zeros

4. Determine the low pass filter cutoff frequency that must be used to decimate to reduce the sampling ratefrom 8 KHz to 4 KHz.

5. The signal sequence x(n)=[0 2 4 6 8] is interpolated using the interpolation filter sequence bk=[0.5 1 0.5] andthe interpolation factor is 2. Determine the interpolated sequence y(m).

6. Explain the following number formats for signals and coefficients in DSP systems: a) Fixed Point Formatb)Double Precision Fixed Point format c) Floating-Point format d) Block Floating Point format.

7. Explain briefly the concept of dynamic range and precision.8. Explain the following sources of Error in DSP Implementations: a) A/D Conversing Errors b) DSP

Computational errors c) D/A Conversion errors.

9. Explain the concept of Compensating Filter with an examples


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Subject: Digital Signal Processors and Architectures

Reference Books:

UNITS:II

PART A Question

1. Explain the concept of Basic Architectural Features of Digital signal processors with an example.2. With neat sketch explain the following DSP computational Building blocks: a) Multiplier b) Shifter c)Multiply

and accumulate (MAC) unit d) Arithmetic Logic Unit.

3. With necessary diagram explain Bus architecture and Memory.

PART B Question

1. Explain the following data addressing capabilities with an example: a) Immediate addressing mode b)Register addressing mode c) Direct addressing mode e) Indirect addressing mode f)Special Addressing

Modes g) Bit reversed addressing mode.

2. Briefly describe the concept of Address Generation Unit.3. Explain the following programmability and Program execution in DSP Implementations: a) Program Control

b) Program Sequencer.

4. Explain the following Speed issues in DSP architectures: a) Hardware Architecture b) Parallelism c) Pipeliningd) System Level Parallelism and Pipelining.

5. Briefly discuss the external interfacing features of DSP architectures


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Subject: System On Chip Architecture

Reference Books:

UNITS:I

PART A Question

1. Briefly discuss the overview of System Architecture.2. Explain in detail the basic components of the system3. Discuss hardware and software programmability vs performance.4. Briefly describe the functional view of the processor.5. With neat sketch explain simple Sequential Processor.6. Explain in-detail the model of pipelined processor, also explain the Instruction timing in a pipelined

processor.

7. Briefly describe the concept of ILP (Instruction level parallelism)8. With neat sketch explain the model of super scalar processor9. Briefly explain the VLIW processor model.

PART B Question

1. With neat sketch explain the concept involved in the SIMD Architectures (Array and Vector Processors).2. Briefly describe the memory and addressing in SOC3. Briefly describe the Architecture of Memory in soc4. Briefly describe the concept of Memory for SOC operating system.5. With neat sketch explain the system level interconnection schemes: a) Bus based approach b) Network on

chip approach.

6. Explain in detail SOC design approach.7. Briefly discuss the system architecture and complexity issues for SOC8. Discuss the possible arrangement of addressing the TLB9. Find an actual VLIW instruction format. Describe the layout and the constraints on the program in using the

applications in a single instruction.

10.Design validation is important SOC design consideration. Find several approaches specific to SOC designs.Evaluate each from the perspective of a small SOC vendor.

11.Find two new VLIW DSPs. Determine the maximum number of operations issued in each cycle and themakeup of the operations (number of integer, floating point, branch, etc). what is the started maximum

performance(operations per second) ? find out how this number was computed.12.Find (from the internet) two new, large FPGA parts. Determine the number of logic blocks ( configurable logic

blocks[CLBs]), the minimum cycle time, and the maximum allowable power consumption. What soft

processors are supported?


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Subject: System On Chip Architecture

Reference Books:

UNITS:II

PART A Question

1. Briefly describe how processor can be select for SOC design.2. With examples describe the following: a) Soft Processors b) general core path processor selection c)

compute core path processor selection

3. With relevant information explain the basic concepts in processor architecture.4. Explain in-detail the basic concepts in processor Micro-architecture.5. Briefly discuss the basic elements in instruction handling.6. Explain the following buffers: a) Mean Request Rate buffers b) Fixed or Maximum Request Rate.

PART B Question

1. Explain the following : a) Reducing the cost of branches b) Branch Target Buffers (BTBs)2. Explain the concept of branch prediction, also explain the following dynamic branch predictions: a) Binomial

b) Two-Level Adaptive c) combined methods.

3. Explain the concept of more robust processors.4. With neat sketch explain vector processors and vector instruction extensions.5.With detail explanation, explain the concept of VLIW processors.6.With relevant information explain the concept of superscalar processors

M.tech VLSI SEM II MID I ImportantQuestions

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