MP&MC Unit IV

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UNIT IV

PIC MICROCONTROLLERS

OVERVIEW OF PIC MICROCONTROLLER

PIC stands for Peripheral Interface Controller given by Microchip Technology to identify its single-chip

microcontrollers. These devices have been very successful in 8-bit microcontrollers. The main reason is that

Microchip Technology has continuously upgraded the device architecture and added needed peripherals to the

microcontroller to suit customers' requirements.

The architectures of various PIC microcontrollers can be divided as follos.

Low - end PIC Architectures:

Microchip PIC microcontrollers are available in various types. !hen PIC microcontroller MC" as

first available from #eneral Instruments in early $%8&'s the microcontroller consisted of a simple processor

e(ecuting $)-bit ide instructions ith basic I*+ functions. These devices are ,non as lo-end architectures.

They have limited program memory and are meant for applications requiring simple interface functions and

small program data memories. ome of the lo-end device numbers are

$)C/00

$1C/0

$1C/&/

Mid range PIC Architectures

Mid range PIC architectures are built by upgrading lo-end architectures ith more number of peripherals

more number of registers and more data*program memory. ome of the mid-range devices are

$1C10

$1C20$13820

Program memory type is indicated by an alphabet.

C 4 5P6+M

3 4 3lash6C 4 Mas, 6+M

Popularity of the PIC microcontrollers is due to the folloing factors.

$. peed7 arvard 9rchitecture 6IC architecture $ instruction cycle 4 : cloc, cycles.

). Instruction set simplicity7 The instruction set consists of ;ust .

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it causes PIC to resetA hence malfunction is avoided.9 atch dog timer =user programmable> resets the processor if the softare*program ever malfunctions

and deviates from its normal operation.

:. PIC microcontroller has four optional cloc, sources.

o

Bo poer crystalo Mid range crystal

o igh range crystal

o 6C oscillator =lo cost>.

/. Programmable timers and on-chip 9C.

1. "p to $) independent interrupt sources.

2. Poerful output pin control =)/ m9 =ma(.> current sourcing capability per pin.>

8. 5P6+M*+TP*6+M*3lash memory option.

%. I*+ port e(pansion capability.

$&. 3ree assembler and simulator support from Microchip at .microchip.com

CPU Architecture:

The CP" uses arvard architecture ith separate Program and @ariable =data> memory interface. This

facilitates instruction fetch and the operation on data*accessing of variables simultaneously.

3ig.:.$ CP" 9rchitecture of PIC microcontroller

PIC Meor! Organi"ation:

PIC microcontroller has $< bits of program memory address. ence it can address up to 8, of program

memory. The program counter is $


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ignored. imilarly hile addressing :, of memory $) bits are required. ence the M? of the program

counter is ignored.

3ig:.). Program Memory map

The program memory map of PIC$1C2:9 is shon in 3ig :.). +n reset the program counter is cleared andthe program starts at &&. ere a 'goto' instruction is required that ta,es the processor to the mainline program.

!hen a peripheral interrupt that is enabled is received the processor goes to &&:. 9 suitable branching to

the interrupt service routine =I6> is ritten at &&:.

#ata eor! $Register %i&es':

ata Memory is also ,non as 6egister 3ile. 6egister 3ile consists of to components.

$. #eneral purpose register file =same as 69M>.). pecial purpose register file =similar to 36 in 8&/$>.

3ig :.< ata Memory map

The special purpose register file consists of input*output ports and control registers. 9ddressing from&& to 33 requires 8 bits of address. oever the instructions that use direct addressing modes in PIC to

address these register files use 2 bits of instruction only. Therefore the register ban, select =6P&> bit in the

T9T" register is used to select one of the register ban,s.

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3ig :./ ?asic 9rchitecture of PIC $1C2:9

The basic architecture of PIC$1C2:9 is shon in fig :./. The architecture consists of Program

memory file registers and 69M 9B" and CP" registers. It should be noted that the program Counter is $< -

bit and the program memory is organiEed as $: - bit ord. ence the program Memory capacity is 8, ( $: bit.5ach instruction of PIC $1C2:9 is $: - bit long. The various CP" registers are discussed here.

CPU registers $registers coon&! used ! the CPU'

! the or,ing register is used by many instructions as the source of an operand. This is similar to

accumulator in 8&/$. It may also serve as the destination for the result of the instruction e(ecution. It is an 8 -

bit register.

3ig.:.1 ! 6egister

STATUS Register

The T9T" register is a 8-bit register that stores the status of the processor. This also stores carry Eero and

digit carry bits.

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T9T" - address &


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3ig :.8 chematic of ho PCB is loaded from PCB9T

Progra Counter Stac4

9n independent 8-level stac, is used for the program counter. 9s the program counter is $


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3ig :.% 6egister 3ile Map

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Port Structure and Pin Con)iguration o) PIC +0C6,A

9s mentioned earlier there is a large variety of PIC microcontrollers. oever the midrange

architectures are idely used. +ur discussion ill mainly confine to PIC$1C2:9 hose architecture has mostof the required features of a mid-range PIC microcontroller. tudy of any other mid-range PIC microcontroller

ill not cause much variation from the basic architecture of PIC $1C2:9.

PIC $1C2:9 has / I*+ Ports. 5ach port is a bidirectional I*+ port. In addition they have the folloingalternate functions.

In addition to I*+ pins there is a Master clear pin =MCB6> hich is equivalent to reset in 8&/$.

oever unli,e 8&/$ MCB6 should be pulled lo to reset the micro controller. ince PIC$1C2:9has

inherent poer-on reset no special connection is required ith MCB6 pin to reset the micro controller onpoer-on.

There are to @pins and to @pins. There are to pins =+C$ and +C)> for connecting the

crystal oscillator* 6C oscillator. ence the total number of pins ith a $1C2:9 is


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INSTRUCTION SET

7uide&ines )ro Microchi3 Techno&og!

3or riting assembly language program Microchip Technology has suggested the folloing guidelines.$. !rite instruction mnemonics in loer case. =e.g. movf>

). !rite the special register names 69M variable names and bit names in upper case. =e.g. PCB 6P&

etc.>

Instruction Set:

The instruction set for PIC$1C2:9 consists of only > e(pect the fto be replaced by the name of a special purpose register =e.g. P+6T9> or the name of a 69M variable =e.g.

G"M$> hich serves as the source of the operand. 'f' stands for file register. The 3=!> parameter is thedestination of the result of the operation. It should be replaced by7

3 if the destination is to be the source register.

! if the destination is to be the or,ing register =i.e. 9ccumulator or ! register>.

The it oriented instructions also e(pect parameters =e.g. btfsc f b>. ere 'f' is to be replaced by the

name of a special purpose register or the name of a 69M variable. The 'b' parameter is to be replaced by a bitnumber ranging from & to 2.

3or e(ample7

F equ )

btfsc T9T" F

F has been equated to ). ere the instruction ill test the F bit of the T9T" register and ill s,ip the ne(tinstruction if F bit is clear.

The &itera& instructions require an operand having a ,non value =e.g. &9> or a label that represents a

,non value.

3or e(ample7

G"M equ &9 A 9ssigns &9 to the label G"M = a constant >movl G"M A ill move &9 to the ! register.

5very instruction fits in a single $:-bit ord. In addition every instruction also e(ecutes in a single

cycle unless it changes the content of the Program Counter. These features are due to the fact that PIC micro

controller has been designed on the principles of 6IC =6educed Instruction et Computer> architecture.

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Instruction set:

Mnemonics escriptionInstruction

Cycles

bcf f b Clear bit b of register f $

bsf f b et bit b of register f $

clr Clear or,ing register ! $

clrf f Clear f $

movl , Move literal ',' to ! $

movf f Move ! to f $

movf f 3=!> Move f to 3 or ! $

sapf f 3=!> ap nibbles of f putting result in 3 or ! $

andl , 9nd literal value into ! $

andf f 3=!> 9nd ! ith 3 and put the result in ! or 3 $

andf f 3=!> 9nd ! ith 3 and put the result in ! or 3 $

iorl , inclusive-+6 literal value into ! $

iorf f 3=!> inclusive-+6 ! ith f and put the result in 3 or ! $

(orl , 5(clusive-+6 literal value into ! $

(orf f 3=!> 5(clusive-+6 ! ith f and put the result in 3 or ! $

addl , 9dd the literal value to ! and store the result in ! $

addf f 3=!> 9dd ! to f and store the result in 3 or ! $

subl , ubtract the literal value from ! and store the result in ! $

subf f 3=!> ubtract f from ! and store the result in 3 or ! $

rlf f 3=!>Copy f into 3 or !A rotate 3 or ! left through the carrybit

$

rrf f 3=!> Copy f into 3 or !A rotate 3 or ! right through the carrybit

$

btfsc f bTest 'b' bit of the register f and s,ip the ne(t instruction if

bit is clear$ * )

btfss f bTest 'b' bit of the register f and s,ip the ne(t instruction if

bit is set$ * )

decfsE f 3=!>ecrement f and copy the result to 3 or !A s,ip the ne(t

instruction if the result is Eero$ * )

incfcE f 3=!>Increment f and copy the result to 3 or !A s,ip the ne(t

instruction if the result is Eero$ * )

goto label #o to the instruction ith the label JlabelJ )

call label#o to the subroutine JlabelJ push the Program Counter

in the stac,)

retrun6eturn from the subroutine P+P the Program Counterfrom the stac,

)

retl ,6etrun from the subroutine P+P the Program Counterfrom the stac,A put , in !

)

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retie6eturn from Interrupt ervice 6outine and re-enable

interrupt)

clrdt Clear !atch og Timer $

sleep #o into sleep* stand by mode $

nop Go operation $

Encoding o) instruction:

9s has been discussed each instruction is of $:-bit long. These $:-bits contain both op-code and the

operand. ome e(amples of instruction encoding are shon here.

Example-1:

c) )8 Clear 'b' bit of register 'f'

+perands7 & K f K $)2

& K b K 2

5ncoding7

The instruction is e(ecuted in one instruction cycle i.e. : cloc, cycles. The activities in various cloc, cycles

are as follos.

Example-2:

goto 9 #o to label ',' instruction

+perand7 & K D K )&:2 =$$-bit address is specified> +peration7 D PC L$&7&

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ince this instruction requires modification of program Counter it ta,es to instruction cycles for e(ecution.

N-Cycle activities are shon as follos.

I.O Port Con)iguration

#iscussion on I.O 3orts o) PIC+0C6,A:

PIC$1C2:9 has five I*+ ports. Port-? Port-C and Port- have 8 pins each. Port-9 and Port-5 have 1

and < pins respectively. 5ach port has bidirectional digital I*+ capability. In addition these I*+ ports are

multiple(ed ith alternate functions for the peripheral devices on the microcontroller. In general hen a

peripheral is enabled that pin may not be used as a general purpose I*+ pin. 5ach port latch has a

corresponding T6I =Tri-state 5nable> register for configuring the port either as an input or as an output. The

port pins are designated by the alphabet 6 folloed by the respective port =viE. 9 ? C or 5> and the pin

number. 3or e(ample Port-9 pins are named as 69& 69$ etc.

Port-A

Port-9 pins 69&-69< and 69/ are similar. These pins function =alternate function> as analog inputs to

the analog-to-digital converter.

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3ig :.$$ 69&-69< and 69/ pin of Port-9

The structure of Port-9 pins 69&-69< and 69/ is shon in the figure. T6I9 register decides

hether the port-pin is configured as an input or as an output =digital> pin. etting a T6I9 register bit puts the

corresponding output driver in high impedance mode. In this mode the pin can be used as a digital or analog

input. Clearing a bit in the T6I9 register puts the contents of the data latch on the selected pins i.e. the pinfunctions as a digital output. Pins 69&-69 and 69/ have current sourcing capability of )/m9.

The alternate function of 69: pin is Timer-& cloc, input =T&CDI>. 69: pin is an open drain pin and

hence requires e(ternal pull-up hen configured as output pin. It is shon in the folloing figure.

3ig :.$) 69: pin ConfigurationConfiguration of Port-9 pinsExample 7 et 69&-69< as outputs and 69: - 69/ as inputs.

bcf T9T" 6P& A elect ?an,-&

clrf P+6T9 A Clears the data latch

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bsf T9T" 6P& A elect ?an,-$

movl .

5ach port pin has a ea, internal pull-up that can be enabled by clearing bit of +PTI+G register

=bit-2>. !hen a pin is configured in the output mode the ea, pull-up is automatically turned off. Internal

pull-up is used so that e can directly drive a device from the pins.

3ig :.$< Pins 6?&-6?< of Port-?

Configuration of Port-? pinsExample 7 et 6?&-6?< as outputs 6?:-6?/ as inputs 6?2 as output.

bcf T9T" 6P&

clrf P+6T?bsf T9T" 6P&

movl 2&

TIMER COMPARE AND CAPTURE MODE

O*er*iew o) Tier Modu&es7

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PIC $1C2:9 has three modules viE. Timer-& Timer-$ and Timer-). Timer-& and Timer-) are 8-bit

timers. Timer-$ is a $1-bit timer. 5ach timer module can generate an interrupt on timer overflo.

Tier- O*er*iew:

The timer-& module is a simple 8-bit "P counter. The cloc, source can be either the internal cloc, =fosc*

:> or an e(ternal cloc,. !hen the cloc, source is e(ternal the Timer-& module can be programmed to

increment on either the rising or falling cloc, edge. Timer-& module has a programmable pre-scalar option.This pre-scalar can be assigned either to Timer-& or the !atch dog timer but not to both.

The Timer-& Counter sets a flag T&I3 =Timer-& Interrupt 3lag> hen it overflos and can cause an

interrupt at that time if that interrupt source has been enabled =T&I5 4 $> i.e. timer-& interrupt enable bit 4 $.

OPTION Register Con)iguration7

+ption 6egister =9ddr7 8$> Controls the pre-scalar and Timer -& cloc, source. The folloing+PTI+G register configuration is for cloc, source 4 fosc*: and no !atchdog timer.

Tier- use without 3re-sca&ar

Internal cloc, source of f osc *:. =5(ternal cloc, source if selected can be applied at 69:*T+CDI input at

P+6T9>.

The folloing diagram shos the timer use ithout the pre-scalar.

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3ig:.$: Timer - & operation ithout pre-scalar

Tier- use with 3re-sca&ar:

The pre-scalar can be used either ith the Timer-& module or ith the !atchdog timer. The pre-scalar

is available for Timer-& if the pre-scalar assignment bit P9 in the +PTI+G register is &. Pre-scalar is a

programmable divide by n counter that divides the available cloc, by a pre-specified number before applying

to the Timer-& counter.

3ig :.$/ Timer - & ith pre-scalar

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Tier - + Modu&e

Timer $ module is a $1-bit timer*counter consisting of to 8-bit registers =TM6$ and TM6$B> hich

are readable and ritable. The TM6$ register pair =TM6$7TM6$B> increments from &&&& to 3333 and

rolls over to &&&&. The TM6$ interrupt if enabled is generated on overflo hich sets the interrupt flag bitTM6$I3 =bit-& of PI6$ register>. This interrupt can be enabled*disabled by setting*clearing TM6$ interrupt

enable bit TM6$I5 =bit-& of the PI5$ register>.

The operating and control modes of Timer$ are determined by the special purpose register T$C+G.

@arious bits of T$C+G register are given as follos7-

3ig :.$1 T$C+G 6egister

TM6$ +G7 Timer$ +G bit

& 4 stops Timer $A $ 4 5nables Timer $ TM6$C 7 Timer $ Cloc, source elect ?it$ 4 5(ternal Cloc, =6C+*T$++*T$CDI>

& 4 Internal Cloc, = > 7 Timer $ 5(ternal Cloc, Input ynchroniEation ?it=@alid if TM6$C 4 $>

$ - o not synchroniEe

& - ynchroniEe

T$+C5G7 +scillator enable control bit$ 4 +scillator is enabled

& 4 +scillator is shut off

Timer $ Input Cloc, Pre-scalar

Se&ect its Pre-sca&ar Va&ue

T+C9PS+ T+C9PS

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$ $ $78

$ & $7:

& $ $7)

& & $7$

3ig :.$2 +peration of Timer $

Timer $ can operate in one of the to modes

9s a timer =TM6$C 4 &>. In the timer mode Timer $ increments in every instruction cycle. The timer

$ cloc, source is . ince the internal cloc, is selected the timer is alays synchroniEed and thereis no further need of synchroniEation.

9s a counter =TM6$C 4 $>. In the counter mode e(ternal cloc, input from the pin 6C+*T$CDI isselected.

Reading and writing Tier +

6eading TM6$ and TM6$B from Timer $ hen it is running from an e(ternal cloc, source have to

be done ith care. 6eading TM6$ or TM6$B for independent 8 - bit values does not pose any problem.

!hen the $1-bit value of the Timer is required the high byte =TM6$> is read first folloed by the lo byte

=T6$lB>. It should be ensured that TM6$B does not overflo =that is goes from 33 to &&> since T6$as read. This condition is verified by reading TM6$ once again and comparing ith previous value of

TM6$.

E;a3&e Progra

6eading $1bit of free running Timer $

movf TM6$ A read high byte

movf TMP A store in TMP

movf TM6$B A read lo bytemovf TMPB A store in TMPB

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movf TM6$ ! A read high byte in !

subf TMP ! A subtract $ st read ith ) nd readbtfsc T9T" F A and chec, for equality goto ne(t A

A if the high bytes differ then there is an overflo

A read the high byte again folloed by the lo bytemovf TM6$ ! A read high byte

movf TMP

movf TM6$B ! A read lo bytemovf TMPBne(t 7 nop

Tier 2 O*er*iew

3ig :.$8 chematic diagram shoing operation of Timer )

Timer ) is an 8 - bit timer ith a pre-scalar and a post-scalar. It can be used as the P!M time base for

P!M mode of capture compare P!M =CCP> modules. The TM6) register is readable and ritable and is

cleared on device reset.

The input cloc, = fosc*:> has a pre-scalar option of $7$ $7: or $7$1 hich is selected by bit & and bit $ ofT)C+G register respectively.

The Timer ) module has an 8bit period register =P6)>. Timer-) increments from && until it is equal toP6) and then resets to && on the ne(t cloc, cycle. P6) is a readable and ritable register. P6) is initialiEed

to 33 on reset.

The output of TM6) goes through a :bit post-scalar =$7$ $7) to $7$1> to generate a TM6) interrupt by

setting TM6)I3.

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3ig :.$% The T)C+G 6egister

Interru3t Logic in PIC +0C6,A

3ig :. )& chematic diagram shoing the interrupt logic for PIC

PIC $1C2:9 microcontroller has one vectored interrupt location =i.e. &&&:> but has $) interrupt

sources. There is no interrupt priority. +nly one interrupt is served at a time. oever interrupts can be

mas,ed.

CCP Modu&es

Ca3ture . Co3are .P1M $CCP' Modu&es:

PIC$1C2:9 has to CCP Modules. 5ach CCP module contains a $1 bit register =to 8-bit registers>

and can operate in one of the three modes viE. $1-bit capture $1-bit compare or up to $&-bit Pulse !idthModulation =P!M>. The details of the to modules =CCP$ and CCP)> are given as follos.

CCP+ Modu&e:

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CCP$ Module consists of to 8-bit registers viE. CCP6$B =lo byte> and CCP6$ =high byte>. The

CCP$C+G register controls the operation of CCP$ Module.

CCP2 Modu&e:

CCP) Module consists of to 8 bit registers viE. CCP6)B =Bo byte> and CCP6) =high byte>. The

CCP$C+G register controls the operation of CCP) Module.

?oth CCP$ and CCP) modules are identical in operation ith the e(ception of the operation of special event

trigger.

The folloing table shos the timer resources for the CCP Mode.

CCP Mode Timer "sed

Capture

Compare

P!M

Timer $

Timer $

Timer )

CCP$C+G 6egister =9ddress $2 >

CCP)C+G 6egister is e(actly similar to CCP$C+G register. CCP)C+G 6egister address is $. CCP$C+G

controls CCP module$ here as CCP)C+G controls CCP Module).

?it /-:7

CCP$0 CCP$O7 P!M least significant bits. These bits are of no use in Capture mode. In P!M Mode thesebits are the to B?s of the P!M duty cycle. The eight M?s are found in CCP6$B. Thus the P!M mode

operates in $&-bit mode.

CCP$0 CCP$O7 P!M least significant bits. These bits are of no use in Capture mode. In P!M Mode these

bits are the to B?s of the P!M duty cycle. The eight M?s are found in CCP6$B. Thus the P!M modeoperates in $&-bit mode.

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&$$&4Capture mode every : th rising edge

&$$$4Capture mode every $1 th rising edge$&&&4Compare mode set output on match =CCP$I3 bit is set>

$&&$4Compare mode clear output on match =CCP$I3 bit is set>

$&$&4Compare mode generate softare interrupt on match =CCP$I3 bit is set CCP$ pin unaffected>$&$$4Compare mode trigger special event =CCP$I3 bit is setACCP$ resets Tmr$A CCP) resets TM6$ and

starts 9* conversion if 9* module is 5nabled>

$$004P!M mode.

CAPTURE MO#E $CCP+':

Capture Mode captures the $1-bit value of TM6$ into CCP6$7CCP6$B register pair in response to anevent occurring on 6C)*CCP$ pin. Capture Mode for CCP) is e(actly similar to that of CCP$.

9n event on 6C)*CCP$ pin is defined as follos7

5very falling edge

5very rising edge.

5very : th rising edge.

5very $1 th rising edge.

9s mentioned earlier this event is decided by bit .

). Timer $ should be operated from the internal cloc, =fosc*:> i.e. timer mode or in synchroniEed counter

mode.

Co3are Mode $CCP+'

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Compare mode for CCP) is similar to that of CCP$ e(cept that in special event trigger mode CCP$

resets TM6$ only hereas CCP) resets TM6$ and starts 9* conversion if 9* module is enabled.

In compare mode the $1-bit CCP6$ register value is compared against TM6$ register pair =TM6$

and TM6$B> value. !hen a match occurs the 6C)*CCP$ pin is driven high or driven lo or remains

unchanged as decided by CCP$C+GL ?oth CCP$ and

CCP) have similar operation in P!M mode. ere e ill discuss P!M ith respect to CCP$.

In P!M mode the CCP$ pin produces up to a $&-bit resolution Pulse !idth Modulation =P!M> output.

6C)*CCP$ pin should be configured in the output mode by clearing T6ICL) bit.

The schematic bloc, diagram of CCP$ module in P!M mode is shon in the figure.

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3ig :.)< P!M +peration

It can be noted that P6) =Period 6egister 8 bit> decides the P!M period here CCP6$B =8-bits> and

CCP$C+G L/7: =)-bits> decide the P!M duty cycle. !hen TM6) equals P6) the 6 latch is set and

6C)*CCP$ pin is pulled high. In the same time TM6) is cleared and the duty cycle value available in

CCP6$B is latched to CCP6$. CCP6$ CCP$C+G L/7: decide the duty cycle and hen this $&-bit

equals the TM6)) pre-scalar or N-bits the 6 latch is set and 6C)*CCP$ pin is driven lo.

WATCH DOG TIMER:

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R(PU - PORT( Pu&&-u3 ena&e it

o $ - P+6T? pull-up resistors are disabledA and

o & - P+6T? pins can be connected to pull-up resistors.

INTE#7 - Interru3t Edge Se&ect it

o $ - Interrupt on rising edge of IGT pin =&-$>A and

o & - Interrupt on falling edge of IGT pin =$-&>.

TCS - TMR C&oc4 Se&ect it

o $ - Pulses are brought to TM6& timer*counter input through the 69: pinA and

o & - Internal cycle cloc, =3osc*:>.

TSE - TMR Source Edge Se&ect it

o $ - Increment on high-to-lo transition on TM6& pinA and

o & - Increment on lo-to-high transition on TM6& pin.

PSA = Pre-sca&ar Assignent it

o $ Pre-scalar is assigned to the !TA and

o & Pre-scalar is assigned to the TM6& timer*counter.

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PS28 PS+8 PS = Pre-sca&ar Rate Se&ect it

o Pre-scalar rate is ad;usted by combining these bits

9s seen in the table :-$ the same combination of bits gives different pre-scalar rate for the

timer*counter and atch-dog timer respectively.

To se&ect ode:

Timer mode is selected by the T&C bit of the +PTI+GH65# register =T&C7 &4timer $4counter>A

!hen used the pre-scalar should be assigned to the timer*counter by clearing the P9 bit of the

+PTI+GH65# register. The pre-scalar rate is set by using the P)-P& bits of the same registerA and

!hen using interrupt the #I5 and TM6&I5 bits of the IGTC+G register should be set.

To easure tie:

6eset the TM6& register or rite some ell-,non value to itA

5lapsed time =in microseconds hen using quartE :ME> is measured by reading the TM6& registerA

and

The flag bit TM6&I3 of the IGTC+G register is automatically set every time the TM6& register

overflos. If enabled an interrupt occurs.

To count 3u&ses:

The polarity of pulses are to be counted is selected on the 69: pin are selected by the T+5 bit of the

+PTI+G register =T&57 &4positive $4negative pulses>A and

Gumber of pulses may be read from the TM6& register. The pre-scalar and interrupt are used in the

same manner as in timer mode.

SYNCHRONOUS SERIAL PORT

Most of mid range PIC microcontrollers include a ynchronous erial Port =P> Module. The discussion

in this section is relevant to PIC$1C2:9 only. P Module section can be configured in either of the folloingto modes.

erial Peripheral Interface =PI>

Inter Integrated Circuit =I)C>

5ither of these modes can be used to interconnect to or more PIC chips to each other using a minimal

number of ires for communication. 9lternatively either can be used to connect a PIC microcontroller to a

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peripheral chip. !hen I )C mode is selected the peripheral chip must also have an I )C interface. +n the other

hand the PI mode provides the cloc, and serial data lines for direct connection to shift registers. This leads toincreased I*+ interface capability and an arbitrary number of I*+ devices can be connected to a PIC

microcontroller. PI can also achieve data rate significantly higher than I)C. ?oth the communication methods

are synchronous i.e. the data transfer is synchroniEed ith an e(plicit cloc, signal.

To special purpose registers control the synchronous serial port =P> operations. These registers are7

PC+G =ynchronous erial Port Control 6egister> 9ddress7 $:

PT9T=ynchronous erial Port status 6egister> 9ddress7 %:

Seria& Peri3hera& Inter)ace $SPI' Port-C three pins viE. 6C/*+ 6C:*I and 6C


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3ig :.)/ PI Master * lave Connection

The schematic diagram of PI Master*lave connection is shon in the figure.

Tiing diagra )or data trans)er in >Master ode>7

PI3 interrupt flag is cleared by the user softare if already in the set mode. The interrupt is enabled.

9ny rite to P?"3 initiates the data transfer i.e. transmission and reception. The cloc, pulses =8 cloc,

pulses> are output through CD pin. The data is received through I. !hen CDP4$ =PC+GL:> data

changes at + at negative cloc, transition and is read through I at positive cloc, transition. The idle state

of cloc, is high. If CDP4& data appears at + at positive cloc, transition and is read through I at negativecloc, transition. The idle state of the cloc, is lo. These are shon in the folloing diagrams.

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=i> Timing diagram for CDP4$

=ii> Timing diagram for CDP4&

3ig :.)1 Timing iagram under PI mode

SERIAL PERIPHERAL INTERFACE

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I.O Port E;3ansion using Seria& Peri3hera& Inter)ace $SPI'

Though PI is a serial communication interface it can be used to realiEe multiple output parallel ports

and multiple input parallel ports. !e ill consider this realiEation of an output parallel port and an input port

separately.

Parallel +utput Port 6ealiEation 9 parallel 8-bit output port can be realiEed through PI ith the help of

a shift register chip =2:C/%/> as shon in 3ig )/.$. 6C/*& pin outputs serial data hile 6C ith a shift register

!hen an 8-bit data is ritten to P?"3 the data is shifted out of 6C/*& pin. !ith CDP 4 $ the

data is stable at the positive transition but changes at the negative transition. The shift shifts the data at the

positive cloc, transition. 9fter 8 cloc, pulses all 8-bits are shifted in the shift register. The completion of data

transfer is indicated by PI3 interrupt flag becoming ' $' . The interrupt service routine ma,e 6C: ' $' thus

latching the 8-bit data to the output of the shift register. The configuration of various registers are shon in 3ig

:.)8

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Port con)igurations

3ig :.)8 @arious 6egister Configurations

Para&&e& In3ut Port Rea&i"ation

9 shift register =2:C$1/> is connected to the PIC microcontroller as shon in 3ig :.)%. Pin 62 is

configured as an output and is used to load 8-bit data to the shift register. 9 dummy rite to P?"3 initiates

data transfer. ata bit is read into 6C:*I at the negative cloc, transition =CDP 4 &> here the data bit is

stable. ata is shifted in the shift register at the position cloc, transition as shon in the timing diagram. 9fter

the completion of data transfer PI3 interrupt flag goes high. Thereafter the 8-bit data can be read by reading

P?"3.

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3ig :.)% 6ealiEation of an 8-bit parallel input port ith PIC in PI mode.

Port con)igurations 3ig :.


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I2C BUS OPERATION .

I )C stands for Inter-Integrated circuit. I )C communication is a to ire bi-directional interface for

connecting one or more master processors ith one or more slave devices such as an 55P6+M 9C 69M

BC display 9C etc. I )C interface requires to open drain I*+ pins viE. 9 =erial ata> and CB

=erial Cloc,>.

The reason for open drain connection is that the data transfer is bi-directional and any of the devices

connected to the I )C bus can drive the data line =9>. The serial cloc, line =CB> is usually driven by the

master. ince 9 and CB pins are open drain pins e(ternal pull-up resistances are required for operation of

I )C bus.

9 typical I)C bus shoing the connection of multi-master and multi-slave configuration is shon in the

folloing figure.

3ig :.. The folloing diagram shos the data

communication pattern having 8 data bits and one ac,noledgement bit.

3ig :.


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). ata in 9 line is stable during cloc, =CB> high. 9 ne bit is initiated at the negative cloc,

transition after a specified hold time.

is driven by the master.

:. 9n ac,noledgement bit =&> is driven by the receiver after the end of reception. If the receiver does not

ac,noledge 9 line remains high =$>.

I)C bus transfer consists of a number of byte transfers ithin a T96T condition and either another

T96T condition or a T+P condition. uring the idle state hen no data transfer is ta,ing place both 9

and CB lines are released by all the devices and remains high. !hen a master ants to initiate a data transfer

it pulls 9 lo folloed by CB being pulled lo. This is called T96T condition. imilarly hen the

processor ants to terminate the data transfer it first releases CB =CB becomes high> and then 9. This is

called a T+P condition. T96T and T+P conditions are shon in the diagram as follos.

3ig :. bit is sent by the master. If 6* bit is

'&' the folloing byte =after the ac,noledgement bit> is ritten by the master to the addressed slave

peripheral. If 6* 4$ the folloing byte =after the ac,noledgement bit> has to be read from the slave by the

master.

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9fter sending the 2-bit address of the slave the master sends the address =usually 8 bit> of the internal

register of the slave herefrom the data has to be read or ritten to. The subsequent access is automatically

directed to the ne(t address of the internal register.

The folloing diagrams give the general format to rite and read from several peripheral internal

registers.

3ig :. bit indicates hether the data is to be ritten by the master or read by the master. If

6* is $ the subsequent data are to be read by the master. If 6* 4 & the subsequent data are to be ritten by

the master to the addressed slave. It has to be noted that the slave address is sent first folloing a 'start'

condition. The addressed slave responds by ac,noledging and gets ready for data transfer. If data has to be

read from a specific address of the slave device the master sends the 2-bit address of the slave first folloing a

'start' condition. 6* bit is sent as 'lo'. The addressed slave ac,noledges by pulling the 9CD line lo. The

master then sends the 8-bit internal address of the slave from hich data has to be read. The slave

ac,noledges. ince 6* bit as initially & the master is in the rite mode. To change this to read mode the

'start' condition is again generated folloed by 2-bit address of the slave ith 6* 4 $. The slave

ac,noledges. The slave then sends data from previously specified internal address to the master. The master

ac,noledges by pulling 9CD bit lo. The data transfer stops hen the master does not ac,noledge the data

reception and a 'stop' condition is generated.

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UNIT V

MICROCONTROLLER (ASE# S?STEMS #ESI7N

LCD INTERFACING

There are basically to types of BCs as far as the interfacing technique is concerned7 parallel BCs

and serial BCs. Parallel BCs =e.g. itachi ::28& series> are connected to the microcontroller circuitry

such that the data is transferred to the BC unit using more than one data line and four or eight data lines are

very common. erial BCs are connected to a microcontroller using only one data line and data is usually

transferred to the BC using the standard 6-)


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.

@ss is the & @ supply or ground. The @ pin should be connected to the positive supply. 9lthough the

manufacturers specify a / @ d.c. supply the modules illusually or, ith as lo as < @ or as high as 1 @.

Pin < is named as @55 and this is the contrast control pin. This pin is used to ad;ust the contrast of the

device and it should be connected to a variable voltage supply. 9 potentiometer is usually connected beteen

the poer supply lines ith its iper arm connected to this pin so that the contrast can be ad;usted. This pin

can be connected to ground for most applications.

Pin : is the 6egister elect =6> and hen this pin is B+! data transferred to the display is treated as

commands. !hen 6 is I# character data can be transferred to and from the module.

Pin / is the 6ead*!rite =6*!> line. This pin is pulled B+! in order to rite commands or character

data to the BC module. !hen this pin is I# character data or status information can be read from the

module.

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Pin 1 is the 5nable =5> pin hich is used to initiate the transfer of commands or data beteen the

module and the microcontroller. !hen riting to the display data is transferred only on the I# to B+!

transition of this line. !hen reading from the display data becomes available after the B+! to I#

transition of the enable pin and this data remains valid as long as the enable pin is at logic I#.

Pins 2 to $: are the eight data bus lines =+ to 2>. ata can be transferred beteen the

microcontroller and the BC unit using either a single 8-bit byte or as to :-bit nibbles. In the latter case only

the upper four data lines =: to 2> are used. The :-bit mode has the advantage that feer I*+ lines are

required to communicate ith the BC.

Connecting the LC# to the icrocontro&&er

The BC module is assumed by default to be connected to Port ? of a PIC microcontroller. The pin

connections are as follos7

LC# odu&e Port ( 3ins

6 ?$

6*! ?)

5 ? InitialiEe the display to $ line

BC=-)> InitialiEe the display to ) lines

BC=)/2> Clear display and home the cursor

BC=)/8> 6eturn the cursor to home position

BC=)/1$)8G> 6eturn cursor to position G on line $ here G 4 & is the first character position on line $

BC=)/1$%)G> 6eturn cursor to position G on line ) here G 4 & is the first character position on line )

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ANALOG TO DIGITAL CONVERTER

There are numerous ays in hich an analog signal can be converted to digital form. The 9nalog to

igital convertors can be classified into to general groups based on the conversion technique.

+ne technique involves comparing a given analog signal ith the internally generated equivalent signal.

This group includes successive appro(imation counter and flash-type converters. The second techniqueinvolves changing an analog signal into time or frequency and comparing these ne parameters against ,non

values.

Thus group includes integrator converters and @oltage to 3requency converters. The trade-off beteen

the to techniques is based on accuracy @s speed. The successive appro(imation and the flash type are faster

but generally less accurate than the integrating and the @oltage to 3requency converters. 3urthermore the flash

type is e(pensive and difficult to design for high accuracy.

The most commonly used 9* converters are successive appro(imation and integrating type 9*

converters. The successive appro(imation 9* converters are used in applications such as data loggers andinstrumentation here conversion speed is important. +n the other hand integrating type converters are used

in applications such as digital meters panel meters and monitoring systems here the conversion accuracy is

critical.

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SUCCESSIVE APPRO@IMATION A.# CONVERTERS:

3igure shos the bloc, diagram of a successive appro(imation 9* converter. The ma;or elements of

this converter are a *9 converter the successive appro(imation =96> and the comparator. ere the output of

*9 converter is compared ith the measured voltage. The digital input to the 9C is generated using

successive appro(imation method. !hen the 9C output matches the analog signal the input to the 9C is

the equivalent digital signal.

3irst bit < is turned +G and the output of the 9C is compared ith an analog signal. If the

comparator changes state indicating that the output generated by < is larger than the analog signal bit < is

turned +33 in the 96 and bit ) is turned +G. The process continues until the input reaches bit &.

SUCCESSIVE APPRO@IMATION TEC5NIUE:

uccessive appro(imation process can be shed through either softare or hardare approach. In

softare approach an 9* converter is designed using 9* converter and the microprocessor plays the role of

the comparator and the 96. ?loc, diagram for successive appro(imation 9C is shon in 3ig.

MP&MC Unit IV

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