MOS Physics

7/31/2019 MOS Physics

1/34

PHYSICS OF THE MOS TRANSISTOR

1. Introduction:A field effect transistor (FET) operates as a conducting semiconductor channel with two ohmic

contacts the source and the drain where the number of charge carriers in the channel iscontrolled by a third contact the gate. In the vertical direction, the gate-channel-substratestructure (gate junction) can be regarded as an orthogonal two-terminal device, which is either aMOS structure or a reverse-biased rectifying device that controls the mobile charge in the channelby capacitive coupling (field effect). Examples of FETs based on these principles are metal-oxide-semiconductor FET (MOSFET), junction FET (JFET), metal-semiconductor FET(MESFET), and hetero-structure FET (HFETs). In all cases, the stationary gate-channelimpedance is very large at normal operating conditions.

The most important FET is the MOSFET. In a silicon MOSFET, the gate contact is separatedfrom the channel by an insulating silicon dioxide (SiO2) layer. The charge carriers of theconducting channel constitute an inversion charge, that is, electrons in the case of a p-type

substrate (n-channel device) or holes in the case of an n-type substrate (p-channel device),induced in the semiconductor at the silicon-insulator interface by the voltage applied to the gateelectrode. The electrons enter and exit the channel at n+ source and drain contacts in the case ofan n-channel MOSFET, and atp+ contacts in the case of ap-channel MOSFET.

MOSFETs are used both as discrete devices and as active elements in digital and analogmonolithic integrated circuits (ICs). In recent years, the device feature size of such circuits hasbeen scaled down into the deep sub-micrometer range. Presently, the 0.13-m technology nodefor complementary MOSFET (CMOS) is used for very large scale ICs (VLSIs) and, within a fewyears, sub-0.1-m technology will be available, with a commensurate increase in speed and inintegration scale. Hundreds of millions of transistors on a single chip are used in microprocessorsand in memory ICs today.

CMOS technology combines both n-channel andp-channel MOSFETs to provide very low powerconsumption along with high speed. New silicon-on-insulator (SOI) technology may help achievethree-dimensional integration that is, packing of devices into many layers, with a dramaticincrease in integration density.

The current chapter presents a discussion on the physics of the MOS transistor. It focuses on theconduction in MOSFET in the different regimes. Since the scaling issues of MOSFET arebecoming increasingly important, scaling of MOS transistors are also discussed.

2. The MOS Capacitor:

It is important to understand the MOS capacitor in order to understand the behavior of the MOStransistor. Before we describe the MOS structure, it is useful to review the basic electrostatics asapplied to parallel plate capacitors. We shall then go on to analyze the MOS structure.

2.1 The Parallel Plate Capacitor:

The parallel plate capacitor consists of two parallel metallic plates of area A, separated by aninsulator of thickness ti and dielectric constant . If we place a charge Q on the upper plate, itattracts charges of opposite sign in the bottom plate, while repelling charges of the same sign. Ifthe bottom plate is connected to ground, the repelled charge flows to ground. Now the two


2/34

capacitor plates hold equal and opposite charge. This charge resides just next to the insulator oneither side of it as shown in figure 1.

Figure 1. Charging of a parallel plate capacitor

This is true, whatever the quantity or sign of charge placed on the upper plate. The inducing andinduced charges are always separated by the thickness of the insulator, ti. Therefore this structurehas a constant capacitance given by:

it

AC

= (1)Since there are no charges inside the dielectric, the electric field in the insulator is constant andthe electrostatic potential changes linearly from one plate to the other.

2.2 Qualitative Analysis of the MOS capacitor:

Figure 2 shows the structure of a MOS capacitor.

Figure 2. Structure of a MOS capacitor

In a MOS capacitor, we replace the lower plate by a semiconductor. Unlike a metal, asemiconductor can have charges distributed in its bulk. For the sake of an example, let usconsider a P type semiconductor (Si) doped to 1016 atoms /cm3. As we know, holes outnumberelectrons in this semiconductor by an extremely large factor. If we place a negative charge on the

upper plate, holes will be attracted by this charge, and will accumulate near the silicon-insulatorinterface. This situation is analogous to the parallel plate capacitor and thus, the capacitance willbe the same as that for a parallel plate capacitor. If, however, we place a positive charge on theupper plate, negative charges will be attracted by it and positive charges will be repelled. In a Ptype semiconductor, there are very few electrons. The negative charge is provided by the ionizedacceptors after the holes have been pushed away from them. But the acceptors are fixed in theirlocations and cannot be driven to the edge of the insulator. Therefore, the distance between theinduced and inducing charges increases - so the capacitance is lower as compared to the parallelplate capacitor. As more and more positive charge is placed on the upper plate, holes from a


3/34

thicker slice of the semiconductor are driven away, and the incremental induced charge is fartherfrom the inducing charge. Thus the capacitance continues to decrease. This does not, however,continue indefinitely. We know from the law of mass action that as hole-density reduces, theelectron density increases. At some point, the hole-density is reduced and electron densityincreased to such an extent that electrons now become the majority carriers near the interface.This is called inversion. Beyond this point, more positive charge on the upper plate is answered

by more electrons in the semiconductor. But the electrons are mobile, and will be attracted to thesilicon insulator interface. Therefore, the capacitance quickly increases to the parallel plate value.Figure 3 shows the capacitance versus voltage (C-V) characteristics of a typical MOS capacitor.

Figure 3. C-V characteristics

2.3 Interface charge of MOS capacitor:

The induced interface charge in the MOS capacitor is closely linked to the shape of the electronenergy bands of the semiconductor near the interface. At zero applied voltage, the bending of theenergy bands is ideally determined by the difference in the work functions of the metal and thesemiconductor. This band bending changes with the applied bias and the bands become flat whenwe apply the so-called flat-band voltage given by

( )

q

EEX

q

V FcsmsmFB+

=

=

..(2)

where m and s are the work functions of the metal and the semiconductor, respectively, Xs isthe electron affinity for the semiconductor,Ec is the energy of the conduction band edge, and EFis the Fermi level at zero applied voltage. The various energies involved are indicated in Figure1.3, where we show typical band diagrams of a MOS capacitor at zero bias, and with the voltageV= VFB applied to the metal contact relative to the semiconductoroxide interface.


4/34

Figure 4. Band diagrams of MOS capacitor (a) at zero bias and (b) with an applied voltage

equal to the flat-band voltage.

At stationary conditions, no net current flows in the direction perpendicular to the interface owingto the very high resistance of the insulator layer (however, this does not apply to very thin oxidesof a few nanometers, where tunneling becomes important). Hence, the Fermi level will remainconstant inside the semiconductor, independent of the biasing conditions. However, between thesemiconductor and the metal contact, the Fermi level is shifted by qVEE FsFm = . Hence, wehave a quasi-equilibrium situation in which the semiconductor can be treated as if in thermalequilibrium.

A MOS structure with a p-type semiconductor will enter the accumulation regime of operationwhen the voltage applied between the metal and the semiconductor is more negative than the flat-band voltage (VFB< 0 in Figure 4). In the opposite case, when V >VFB, the semiconductoroxideinterface first becomes depleted of holes and we enter the so-called depletion regime. Byincreasing the applied voltage, the band bending becomes so large that the energy differencebetween the Fermi level and the bottom of the conduction band at the insulatorsemiconductorinterface becomes smaller than that between the Fermi level and the top of the valence band. Thisis the case indicated for V = 0V in Figure 4. Carrier statistics tells us that the electronconcentration then will exceed the hole concentration near the interface and we enter theinversion regime. At still larger applied voltage, we finally arrive at a situation in which theelectron volume concentration at the interface exceeds the doping density in the semiconductor.

This is the strong inversion case in which we have a significant conducting sheet of inversioncharge at the interface.

2.4 Quantitative Analysis of MOS Capacitor:

Let us consider a one dimensional representation of the MOS structures as shown in figure 5below.


5/34

Figure 5. One dimensional representation of the MOS structure

The origin is assumed to be at the silicon-oxide interface and the positive x direction is into thebulk of silicon. Using a one dimensional analysis, we want to relate the semiconductor charge tothe applied gate voltage. In a practical case, there is a potential difference between two dissimilarmaterials in contact. Also, the silicon - oxide interface will have some fixed charge sitting there.However, we consider the ideal case first, where there is no built in contact potential between thesemiconductor and the metal, and there is no interface charge.

2.4.1 The ideal case:Let the back surface of Si be at zero potential and the voltage applied to the gate terminal is Vg.Let the electrostatic potential at any point x be denoted by )(x and let the potential at thesilicon-oxide interface be s . We construct a Gaussian box passing through the interface andextending to +1 as shown in figure 6.

Figure 6. Analysis of the ideal case

According to Gauss law, the integral of the outward pointing Dr

around the box should be equalto the charge contained inside. The only boundary where D

ris non zero is the one passing

through the interface. Therefore, total charge in silicon is given by,

ox

gs

oxtott

VAreaQ

=

....(3)

If we define QSito be the semiconductor charge per unit area, and COX to be the parallel plate

capacitance per unit area, we get

OX

Sisg

C

QV = .(4)

Thus, the surface potential and the applied gate voltage can be related to each other. If the surfacepotential is known, we can evaluate the semiconductor charge by integrating the Poisson'sequation in the semiconductor, once.We can write the Poisson's equation in the semiconductoras:


6/34

= Dr

......(5)

)(22

npNNq ADSi +=

+

.....(6)

Since the electrostatic potential is dependent only on x, we can change partial derivatives to totalderivatives.

Thus,

dx

dE

dx

d

dx

d

dx

d=

=

2

2

......(7)

whereEis the electric field. Changing the variable from x to, we get,

)(21 2

2

2

Ed

d

d

dEE

dx

d

d

dE

dx

dE

dx

d

==== ...(8)

LetKT

qu

= .

)(2

)(2

1 222

2

E

KT

qE

d

d

dx

d==

.(9)

The right hand side of the Poisson's equation represents the charge density. In the absence of anapplied voltage, this must be zero everywhere. Therefore,

0)( 00 =++

npNNq AD ..(10)where 0p and 0n represent the hole and electron density in the absence of an applied

field. Therefore, 00 pnNN AD =+

Substituting equation (8) in equation (5), we get,

)]([)(2 00

2 nnppqEdu

d

KT

q Si =

= 112)(2 00

0

0

02nn

pn

ppKTpE

dud

KTq

Si

Si

....(11)

Using,)()(

0FF

KT

q

iKT

q

enenn

== and)()(

0FF

KT

q

iKT

q

epepp

== , (where in and

ip refers to intrinsic carrier concentration at temperature T), we get,

( )

= 11

2)(

0

002 uu

Si

ep

ne

KTpE

du

d

This can be integrated from x = (where E = 0 and u = 0) to x to give

( )

=

2

0 0 0

002 112

)(E u

uu

Si

due

p

ne

KTpEd

( )

+= ue

p

nue

KTpE

uu

Si

112

0

002

( )

+= ue

p

nue

KTpE uu

Si

112

0

00


7/34

( )

+= ue

p

nue

qpE uu

Si

112

0

00

(12)

Thus, displacement ( )

+== ue

p

nue

pqED uuSiSi 11

2

0

00

r.(13)

This equation permits us to calculate D (x

uSi

=

) from u. In fact if u is very small, the

exponentials in u can be expanded to second order. The first two terms cancel with 1 and u,

leaving up

npq

x

u

Si

+

0

00 1

m .(14)

If we take n0 S )

A somewhat more accurate expression for depletion charge accounts for slightly lower charge

density at the edge of the depletion region by subtractingq

KTfrom S . Hence,

)(2q

KTqNXqNQ SSiADAdepl == ..(16)

Calculated values for the total semiconductor charge per unit area (i.e. inclusive of depletion andmobile charge) and just the depletion charge per unit area have been plotted in figure 7 for a P


8/34

type semiconductor doped to 1016/cm3. For small positive surface potential, the totalsemiconductor charge contains only depletion charge. However, beyond a surface potential near2fF, the total charge exceeds the depletion charge very rapidly. This additional charge is due tomobile minority carriers (in this case electron).

Figure 7. Semiconductor charge as a function of gate voltage

2.4.2 The practical case:A practical MOS structure will differ from the ideal case assumed above in a few respects. Thereis a built-in potential difference between the metal used and silicon, due to the difference betweentheir work functions. This shifts the relationship between VG and S . Also, there is a fixed oxidecharge which resides essentially at the silicon oxide interface. Thus, the total charge in theGaussian box includes this fixed charge and the semiconductor charge. These two non-idealitiescan be accounted for by modifying the relationship between VG and S to be

OX

OXSi

SMSGC

QQV ++= ..(17)

Figure 8 shows the surface potential as a function of applied voltage for a MOS capacitor withoxide thickness of 22.5 nm, substrate doping of 1016/cm3, oxide charge of 4X1010q andaluminium as the gate metal.

Figure 8. Surface potential as a function of gate voltage


9/34

The surface potential changes quite slowly as a function of gate voltage in the accumulation andinversion regions. The absolute value of semiconductor charge has been plotted as a function ofapplied gate voltage in figure 9. (The charge is actually negative for positive gate voltages).

Figure 9. Absolute semiconductor charge as a function of gate voltage

As one can see, for small positive gate voltages, the entire semiconductor charge is depletioncharge. As the voltage exceeds a threshold voltage, the total charge becomes much larger than thedepletion charge. The excess charge is provided by mobile electron charges. This is the inversionregion of operation, where electrons become the majority carriers near the surface in a p typesemiconductor. Notice that the depletion charge is practically constant in this region. This regionbegins when the surface potential exceeds F2 .

3. The MOS Transistor:

Inversion converts a p type semiconductor to n type at the surface. We can use this fact toconstruct a transistor. We place semiconductor regions strongly doped to N type on either side ofa MOS capacitor made using P type silicon. Figure 10 shows the structure of a MOS transistor.

Figure 10. Structure of the MOS transistor

Now if we try to pass a current between these two N regions when inversion has not occurred, weencounter series connected NP and PN diodes on the way. Whatever the polarity of the voltageapplied to pass current, one of these will be reverse biased and practically no current will flow.

However, after inversion, the intervening P region would have been converted to N type. Nowthere are no junctions as the whole surface region is n type. Current can now be easily passedbetween the two n regions. This structure is an n channel MOS transistor. PMOS transistors canbe similarly made using P regions on either side of a MOS capacitor made on n type silicon.


10/34


11/34

Figure 11(c)

Figure 11(d)

Figure 11(e)


12/34

Figure 11(f)

Figure 11. Fluid dynamic analogy of MOS transistor

[All voltages measured with respect to source](a) Transistor operating in cut off

(b) Channel strongly inverted but no current since VD=0

(c) Transistor operating in active region

(d) Transistor operating in saturation region

(e) Transistor operating in weak inversion but no current since VD=0

(f) Transistor operating in weak inversion with current flowing since VD>0

In figure 11(a), VG is lower than VT. The channel is cut off and no transport occurs betweensource and drain. Let us now lower the handle such that VG becomes greater than VT. The channelis now filled with water. This is analogous to strong inversion in a MOS transistor.Communication between source and drain is now possible but no flow of water is observed in the

steady state since VD=0 as shown in figure 11(b). If we now drain out water from the draintank, then VD becomes greater than zero and a steady flow of water is observed as shown in figure11(c). The flow increases as VD is increased further, until saturation is reached. Once thesaturation is reached (as shown in figure 11(d)), any further increase in VDdoes not affect theflow. In fact, the water enters slowly from the source and as its approaches the drain, moves fasterin order to maintain a fixed flow, despite the fact that there is very little water in the channel nearthe drain. Again one can make an analogy to the simplified picture of transistor operation insaturation.

It is evident from the figure that for a given VD, the flow rate increases if VG is increased anddecreases if VG is decreased. If VG is decreased to such an extent that the top surface of the pistonis slightly above the source surface, then the direct flow water is prevented. Water molecules can

still flow from left to right. This can be visualized if one considers the diffusion of water vapor.This situation corresponds to weak inversion of MOSFET. The vapor concentration is maximumat the water surface and decreases exponentially as one moves vertically away from it. If thelevels of water in the two tanks are same, then the rate of diffusion of water vapor from the sourceto drain and the rate of diffusion from the drain to source becomes same in the steady state. Thusthere is no resultant flow of water in absence of a positive VD. This situation is depicted in figure11(e). However, if the water surface in the drain tank is lower as compared to that in the sourcetank, then at any horizontal plane above the piston, the vapor concentration will be decreasing asone goes from source to drain along the channel. Water vapor thus diffuses from left to right,


13/34

carrying a minute current, even if the position of the piston surface is slightly above the watersurface. However, a very small drop in the position of the piston can greatly increase the current,since the vapor concentration over the source at points slightly above the level of piston willincrease exponentially. One might thus expect an exponential dependence of current on the pistonposition and this is truly analogous to the case of a MOS transistor, in which the drain currentexhibits an exponential dependence on the gate to source voltage in the sub-threshold regime.

4. I-V characteristics of the MOS transistorA quantitative derivation of the current-voltage characteristics of the MOS device is complicatedby the fact that it is inherently a two dimensional device. The vertical field due to the gate voltagesets up a mobile charge density in the channel region as seen in figure 8. The horizontal field dueto source-drain voltage causes these charges to move, and this constitutes the drain current.Therefore, a two dimensional analysis is required to calculate the transistor current, which can bequite complex. However, reasonably simple models can be derived by making several simplifyingassumptions.

4.1 A simplified MOS ModelWe make the following simplifying assumptions based on the Shichman and Hodges model:

1. The vertical field is much larger than the horizontal field. Then, the resultant field isnearly vertical, and the results derived for the one dimensional analysis for the MOScapacitor can be used to calculate the point-wise charge density in the channel. This isknown as the gradual channel approximation. Accurate numerical simulations haveshown that this approximation is valid in most cases.

2. The source is shorted to the bulk.3. The gate and drain voltages are such that a continuous inversion region exists all the way

from the source to the drain.4. The depletion charge is constant along the channel.5. The total current is dominated by drift current.6. The mobility of carriers is constant along the channel.7. All voltages are measure with respect to source. Thus GV indicates gate to source

voltage, DV indicates drain to source voltage and BV indicates bulk to sourcevoltage.

Figure 12 shows the co-ordinate system used for evaluating the drain current. The x axis pointsinto the semiconductor, the y axis is from source to the drain and the z axis is along the width ofthe transistor. The origin is at the source end of the channel. We represent the channel voltage asV(y), which is 0 at the source end and VD at the drain end. We assume the current to be made upof just the drift current. Since we are carrying out a quasi two dimensional analysis, all variablesare assumed to be constant along the z axis. Let n(x, y) be the concentration of mobile carriers(electrons for an n channel device) at the position (x, y) (for any z).

Figure 12. Cartesian Coordinate System used for analyzing the MOS transistor


14/34

The drift current density at a point is

J = number of carriers X charge per carrier X velocity

=y

yVqyxn

)()(),(

yyVqyxn

= )(),( ....................................................................................................................(18)

Integrating the current density over a semi-infinite plane at the channel position y (as shown inthe figure 10) will then give the drain current. Hence,

= =

=0 0

)(),(

x

W

z

D dzdxy

yVyxqnI

Since there is no dependence on z, the z integral just gives a multiplication by W. Therefore,

=

=0

),()(

x

D dxyxny

yVqWI

The value ofn(x, y) is non zero in a very narrow channel near the surface. We can assume that

y

yV

)( is constant over this depth. Then,

=

=0

),()(

x

D dxyxny

yVqWI

But

=

=0

)(),(x

n yQdxyxnq , where )(yQn is the electron charge per unit area in the

semiconductor at point y in the channel. ( )(yQn is negative, of course). Therefore,

)()(

yQ

y

yVWI nD

= ...(19)

Integrating the drain current along the channel gives,

=L L

nD dyy

yVyQWdyI

0 0

)()(

=DV

nD ydVyQWLI0

)()(

=DV

nD ydVyQL

WI

0

)()(

We now use the assumption that the surface potential due to the vertical field saturates around

F2 if we are in the inversion region. Therefore, the total surface potential at point yis FyV 2)( + . Now, by Gausss law and continuity of normal component of D at the interface,

)()( OXSiSMSGOX QQVC +=

+=

OX

OXFMSGOXSi

C

QyVVCQ 2)(

However, deplnSi QQQ +=


15/34

Hence, depletionSin QyQyQ += )()(

++=

OX

depletionOX

FMSGOXC

QQyVVC

)(2)( ..(20)

We have assumed the depletion charge to be constant along the channel. Let us define

OX

depletionOXFMST

CQQV )(2 ++=

Therefore, ))(()( yVVVCyQ TGOXn =

Thus =DV

TGOXD ydVyVVVL

WCI

0

)())((

( )

=

2

2D

DTGOXD

VVVV

L

WCI ...(21)

This derivation gives a very simple expression for the drain current in the active region of nchannel MOS transistor. However, it requires a lot of simplifying assumptions, which limit the

accuracy of this model. If we do not assume a constant depletion charge along the channel, wecan apply the depletion formula to get its dependence on V(y).We have, )2)((2 FSiAdepl yVqNQ += Then,

( ) )2)((22)()( FSiAOXFMSGOXn yVqNQyVVCyQ ++= which leads to

( ) ( )

+

+= 2

3232

222

32

22

FFD

OX

ASiDD

OX

OX

FMSGOXD VC

NqVV

C

QV

L

WCI

..(22)

This is a more complex expression, but gives better accuracy.

4.2 Modeling the saturation region:The treatment in the previous section is valid only if there is an inversion layer all the way fromthe source to the drain. For high drain voltage, the local vertical field near the drain is notadequate to take the semiconductor into inversion. Several models have been used to describe thetransistor behavior in this regime. The simplest of these defines a saturation voltage at which thechannel just pinches off at the drain end. The current calculated for this voltage by the abovemodels is then supposed to remain constant at this value for all higher drain voltages. The pinchoff voltage is the drain voltage at which the channel just vanishes near the drain end. Therefore, atthis point the gate voltage VG is just less than a threshold voltage above the drain voltage VD.Thus, at this point,

TGDsat VVV =

The current calculated at DsatV will be denoted as DSSI . Thus,( ) ( )

= 2221

TGTGOXD VVVVL

WCI

Thus,

( )221

TGOXD VVL

WCI = ..(23)


16/34

The drain current is supposed to remain constant at this VD independent value for all drainvoltages greater than TG VV .

4.2.1 The Early Voltage approach:

Assuming a constant current in the saturation region leads to an infinite output resistance. This

can lead to exaggerated estimates of gain from an amplifier. Therefore, we need a more realisticmodel for the transistor current in the saturation region. One of these is a generalization of themodel proposed by James Early for bipolar transistors. This model is not strictly applicable toMOS transistors. However, due to its numerical simplicity, it is often used in compact models forcircuit simulation.

A geometrical interpretation of the Early model states that the drain current increases linearly inthe saturation region with drain voltage, and if saturation characteristics for different gatevoltages are produced backwards, they will all cut the drain voltage axis at the same (negative)drain voltage point. The absolute value of this voltage is called the Early Voltage VE.

The current equations in saturation mode now become:

),( DsatGDDsat VVII =

EDsat

EDDsatD

VV

VVII

++

= , )( DsatD VV > .. ..(24)

Any model can be used for calculating the drain current for DsatD VV < . The value ofVDsat will bedetermined by considerations of continuity of the drain current and its derivative at thechangeover point from linear to saturation regime. For example, if we use the simple modeldescribed in equation (21),

)( DTGOXD

D VVVL

WC

V

I=

, )( DsatD VV ...(25)

And EDsat

Dsat

D

D

VV

I

V

I

+=

, )( DsatD VV ..(26)

Where

=

2)(

2Dsat

DsatTGOXDsat

VVVV

L

WCI

Equating R.H.S. of (25) and (26) we get,

+= 1

)(21

E

TGEDsat

V

VVVV

In practice, VE is much larger than )( TG VV . If we expand the above expression, we find that tofirst order the value of VDsat remains the same as the one used in the simple model - that is,

)( TG VV . Expansion to second order gives

( )

E

TG

TGDsatV

VVVVV

21 (27)

4.2.2 Simulation Model

Since the value of VDsat does not change substantially from the ideal saturation case, a simplerapproach can be tried. The drain current is calculated using the ideal saturation model and itsvalue is multiplied by a correction factor = (1 + VD) in saturation. This automatically assures


17/34

continuity of ID and its derivative. is a fit parameter, whose value is 1/VE. This approach is usedin SPICE, a popular circuit simulation program. Thus, the drain current equation in saturation

region becomes, ( ) )1(21 2

DTGOXD VVVL

WCI += ..(28)

The output characteristics of the MOS transistor indicating the three regions of operation is

shown in figure 13.

Figure 13. Output characteristics of a MOS transistor

The device operates in the cut off region for TG VV . In the cut off region, 0=DI . However,

for TG VV , the device conducts giving a non zero value of DI . If DTG VVV , the transistoroperates in the active region. DTG VVV , the transistor operates in the saturation region.

4.3 Body Effect:In the discussion in sections 4.1 and 4.2, we tacitly assumed that the source and bulk are tiedtogether, i.e. 0=BV . If the value of BV is raised, the two depletion regions under n+ regionsbecome deeper. To reach a similar depletion region depth under the channel, a larger GV valuethan before is needed. Electrons will start flowing into a significant extent into the channel only ifthat larger GV is reached. Looking into the same situation from a different angle, BV acts as areverse bias for the field induced junction formed by the strong inversion layer and body. Thus if

BV is raised, the depletion region of that junction will widen, uncovering more acceptor atomsand revealing their negative charge. Now fewer electrons will be needed in the inversion layer tobalance the gate charges. If it is desired to restore the number of electrons to what it was before

BV was raised, then GV will have to be increased. This effect of channel-body bias on theinversion level is called body effect or substrate-bias effect. Making the body bias more negativewith respect to the source, decreases the number of electrons, just as decreasing the gate potentialwould. For this reason, the body is sometimes called the back gate and the body effect is alsocalled the back gate effect.


18/34

It can be proved that for body effect, the threshold voltage of MOS transistor gets changedaccording to the following formula:

FFBTT VVV 220 ++= (29)

where is the bulk threshold parameter given by OX

ASi

C

Nq

2

= .4.3 Sub-threshold conduction:The discussion on MOSFET that has been done so far assumes that there is no conduction in thechannel below the threshold voltage. However, for gate-source voltages less than the extrapolatedthreshold voltage VTbut high enough to create a depletion region at the surface of the silicon, thedevice operates in weak inversion. In a weak inversion region, the channel charge is much lessthan the charge in the depletion region, and the drain current arising from the drift of the majoritycarriers is negligible. However, the total drain current in weak inversion is larger than that causedby drift because a gradient in minority carrier concentration causes diffusion current to flow. Inweak inversion region, an n-channel MOS transistor operates as an n-p-n bipolar transistor, wherethe source acts as emitter, the substrate as base and the drain as collector.

To analyze the conduction in the sub-threshold region, let us assume that the source and thesubstrate are both grounded and VD > 0. Then increasing the gate voltage VG increases the surfacepotential S which tends to reduce the reverse bias across the source substrate junction and to

exponentially increase the concentration of electrons in the p-type substrate at the source, )0(pn .For the np junction at the source, the concentration of electrons in the p-type substrate at thesource, )0(pn is given by

KT

q

pp

s

enn

0)0( = ..(30)

Similarly, the concentration of electrons in the p-type substrate at the drain, )(Lnp is given by

KTVq

pp

Ds

enLn)(

0)(

=

...(31)

The drain current due to diffusion of electrons in the substrate is:

L

nLnqADI

pp

nD

)0()( = ....(32)

where nD is the diffusion coefficient for electrons and A is the cross sectional area in whichcurrent flows. The area A is the product of the transistor width W and the thickness X of theregion in whichID flows. Putting equations (30) and (31) in (32), we get,

=

KT

qV

KT

q

pnD

Ds

eenDL

WXqI 10

(33)

In weak inversion, the surface potential is approximately a linear function of the gate sourcevoltage. Let us assume that the charge stored at the oxide silicon interface is independent of thesurface potential. Then, in weak inversion, changes in the surface potential s are controlled by

changes in gate voltage GV through a voltage divider between the oxide capacitance oxC and the

depletion region capacitancejsC . Therefore,


19/34

+==

+=

111

nCC

C

dV

d

OXjs

OX

G

s ..(3

4)

where,OX

js

C

Cn += 1 and

OX

js

C

C= . Separating variables and integrating equation (33), we get,

kn

VGs += ....(35)

where kis a constant. Equation (34) is valid only in the weak inversion region. WhenTG VV = with 0=SBV , fs 2= by the definition of threshold voltage. For TG VV > , the

inversion layer holds the surface potential nearly constant and equation (34) is not valid.Since, equation (34) is valid only for TG VV , hence equation (34) is rewritten as:

1kn

VV TGs +

= ..(36)

where n

V

kkT

+=1 . Substituting equation (35) into equation (32), we get,

=

KT

qV

nKT

VVq

KT

qk

pnD

DTG

eeenDL

WXqI 1

)(

0

1

..(37)

Figure 14 shows the I-V characteristics of a MOS transistor in the sub-threshold region.

Figure 14. I-V characteristics of a MOS transistor in the sub-threshold region

5. MOS Capacitances:For the simulation of dynamic events in MOSFET circuits, we also have to account forvariations in the stored charges of the devices. In a MOSFET, we have stored charges in thegate electrode, in the conducting channel, and in the depletion layers. Somewhat simplified,

the variation in the stored charges can be expressed through different capacitance elements, asindicated in Figure 15.

We distinguish between the so-called parasitic capacitive elements and the capacitiveelements of the intrinsic transistor. The parasitic capacitances include the overlap capacitancesbetween the gate electrode and the highly doped source and drain regions (COS and COD), thejunction capacitances between the substrate and the source and drain regions (CJS andCJD), and the capacitances between the metal electrodes of the source, the drain, and the


20/34

gate.

The semiconductor charges of the intrinsic gate region of the MOSFET are dividedbetween the mobile inversion charge and the depletion charge, as indicated in Figure 15. Inaddition, these charges are non uniformly distributed along the channel when drain- sourcebias is applied. Hence, the capacitive coupling between the gate electrode and the

semiconductor is also distributed, making the channel act as an RC transmission line. Inpractice, however, because of the short gate lengths and limited bandwidths of FETs, thedistributed capacitance of the intrinsic device is usually very well represented in terms ofa lumped capacitance model, with capacitive elements between the various intrinsicdevice terminals.

Figure 15. Intrinsic and parasitic capacitive elements of the MOSFET

In Meyers capacitance model, the distributed intrinsic MOSFET capacitance can be splitinto the following three lumped capacitances between the intrinsic terminals:

GBGD VVGS

GGS

V

QC

,

= GBGS VV

GD

GGS

V

QC

,

= GDGS VV

GB

GGS

V

QC

,

= ....(38)

where QG is the total intrinsic gate charge. The intrinsic MOSFET equivalent circuitcorresponding to this model is shown in Figure 16.


21/34

Figure 16. Large signal MOS equivalent circuit based on Meyers capacitance model

In general, the gate charge reflects both the inversion charge and the depletion charge and cantherefore be written as GdGiG QQQ += . However, in the drain current equation, the depletioncharge is ignored in strong inversion, except for its influence on the threshold voltage. Likewise,

in the Meyer capacitance model, the gate-source capacitance CGS and the gate-drain capacitanceCGD can be assumed to be dominated by the inversion charge. Here, we include gate-substratecapacitance CGB in the sub-threshold regime, where the depletion charge is dominant.

The contribution of the inversion charge to the gate charge is determined by integrating the sheetcharge density over the gate area, that is,

=L

TGGi dxxVVVQ0

)]([ ..(39)

We have,

D

TGOXnI

dVVVVCWdx )( = , which allows us to make a change of integration

variable fromx to V. Hence, we obtain for the non saturated regime,

==DV

TGDTGS

TGDTGSiTG

D

OXnGi

VVVV

VVVVCdVVVV

LI

CWQ

022

332

2

)()()()(

32)(

.....(40)

where COX is the total gate oxide capacitance and where we expressed ID using equation (21) andreplaced VDSby VGS VGD everywhere.

Using the above relationships, the following strong inversion, long-channel Meyer capacitancesare obtained:

( )

=

2

21

32

DTG

DTG

OXGSVVV

VVVCC ..(41)

( )

=

2

21

32

DTG

TG

OXGDVVV

VVCC ......(42)

0=GBC ...(43)The capacitances at saturation are found by replacing DsatD VV = in the above equations, that is,

OXGS CC 32

= .......(44)

0=GDC ...(45)0=GBC ...(46)

This result indicates that in saturation, a small change in the applied drain-source voltage does notcontribute to the gate or the channel charge, since the channel is pinched off. Instead, the entirechannel charge is assigned to the source terminal, giving a maximum value of the capacitanceCGS. Normalized dependencies of the Meyer capacitances CGS and CGD on bias conditions areshown in Figure 17.


22/34

Figure 17 Normalized strong inversion Meyer capacitances according to (40) to (45) versus

(a) drain-source bias and (b) gate-source bias.

In the sub-threshold regime, the inversion charge becomes negligible compared to the depletioncharge, and the MOSFET gate-substrate capacitance will be the same as that of a MOS capacitorin depletion, with a series connection of the gate oxide capacitance Ci and the depletioncapacitance Cd. The applied gate-substrate voltage VGB can be subdivided as follows:

OX

dep

sFBGBC

qVV += ................................................................................................................(47

)where VFB is the flat-band voltage, s is the potential across the semiconductor depletion layer

(i.e., the surface potential relative to the substrate interior), andOX

dep

C

q is the voltage drop

across the oxide. In the depletion approximation, the depletion charge per unit area depq is related

to s by sOXdep Cq = , where is the body effect parameter given byOX

ASi

C

qN

2= .

Using this relationship to substitute for s in (46), we get the total charge in the depletion regionas:

+==2

2 FBGBOXdepGd VVCWLqQ (48)

from which we get the following sub-threshold capacitances:

2

)(41

FBGB

OX

GBVV

C

C +

= .(49)

0=GSC ...(50)0=GDC ...(51)


23/34

Let us now consider the voltage dependent bulk-source and bulk-drain junction capacitances, CBDand CBS These junction capacitances are due to the depletion charge at the bulk-source and bulk-drain junctions. Each of these capacitances consists of a bottom part and a sidewall part. Thereason we need to distinguish between these is that the presence of the heavily doped channelstop region along the external perimeter of the source and drain makes the capacitance per unitarea very large over there. The sidewall capacitance is proportional to the perimeter along which

it exists. The constant of proportionality is a capacitance per unit of perimeter. This quantity canbe calculated from the knowledge of shapes and doping profiles involved. The bottom walljunction capacitance is given by:

m

BX

jb

BXjb

V

CAC

=

0

0

1

.

...(52)

where 0jbC is zero bias junction capacitance per unit area,Xis SorD accordingly as the terminal

concerned is the source or drain and m is the junction grading coefficient which is21

for a step

graded junction and 31 . 0jbC is given by:

00

12.

+

=DA

DASi

jbNN

NNqC , where 0 is the built in junction potential.

It is to be noted that the value of junction capacitances BXjbC ultimately depend on the external

bias voltage that is applied across the p-n junction. Since the terminal voltages of a MOSFETchange during its dynamic operation, accurate estimation of junction capacitances under transientconditions is quite complicated. The instantaneous values of all junction capacitances will alsochange accordingly. The problem of estimating capacitance values under changing bias

conditions can be simplified, if we calculate a large signal average junction capacitance instead,which is independent of bias potential. This equivalent large signal capacitance is defined asfollows:

=

=

=2

1

)(1)()(

1212

12V

V

j

jj

eq dVVCVVVV

VQVQ

V

QC (53)

Putting equation (51) in (52), we get,

( )

=

mm

jb

eqBXjb

VV

mVV

CAC

1

0

1

1

0

2

12

00 11)1(

...(54)

Here, the reverse bias voltage across the p-n junction is assumed to change from V1to V2. Hence,the equivalent capacitance eqBXjbC is always calculated for a transition between two voltagelevels. For the special case of step graded bulk to source and drain junction, equation (54)becomes

( )

=

0

1

0

2

12

00 112

VV

VV

CAC

j

eqBXjb ...(55)


24/34

Let us assume that the sidewall doping density is given by )(swNA . Then the zero bias junctioncapacitance per unit area is given by:

swDA

DASi

swAjNswN

NswNqC

00

1)()(

2

+

= , where sw0 is the built potential of the sidewall

junctions. Since, all the sidewalls in a typical diffusion structure have approximatelysame depth xj, therefore we can define zero bias sidewall junction capacitance per unitlength, swjC 0 given by jswAjswj xCC = 00 Thus, the equivalent sidewall junctioncapacitance is given by:

( )

=

0

1

0

2

12

0.0 112

VV

VV

CPC

swj

eqBXjsw ..(56)

An accurate modeling of the intrinsic capacitances associated with the gate region of FETsrequires an analysis of the charge distribution in the channel versus the terminal bias voltages.Normally, the problem is simplified by assigning the distributed charges to the various intrinsicterminals. Hence, the mobile charge QI of a MOSFET is divided into a source charge

IpS QFQ = and a drain charge IpD QFQ )1( = , where Fp is a partitioning factor. Thedepletion charge QBunder the gate is assigned to the MOSFET substrate terminal. The total gatecharge QG is the negative sum of these charges, that is, BDSBIG QQQQQQ == .Note that by assigning the charges this way, charge conservation is always assured. The netcurrent flowing into terminalXcan now be written as

=

==Y

YXYXY

Y

Y

Y

XXX

t

VC

t

V

V

Q

dt

dQI ..(57)

where is an adjustable parameter and the indicesXand Yrun over the terminals G, S,D, andB. In this expression, we have introduced a set of intrinsic capacitance elements CXY , the so-called trans-capacitances, defined by

Y

XXYXYV

QC

= (58)

where ),(1 YXXY = )(1 YX =+=

These are equivalent to the charge-based nonreciprocal capacitances introduced by Ward andDutton (1978) and by Ward (1981). The term nonreciprocal means that we have

YXXY CC = when X=Y . The elements CXXare called self-capacitances. CXYcontain informationon how much the charge QXassigned to terminalXchanges by a small variation in the voltage VYat terminal Y. To illustrate why CXYmay be different from CYX, assume a MOSFET in saturation.Then the gate charge changes very little when the drain voltage is perturbed since the inversion

charge is very little affected, making CGD small. However, ifVGis perturbed, the inversion chargechanges significantly and so does QD, making CDG large.

For the four-terminal MOSFET, the WardDutton description leads to a total of 16 trans-capacitances. This set of 16 elements can be organized as follows in a 4 4 matrix, a so-calledindefinite admittance matrix:


25/34

=

BBBDBSBG

DBDDDSDG

SBSDSSSG

GBGDGSGG

CCCC

CCCC

CCCC

CCCC

C ....(59)

Here, the elements in each column and each row must sum to zero owing to the constraintsimposed by charge conservation (which is equivalent to obeying Kirchoffs current law) and forthe matrix to be reference independent, respectively. This means that some of the trans-conductances will be negative, and of the 16 MOSFET elements, only 9 are independent. Thecomplete MOSFET large-signal equivalent circuit, including the 16 trans-capacitances, is shownin Figure 18.

Figure 18. Intrinsic large-signal MOSFET equivalent circuit including a complete set of

nonreciprocal and charge-conserving trans-capacitances

The simplified CVmodel by Meyer is obtained by taking derivatives of the total gate chargewith respect to the various terminal voltages. The Meyer capacitances can be viewed as a subsetof the WardDutton capacitances. Although charge conservation is not assured in the Meyermodel, the resulting errors in circuit simulations are usually small, but can in some cases lead to

serious errors. The unified trans-capacitances needed for the complete WardDutton model canbe obtained along the same lines as described for CGS and CDS. The accuracy of the modeldepends on the quality of the charge and current models used and on the partitioning of theinversion charge between the source and the drain terminal.

6. Short channel and narrow channel effects in MOS transistor:

A MOSFET device is considered to be short when the channel length is the sameorder of magnitude as the depletion-layer widths (xdD ,xdS) of the source and drain junction. As


26/34

the channel length L is reduced to increase both the operation speed and the numberof components per chip, the so-called short-channel effects arise.

6.1 Short channel effects:

The short-channel effects are attributed to two physical phenomena:1. The limitation imposed on electron drift characteristics in the channel,2. The modification of the threshold voltage due to the shortening channel length.

In particular five different short-channel effects can be distinguished:1. Drain-induced barrier lowering and punch through2. Surface scattering3. Velocity saturation4. Impact ionization5. Hot electrons6. Mobility degradation

6.1.1 The modification of the threshold voltage due to Short-Channel Effects (SCE)The equation giving the threshold voltage at zero-bias is

|2|212 FASiOX

FFBT NqC

VV

++= ...........................................................................(60)

The equation is accurate in describing large MOS transistors, but it collapses when applied tosmall-geometry MOSFETs. In fact that equation assumes that the bulk depletion charge is onlydue to the electric field created by the gate voltage, while the depletion charge near n+ sourceand drain region is actually induced by p-n junction band bending. Therefore, the amountof bulk charge the gate voltage supports is overestimated, leading to a larger VT than theactual value. The electric flux lines generated by the charge on the MOS capacitor gateelectrode terminate on the induced mobile carriers in the depletion region just under the gate.For short-channel MOSFETs, on the other hand, some of the field lines originating from thesource and the drain electrodes terminate on charges in the channel region. Thus, less gatevoltage is required to cause inversion. This implies that the fraction of the bulk depletion chargeoriginating from the p-n junction depletion and hence requiring no gate voltage, must besubtracted from the VT expression. Figure 19 shows the simplified geometry of the gate-induced bulk depletion region and the p-n junction depletion regions in a short channelMOS transistor.


27/34

Figure 19. Simplified geometry of the gate-induced bulk depletion region and the p-n

junction depletion regions in a short channel MOS transistor

It is to be noted that the bulk depletion region is assumed to have and asymmetric trapezoidalshape, instead of a rectangular shape, to represent accurately the gate-induced charge. Thedrain depletion region is expected to be larger than the source depletion region because thepositive drain-to-source voltage reversed-biases the drain- substrate junction. We recognize thata significant portion of the total depletion region charge under the gate is actually due to thesource and drain junction depletion, rather than the bulk depletion induced by the gate voltage.Since the bulk depletion charge in the short channel device is smaller than expected, the thresholdvoltage expression must be modified to account for this reduction:

00)(0 TTSCT VVV = ..(61)where VT0 is the zero-bias threshold voltage calculated using the conventional long-channelformula and AVT0 is the threshold voltage shift (reduction) due to the short-channel effect.

The reduction term actually represents the amount of charge differential between a rectangulardepletion region and a trapezoidal depletion region.

Let ALSandALDrepresent the lateral extent of the depletion regions associated with the sourcejunction and the drain junction, respectively. Then, the bulk depletion region chargecontained within the trapezoidal region is

|2|22

10 FASiDS

B NqL

LLQ

+= ....(62)

To calculateALSandALD, we will use the simplified geometry shown in figure 20.

Figure 20. Simplified geometry of the bulk depletion region associated with the drain


28/34

Here, xdS and xdD represent the depth of the p-n junction depletion regions associated with thesource and the drain, respectively. The edges of the source and drain diffusion regions arerepresented by quarter-circular arcs, each with a radius equal to the junction depth,xj. The verticalextent of the bulk depletion region into the substrate is represented byxdm. The junction depletionregion depths can be approximated by

( )02

+= DSA

Si

dD VqN

x ....(63)

and ( )02

A

Si

dSqN

x = .(64)

with the built in junction potential given by

=

20 lni

AD

n

NN

q

KT ....(65)

From figure 18, we find the following relationship between DL and the depletion regiondepths.222 )()( DjdmdDj Lxxxx ++=+

022 222 =++ dDjdDdmDjD xxxxLxL

+++= 1

212)( 222

j

dDjdDjdDdmjjD

x

xxxxxxxxL ..(66)

Similarly,

+ 1

21

j

dS

jSx

xxL ....(67)

Now, the amount of the threshold voltage reduction 0TV due to short-channel effects can befound as:

++

+= 1

211

21

2|2|2

10

j

dS

j

dDj

FASi

OX

Tx

x

x

x

L

xNq

CV ..(68)

The threshold voltage shift term is proportional toL

xj . As a result, this term becomes more

prominent for MOS transistors with shorter channel lengths, and it approaches zero for longchannel MOSFETs where jxL >> .

6.1.2 Drain induced barrier lowering and punch through:

The expressions for the drain and source junction widths are:

( )SBSiDSA

Si

dD VVqN

x ++= 2

..................................................................................................(69)

and


29/34

( )DBSiA

Si

dS VqN

x += 2

............................................................................................................(70)

where VSB and VDB are source-to-body and drain-to-body voltages.

When the depletion regions surrounding the drain extends to the source, so that the twodepletion layers merge (i.e., when xdS + xdD = L), punch through occurs. Punch through can beminimized with thinner oxides, larger substrate doping, shallower junctions, and obviously withlonger channels.

The current flow in the channel depends on creating and sustaining an inversion layer on thesurface. If the gate bias voltage is not sufficient to invert the surface (VGS


30/34

6.1.4 Velocity saturation:

The performance of short-channel devices is also affected by velocity saturation, which reducesthe transconductance in the saturation mode. At low Ey, the electron drift velocity vdein the

channel varies linearly with the electric field intensity. However, as Eyincreases above 104V/cm, the drift velocity tends to increase more slowly, and approaches a saturation value of

vde(sat)=107 cm/s around Ey =105 V/cm at 300 K. Note that the drain current is limited byvelocity saturation instead of pinch off. This occurs in short-channel devices when thedimensions are scaled without lowering the bias voltages. Using vde(sat), the maximum gainpossible for a MOSFET can be defined as:

)(satdeOXm vWCg = ...(71)

6.1.5 Impact Ionization:

Another undesirable short-channel effect, especially in NMOS, occurs due to the high velocityof electrons in presence of high longitudinal fields that can generate electron-hole (e-h)

pairs by impact ionization, that is, by impacting on silicon atoms and ionizing them. It happensas follow: normally, most of the electrons are attracted by the drain, while the holes enter thesubstrate to form part of the parasitic substrate current. Moreover, the region between thesource and the drain can act like the base of an n-p-n transistor, with the source playingthe role of the emitter and the drain that of the collector. If the aforementioned holes arecollected by the source, and the corresponding hole current creates a voltage drop in thesubstrate material of the order of 0.6V, the normally reversed-biased substrate-source p-njunction will conduct appreciably. Then electrons can be injected from the source to thesubstrate, similar to the injection of electrons from the emitter to the base. They can gainenough energy as they travel toward the drain to create new e- h pairs. The situation canworsen if some electrons generated due to high fields escape the drain field to travel into thesubstrate, thereby affecting other devices on a chip.

6.1.6 Hot electron injection:

Another problem, related to high electric fields, is caused by so-called hot electrons. Thesehigh-energy electrons can enter the oxide, where they can be trapped, and giving rise tooxide charging that can accumulate with time and degrade the device performance byincreasing VT and affect adversely the gates control on the drain current. Figure 22 shows thecharge trapping in the oxide due to hot electron injection.

Figure 22. Charge trapping in the oxide due to hot electron injection


31/34

6.1.7 Mobility degradation:In analyzing the carrier transport through the channel, only the effects of the horizontal electricfield due to the drain to source voltage was considered when considering the velocity saturation.However, a vertical field originating from the gate voltage also exists and influences carrier

velocity. A physical reason for this effect is that increasing the vertical electric field forces thecarriers in the channel closer to the surface of the silicon, where surface imperfections impedetheir movement from the source to the drain, reducing the mobility. The vertical field at anypoint in the channel depends on the gate to channel voltage. Since the gate to channel voltage isnot constant from source to drain, the effect of the vertical electric field on mobility should beincluded in deducing equation (21). This effect is approximately modeled by changing themobility in drain current equation to effective mobility given by:

)(10

TGS

effVV +

=

(72)

where 0 is the mobility with zero vertical field and is inversely proportional to the oxide

thickness )(OX

t . For 100=OX

t , is typically in the range of 0.1V-1.

6.2 Narrow channel effects:

MOS transistors are called narrow channel MOS transistors, when the channel width Wbecomesof the same order of magnitude as the maximum depletion region thickness xdm. In narrowchannel MOS transistors, a non negligible part of the field lines emanating from the gatefringe outside the area immediately below it. Since the gate electrode with the field oxidearound the channel, hence a relatively shallow depletion region forms under this overlap area aswell. Consequently, the gate voltage must also support this additional depletion charge in orderto establish the conducting channel. Consequently, the threshold voltages of the narrow channeldevices increase. For narrow channel devices the correction in the threshold voltage is given by:

WxNq

CVV dmFASi

OX

TNCT += |2|210)(0 ...(73)

where is an empirical parameter depending on the shape of the fringing depletion region.

7. Technology Scaling of MOS transistors:Over the past few decades, we have observed a spectacular increase in integration density andcomputational complexity of integrated circuits with digital integrated circuits in particular.Underlying this revolution are the advances in device manufacturing technology that allow for asteady reduction of the minimum feature size such as the minimum transistor channel lengthrealizable on a chip. We observe a reduction rate of approximately 13% per year, halving every 5years. Another interesting observation is that no real sign of a slowdown is in sight, and that thebreathtaking pace will continue in the foreseeable future.

A pertinent question is how this continued reduction in feature size influences the operatingcharacteristics and properties of the MOS transistor, and indirectly the critical digital designmetrics such as switching frequency and power dissipation. A first-order projection of thisbehavior is called a scaling analysis, and is the topic of this section. In addition to the minimumdevice dimension, we have to consider the supply voltage as a second independent variable insuch a study.


32/34

Table 1 shows the different scaling factors of different device parameters used for three types ofscaling.

Table 1. Scaling scenarios for short channel devices

Parameter Relation Full Scaling General Scaling Fixed Voltage Scaling

W 1/S 1/S 1/S

L 1/S 1/S 1/STOX 1/S 1/S 1/SVDD 1/S 1/U 1VT 1/S 1/U 1

NSUB V/Wdepl2 S S2/U S2Area/Device WL 1/S2 1/S2 1/S2

COX 1/ TOX S S SCG COXWL 1/S 1/S 1/SKn COXW/L S S SKp COXW/L S S SIsat COXWV 1/S U 1

J Isat/Area S S

2

/U S

2

Ron V/Isat 1 1 1Intrinsic Delay RonCG 1/S 1/S 1/S

P IsatV 1/S2 1/U2 1Power Density P/Area 1 S2/U2 S2

The three different types of scaling are discussed as below:

A. Full Scaling (Constant Electrical Field Scaling)

In this ideal model, voltages and dimensions are scaled by the same factorS. The goal is to keepthe electrical field patterns in the scaled device identical to those in the original device. Keepingthe electrical fields constant ensures the physical integrity of the device and avoids breakdown or

other secondary effects. This scaling leads to greater device density (less area), higherperformance (less Intrinsic Delay), and reduced power consumption (less P). The effects of fullscaling on the device and circuit parameters are summarized in the third column of Table 1. Weuse the intrinsic time constant, which is the product of the gate capacitance and the on-resistance,as a measure for the performance. The analysis shows that the on-resistance remains constant dueto the simultaneous scaling of voltage swing and current level. The performance improved issolely due to the reduced capacitance. The results clearly demonstrate the beneficial effects ofscalingthe speed of the circuit increases in a linear fashion, while the power/gate scales downquadratically!

B. Fixed-Voltage Scaling

In reality, full scaling is not a feasible option. First of all, to keep new devices compatible with

existing components, voltages cannot be scaled arbitrarily. Having to provide for multiple supplyvoltages adds considerably to the cost of a system. As a result, voltages have not been scaleddown along with feature sizes, and designers adhere to well-defined standards for supply voltagesand signal levels. Afixed-voltage scaling modelwas followed. Only with the introduction of the0.5 mm CMOS technology did new standards such as 3.3 V and 2.5 V make an inroad. Today, acloser tracking between voltage and device dimension can be observed. In a velocity-saturateddevice, keeping the voltage constant while scaling the device dimensions does not give aperformance advantage over the full-scaling model, but instead comes with a major powerpenalty. The gain of an increased current is simply offset by the higher voltage level, and only


33/34

hurts the power dissipation. This scenario is very different from the situation that existed whentransistors were operating in the long-channel mode, and the current was a quadratic function ofthe voltage. Keeping the voltage constant under these circumstances gives a distinct performanceadvantage, as it causes a net reduction in on-resistance. While the above argumentation offersample reason to scale the supply voltages with the technology, other physical phenomena such asthe hot-carrier effect and oxide breakdown also contributed to making the fixed-voltage scaling

model unsustainable.

C. General Scaling:

We observe that the supply voltages, while moving downwards, are not scaling as fast as thetechnology. For instance, for the technology scaling from 0.5 m to 0.1 m, the maximumsupply-voltage only reduces from 5 V to 1.5 V. The obvious question is why not to stick to thefull-scaling model, when keeping the voltage higher does not yield any convincing benefits? Thisdeparture is motivated by the following argumentation: Some of the intrinsic device voltages such as the silicon bandgap and the built-in junctionpotential, are material parameters and cannot be scaled. The scaling potential of the transistor threshold voltage is limited. Making the threshold too lowmakes it difficult to turn off the device completely. This is aggravated by the large process

variation of the value of the threshold, even on the same wafer.Therefore, a more general scaling model is needed, where dimensions and voltages are scaledindependently. This general scaling model is shown in the fourth column of Table 1. Here, devicedimensions are scaled by a factorS, while voltages are reduced by a factorU. When the voltage isheld constant, U = 1, and the scaling model reduces to the fixed-voltage model. Note that thegeneral-scaling model offers a performance scenario identical to the full- and the fixed scaling,while its power dissipation lies between the two models (forS> U> 1).

8. Problems:1. Consider a MOS system with the following parameters:

240=OXt

80.0=GC V15103=AN cm

-311102 = qQOX Ccm

-2(a) Determine the threshold voltage under zero bias (VT0) at room temperature (300K).

Given 097.3 =OX and 07.11 =OX .(b) Determine the amount of channel implant needed to change the threshold voltage to

0.8V

2. A MOS capacitor is fabricated on p-silicon substrate with a doping concentration of1016cm-3. If the gate oxide thickness is 400 and n+ poly-silicon is deposited as gate

metal, calculate:(a) The maximum capacitance per unit area(b) The minimum capacitance per unit area(c) The ideal threshold voltage taking work function into account(d) The threshold voltage taking the work function into account(e) If the C-V characteristics of this capacitor show a VFB=-1V, calculate the amount of

fixed oxide charge.


34/34

3. An nMOS transistor has the following specifications: W=5m, L=1m, tOX=400,n=800cm2V-1s-1, VT=1V. Calculate the drain current flowing through the device for thefollowing conditions:

(a) VGS=2V, VDS=0.5V(b) VGS=VDS=2V

4. An nMOS transistor is fabricated with the following physical parameters: ND=1020cm-3,NA(substrate)=1016cm-3, NA(channel-stop)=1019cm-3, W=10m, Y (length of diffusion region)=5m, L=1.5m, LD=0.25m, Xj=0.4m.

(a) Determine the drain diffusion capacitance for VDB=5V and 2.5V(b) Calculate the overlap capacitance between gate and drain for tOX=200 .

MOS Physics

Documents