Module 5a: Introduction To Memory System (MAIN MEMORY) REFERENCES: •STALLINGS, COMPUTER ORGANIZATION AND ARCHITECTURE •MORRIS MANO, COMPUTER ORGANIZATION AND ARCHITECTURE •PATTERSON AND HENNESSY, COMPUTER ORGANIZATION AND DESIGN •NULL AND LOBUR, THE ESSENTIALS OF COMPUTER ORGANIZATION AND ARCHITECTURE
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Module 5a - Universiti Teknologi Malaysia · Module 5a: Introduction To Memory System (MAIN MEMORY) REFERENCES: ... A final point is that SRAMs are generally somewhat faster than
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Module 5a: Introduction To Memory System
(MAIN MEMORY)
R E F E R E N C E S :
•S T A L L I N G S , C O M P U T E R O R G A N I Z A T I O N A N D A R C H I T E C T U R E
•M O R R I S M A N O , C O M P U T E R O R G A N I Z A T I O N A N D A R C H I T E C T U R E
•P A T T E R S O N A N D H E N N E S S Y , C O M P U T E R O R G A N I Z A T I O N A N D D E S I G N
•N U L L A N D L O B U R , T H E E S S E N T I A L S O F C O M P U T E R O R G A N I Z A T I O N A N D A R C H I T E C T U R E
Memory
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• Used to store information within a computer , either programs or data.
Programs and data cannot be used directly from a disk or CD, but must first be moved in memory
Main memory & cache memory referred as internal memory because it is place at the main board. Communicates directly with CPU immediately.
Secondary & tertiary memory referred as external memory (or auxiliary memory) because it is not located at the main board. Usually for back-up purpose.
Internal vs External Memory
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Primary Secondary Tertiary
Fast Slow Slow
Directly connected
to CPU
Not directly
connected to CPU
Not directly
connected to CPU
Expensive Cheap Cheap
Small volume Large volume Large volume
Eg. Cache/RAM Eg: Disk Eg: Tape
Memory Locations
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Each part of memory has a separate memory location, which can be referred to using a memory address.
Address Values
Unit Terms
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Size of memory is measured in bytes (or multiples such as kilobytes (KB) or megabytes (MB).
Number of bits for an address to uniquely access a memory location.
Number of locations = 2(no of bits in the address)
2log
log bits of no
capacitymemory
Memory Characteristic
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Location
Capacity
Unit of transfer
Access method
Performance
Physical type
Physical characteristics
Organisation
Memory Location
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CPU
Internal
External
Memory Capacity
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Word size
The natural unit of organisation
Common word size: 8, 16, 32 bits.
Number of words
or Bytes
Eg: Memory (a) and (b) have the same number of locations but different size.
…
Memory Unit of Transfer
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Internal
The number of bits read-out of or written into memory at a time.
Usually governed by data bus width
External
Usually a block which is much larger than a word
Addressable unit
Smallest location which can be uniquely addressed
Word internally
Memory Access Methods
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Sequential
Start at the beginning and read through in order
Access time depends on location of data and previous location
e.g. tape
Direct
Individual blocks have unique address
Access is by jumping to vicinity/location plus sequential search
Access time depends on location and previous location
e.g. disk
... Access Methods
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Random
Individual addresses identify locations exactly
Access time is independent of location or previous access
e.g. RAM
Associative
Data is located by a comparison with contents of a portion of the store
Access time is independent of location or previous access
e.g. cache
Memory Performance
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Access time
Time between presenting the address and getting the valid data
Memory Cycle time
Time may be required for the memory to “recover” before next access
Cycle time is access + recovery
Transfer Rate
Rate at which data can be moved
Memory Transfer Rate
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Transfer rate for random-access memory
Transfer rate for non-random-access memory
= TN = TA + N/R
where
TN = average time to read or write N bits
TA = average access time
N = number of bits
R = transfer rate, in bits per second (bps)
timecycle
1
Memory Physical Types
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Semiconductor
RAM & ROM
Magnetic
Disk & Tape
Optical
CD & DVD
Others
Bubble
Hologram
Memory Hierarchy
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Memory systems (a collection of various forms of memory) are constructed in a hierarchy
Why ? Rule of thumb: the faster the memory the higher the cost in
terms of price, making it very expensive to make all the memory out of the fastest memory devices.
Slower technologies are less expensive, making it more practical to make larger memories out of these devices
Goal of a memory hierarchy Keep the data that is accessed most high up the hierarchy, so
it can be accessed quickly
Least used at the bottom of the hierarchy.
Cache memory relatively small semiconductor memory operating at a speed that matches the processor
Main memory – semiconductor random access memory
Disk memory – not random access but not volatile.
Type of Main Memory
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It’s a relatively large and fast memory used to store programs and data during the computer operation.
The principle technology used for the main memory is based on semiconductor integrated circuits
Two main types
Read Only Memory (ROM)
contents are not lost (a.k.a. non-volatile memory)
Random Access Memory (RAM)
contents of memory are lost if the machine is switched off (a.k.a. volatile memory)
ROM
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Programmable ROM (PROM) Programmed after manufacture
Once they are programmed, cannot be changed (One Time Programmable)
Erasable Programmable ROM (EPROM) can be erase by exposing to Ultraviolet (UV) radiation for a few
minutes
can be reprogrammed
Electrically Erasable and Programmable ROM (EEPROM) Erase electrically not UV
No need to take out the IC to erase
Flash memory Erase whole memory electrically
ROM Usage
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Permanent storage
Nonvolatile
Microprogramming
Library subroutines
Systems programs (BIOS)
Function tables
HP-35 ROMs. The array contains 2560 bits.
RAM
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Dynamic RAM (DRAM)
Commonly used as main memory
Use capacitor to store data, 1- charged, 0 – discharged
Capacitor will lose its charge with time need to recharge (refresh)
Static RAM (SRAM)
Used for cache memory.
Use flip-flop to store data – no need refresh
Compare to DRAM – faster but more expensive, more complex and low capacity
Non-volatile RAM (NVRAM)
RAM that is not volatile
use internal power source to keep data in RAM during power off
SRAM VERSUS DRAM
Both static and dynamic RAMs are volatile
Power must be continuously supplied to the memory to preserve the bit values.
A dynamic memory cell is simpler and smaller than a static memory cell.
Thus, a DRAM is more dense (smaller cells more cells per unit area) and less expensive than a corresponding SRAM.
On the other hand, a DRAM requires the supporting refresh circuitry.
For larger memories, the fixed cost of the refresh circuitry is more than compensated for by the smaller variable cost of DRAM cells.
Thus, DRAMs tend to be favored for large memory requirements.
A final point is that SRAMs are generally somewhat faster than DRAMs. Because of these relative characteristics, SRAM is used for cache memory (both on and off chip), and DRAM is used for main memory.
Semiconductor Memory Types
Main Memory Capacity
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Memory locations/words can be grouped into block.
Memory capacity usually measured in bits:
Total no. of memory locations (words) × size of memory word
Memory capacity = Total no. of memory locations (words) X size of memory word
Total no. of memory locations (words) =No. of memory blocks X size of memory word
Example 1: Main Memory Capacity
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Main memory is divided into blocks.
The memory word is 8 bit and the size of a block is 8 words. What is the capacity of the
main memory, if the total number of blocks in the memory is 128?
How many blocks in the main memory if the memory capacity is 32 Kbit?
Example 1: Main Memory Capacity
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Memory capacity = Total no. of memory locations (words) X size of memory word = 1024 x 8 bit = 8192 bits = (8192/1024) Kbits = 8 Kbits
Total no. of memory locations (words) = Total no. of memory blocks X size of memory word = 128 block x 8 word = 1024
Q1: What is the capacity of the main memory, if the total number of blocks in the memory is 128?
The memory word is 8 bit and the size of a block is 8 words
1Kbit = 1024 bit
Example 1: Main Memory Capacity
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Memory capacity = Total no. of memory locations (words) X size of memory word 32Kbit = TML X 8 TML = 32Kbit / 8 = (32 x 1024)/8 = 4096 bits
Total no. of memory locations (words) = Total no. of memory blocks X size of memory word 4096 bits = memory blocks x 8 Memory blocks = 4096/8 = 512 blocks
Q2: How many blocks in the main memory if the memory capacity is 32 Kbit
The memory word is 8 bit and the size of a block is 8 words
TML = Total no. of memory locations
Example 2: Main Memory Capacity
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Memory capacity = Total no. of memory locations (words) X size of memory word = 4096 K x 8 = 32768 Kbits = 32Mbit
Total no. of memory locations (words) = Total no. of memory blocks X size of memory word = 8K x 512 word = 4096 Kwords
Q: What is the capacity of the main memory?
Main memory contains 8K blocks of 512 words each. Each word is 8 bit (1 byte).
1Kbit = 1024 bit 1Mbit = 1024 Kbit
Memory Interleaving
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A single memory module causes sequential access (only one memory access performed at a time) not efficient
Memory interleaving
Splits memory across multiple memory modules (or banks)
Can increase efficiency can issue memory requests to all banks at the same time.
Access is more efficient when memory is organized into banks of chips with the addresses interleaved across the chips
Low-order interleaving (LOI) the low order bits of the address are used to select the memory bank.
High-order interleaving (HOI) the high order bits of the address are used to select the memory bank.
Memory Banks/Modules
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Memory usually implemented in module/interleave (SIMM and DIMM)
SIMM is single in-line memory module while DIMM is dual in-line memory module. A DIMM (dual in-line memory module) is a double SIMM.
Memory Interleaving
Say we have a byte-addressable memory consisting of 8 modules/banks of 4 bytes each.
This gives a total of = 4 * 8 = 32 bytes of memory.
To identify each byte , we need 5 bits ( 25 = 32)
3 bits is used to determine the module there are 8 modules , so 23
2 bits to determine offset within the module module capacity = 22 = 4
To identify each memory unit we need 5 bits ( 25 = 32)
Given 8 modules we need 3 bits ( 23 = 8)
Module capacity = (2(5-3) = 22 = 4)
3 bits to determine
module 110
3 bits to determine
module 001
2 bits to determine offset
00
Memory Interleaving: HOI
HOI distributes the addresses so that each module contain consecutive addresses
Address 3 , in binary (remember we need 5 bits) = 00011
So, address 3 is at module 0, offset 3
High order bits – the module
The address = 00000
The address = 00001
The address = 00010
The address = 00011
The address = 11100
The address = 11101
The address = 11110
The address = 11111
Memory Interleaving: LOI
LOI places the consecutive address in different memory modules.
Address 3 , in binary (remember we need 5 bits) = 00011
So, address 3 is at module 3, offset 0
Low order bits – the module
The address = 00111
The address = 01111
The address = 10111
The address = 11111
The address = 00000
The address = 01000
The address = 10000
The address = 11000
Example 2
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Given a memory capacity = 64 and a total main module of 4.
Determine the module capacity
Where can addresses 25, 32 and 55 be found in HOI and LOI?
Draw the HOI and LOI memory interleaving
To identify each memory unit we need 6 bits ( 26 = 64)
Given 4 modules we need 2 bits ( 22 = 4)
Module capacity = (2(6-2) = 24 = 16)
Example 2
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Given a memory capacity = 64 and a total main module of 4.
Determine the module capacity
Where can addresses 25, 32 and 55 be found in HOI and LOI?
Please remember that these are NOT CONTENT. These are the address (used by memory to get the content).
Example 3
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Given a memory address as 29Ch (10 bits) and there are 4 memory banks/modules. Determine the memory bank/module address and the address of the word in the bank/module, for both HOI and LOI.
1010 0111 00
Given the memory address of 10 bits, 29Ch represented as
1010011100 in binary
Given 4 modules we need 2 bits ( 22 = 4)
Module capacity = (2(10-2) )= 28 = 256 So 8 bits is used for this
10 1001 1100
LOI HOI
Example 3
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1010 0111 00
Given the memory address of 10 bits, 29Ch represented as
1010011100 in binary
Given 4 modules we need 2 bits ( 22 = 4)
Module capacity = (2(10-2) )= 28 = 256 So 8 bits is used for this
10 1001 1100
LOI HOI
Memory bank/module address = 00
Address of the word in the bank/module = 1010 0111 = A7h
Memory bank/module address = 10
Address of the word in the bank/module = 1001 1100 = 9Ch
Example 4
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A main memory has 32 Mwords. There are 16 memory banks (modules). Draw the modular memory address format if the system is implemented with HOI.
bank/module address word in the bank/module
4 bits 21 bits
To identify each 32M memory we need 25 bits ( 25 * 220 = 32M)
Given 16 modules we need 4 bits ( 24 = 16)
Module capacity = (2(25-4) = 221 = 16) We will use 21 bits for offset
Advantages & Disadvantages (LOI)
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Advantages
It produces memory interference.
LOI allows for concurrent access of data stored sequentially in memory
Disadvantages
A failure of any single module would be catastrophic to the whole system.
Advantages of HOI
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Easy memory extension by the addition of one or more memory modules to a maximum of M-1.
Provides better reliability, since a failed module affects only a localized area of the address space.
This scheme would be used without conflict problems in multiprocessors if the modules are partitioned according to disjoint or non-interleaving processes ( programs should be disjoint for its success).
Disadvantages of HOI
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Scheme will cause memory conflicts in case of pipelined, vector processors. The sequentiality of instructions and data to be placed in the same module. Since memory cycle time is much greater than pipelined clock time, a previous memory request would not have completed its access before the arrival of next request, thereby resulting in a delay.
Process interacting and sharing instructions and data in multiprocessor system will encounter considerable conflicts.
This technique is useful only in one single user system/ single user multitasking system.
Example 5
Given a 32K memory with 16 modules.
Determine the module capacity
Using HOI, determine the module and offset for the address 00100000010011.
Using LOI, determine the module and offset for the address 00100000010011.
To identify each 32K memory we need 15 bits ( 25 * 210 = 32K)
Given 16 modules we need 4 bits ( 24 = 16)
Module capacity = (2(15-4) = 211 = 21 * 210 = 2K)
Example 5
Given a 32K memory with 16 modules.
Determine the module capacity
Using HOI, determine the module and offset for the address 00100000100111.
Using LOI, determine the module and offset for the address 00100000100111.
MODULE 2, OFFSET 39
HOI MODULE OFFSET
Example 5
Given a 32K memory with 16 modules.
Determine the module capacity
Using HOI, determine the module and offset for the address 00100000100111.
Using LOI, determine the module and offset for the address 00100000100111.
MODULE 7, OFFSET 258
LOI MODULE OFFSET
Example 6
Requirement : 32 word of memory and module capacity of 4 words each. Each word contains 8 bits.
Calculate the number of address bit for the memory
How many modules are needed?
To identify each 32 word memory we need 5 address bits ( 25 = 32)
Given module capacity of 4 words we need 2 bits for offset ( 22 = 2)
Total modules needed 2(5-2) = 23 = 8 we need 8 modules
The number of bits needed to identify
each module
Example 6
For both HOI and LOI formats, draw and label the sequence of address for the first and last module.
The size of this word is 8 bits. E.g. content is GGh, 10101111b
LOI
HOI
Example 6
For both HOI and LOI formats, draw and label the sequence of address for the first and last module.