mLogic All Spin Logic Device and Circuits for Future Electronics · 2015-03-23 · Carnegie Mellon University 1 Carnegie Mellon University Jimmy Zhu 1, D. Bromberg , V. Sokalski2,

Carnegie Mellon University

1


Jimmy Zhu1, D. Bromberg1, V. Sokalski2, M. Moneck1, L. Pileggi 1

1Department of Electrical and Computer Engineering 2Department of Material Science and Engineering

Carnegie Mellon University, Pittsburgh, U.S.A.

mLogic

All Spin Logic Device and Circuits for Future Electronics


2 mLogic People

David Bromberg, Ph.D.

Postdoc Fellow

Testing and modeling

Matthew Moneck

Research Scientist

Device fab and testing

Vincent Sokalski

Research Professor

Thin film fabrication

En Yang

Postdoc Fellow

Thin film fabrication

Daniel Morris

Ph.D. student

Circuit modeling and analysis

Larry Pileggi

Tanoto Professor, ECE

Jimmy Zhu

ABB Professor, ECE


3 History of Microprocessors 3

Intel Quad Core Processor


4 Transistor and Logic

~ 1V

Gate

n n

p

- - - - - -

Drain Source

VG > VTh On State ~ 1V

+ + + +

It is all about moving charges (electrons) !

Field Effect Transistor (FET) CMOS Invertor

“ 1 ” “ 0 ”

“ HIGH” “ LOW ”


5 Energy Loss When Charging Gates

222

2

12

2

1CVCVRdtiE

Energy stored

C

R

-

Energy dissipated

i

V


6 Joule Heating: Effect of Moving Charge

Results of Joule heating I2R Today’s Microprocessor


7 Magnet: Magnetic Moment and Field

M

H

H

Magnetization M

Magnetic moment per unit volume


8

Tunnel barrier

FeCo/MgO (~1nm) /FeCo

Magnetic electrode

m1

m2

Magnetic electrode

Magnetic Tunnel Junction

0 20 40 60 80 1000.0

0.5

1.0

1.5

2.0

2.5

Resis

tan

ce (

k

)

Data Bits

State “0” State “1”

Energy

transmission

incident


9 Electron: Charge and Spin

-e

2

1S

J/T 10927.02

23-e

Bm

e

Bohr Magneton

Electron Spin: Angular momentum


10

M

electron flow

M

v

electron flow

Moving Domain Wall with STT

I


I

Spin Transfer Torque


11 Pure Spin Current ?

• Electron spin is doing the work.

• Current is only providing a vehicle.

• Can we generate a charge-free spin current?


12

Spin Current

Spin Hall Effect


13 Pure Spin Current

自旋流

Charge

Charge-free Spin Current

Charge


14 Pure Spin Current

Pt

Co/Ni

e-


15 Spin Hall Effect


16 mCell Design

I

r

-ww

r

Tunnel Barrier

Insulating Magnetic

Coupling Layer Free-Layer

Write-path

r

'r

w -w

4-Terminal

Schematic Symbol

: Low Resistance State rr -


17 mCell Design

I

r

-ww

r

Free-Layer

Write-path

r

'r

w -w

4-Terminal

Schematic Symbol

Tunnel Barrier

Insulating Magnetic

Coupling Layer

: High Resistance State rr -


18

+VPC -VPC Iw

Vm >0

Fanout (e.g. Inverter)

RHIGH RLOW


19

+VPC -VPC Iw

Vm >0


RHIGH RLOW


20

+VPC -VPC Iw

Vm >0


RHIGH RLOW


21

+VPC -VPC Iw

Vm >0


RHIGH RLOW


22

Iw

+VPC -VPC

+VPC -VPC

Iw

Vm >0

Vm <0



23 State-Switching

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

Ene

rgy C

han

ge

E

(eV

)

Time t (ns)

J=5x106A/cm

2


24 Power Clocking and Fanout

Fanout is series chain of write paths

pClock: Power and clocking combined

Negligible impact from load capacitance

A F X Y Z

0 -V/2

0 pClk2+

pClk1+ +V/2

+V/2

-V/2

pClk1-

pClk2-

pClk1-

A

F F

X Y Z

pClk2+ pClk2+

pClk2- pClk2- pClk2-

pClk1+

F

A

F F F

pClk2+


25

Iw

+VPC -VPC

+VPC -VPC

Iw

Vm >0

Vm <0



26 Non-Volatile Storage

‘Free’ storage of state for every logic gate

Can enter/exit zero-power ‘sleep’ mode instantaneously

Overhead-free pipelining for super high throughput

Offsets modest switching speed

Example with alternating phases of pClock for each logic level


27 mLogic

Exchanging input terminals inverts function for free

Complementary

MTJ Variation Robustness

Threshold

Logic Density

Push-Pull

Supply Variation Robustness

B

A

CBCABA

V-

V+

C B

B

A

A

BA

V-

V+ V+

BA

V+

A

B

A

B


28 mLogic Bit-Serial Datapaths

Inherent logic-state storage eliminates costly memory

transfers for bit-serial computations

Bit-shifts (delays of bit-serial signals) are trivial

4A 32A 16A A 64A

96A 768A

24576A

1408A

46336A

92680A

92680*A / 217

≈ sin(2π/8)*A

+ + + +

Ex: Constant coefficient multiplication


29 Example: 512 pt FFT w/ 16b Precision

Break into smaller DFTs with O(N) twiddle factor multiplications,

reusing multipliers and butterfly units

Simulation: 23 nJ/FFT and 6.5M FFT/s throughput @ 100mV pClock

6.7x lower energy and 1,700,000x higher throughput than a

published sub-threshold CMOS implementation

nJ/FFT VDD FFT/s # devices

Sub-Vt [ISSCC 2004] 155 0.350 3.8 627K

mLogic 23.1 0.100 6.5M 1.5M


30 Noisy and Intermittent Power Supplies

Possible to detect and correct failures

Compatible with energy harvesting mechanisms

Requires less power regulation circuitry

pClock amplitude

is too low

pClock1

pClock2

output signals

Detected failure,

pulse repeated


31

• All STT based metallic logic

• Nonvolatile logic states

• Ultra-low pulsed voltage

• Portable & energy-harvesting

• Rad-hard for space applications

• Very low cost manufacturing

• Scalable to 5nm CD

mLogic: All Spin Logic Circuits


32

Experimental Demonstration


33 mCell: Read Path

I

r

-ww

r

Free-Layer

Write-path

r

'r

w -w

4-Terminal

Schematic Symbol

Tunnel Barrier

Insulating Magnetic

Coupling Layer


34

Sequence

Tanneal = 250°C Fe60Co20B20

BOTTOM

TOP

V. Sokalski et al. Applied Physics Letters. 101 (072411) (2012).

MTJ with PMA Electrodes

TOP

BOTTOM


35

Ta Seedlayer Effect

V. Sokalski et al. IEEE Transactions on Magnetics, vol. 49, no. 7, 2013

Effect of Underlayer

- Annealing stability increased to 350°C. - TMR improvement by more than a factor of 2.


36

Ta deposition rate is a significant factor in determining annealing stability…

Tanneal = 350°C

Ta Seedlayer Effect

Interface Anisotropy Approach

V. Sokalski et al. IEEE Transactions on Magnetics, vol. 49, no. 7, 2013


37 mCell: Write Path

I

r

-ww

r

Free-Layer

Write-path

r

'r

w -w

4-Terminal

Schematic Symbol

Tunnel Barrier

Insulating Magnetic

Coupling Layer


38 Co/Ni Multilayer for Write-Path

Ta

Si Substrate

Pt

Co/Ni

Ta

Co/Ni multilayer film stack

TaN


39 Current- induced Domain Wall Motion Observation

10 µm

Co-planer Waveguide Test

Structure

(20m long, 50-250nm wide )

Domain Wall Nucleation


40 Spin Hall Driven Domain Wall Motion

0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

20

40

60

80

100

120

140current pulse width

10ns

30ns

50ns

Ave

rag

e D

om

ain

Wa

ll S

pe

ed

(m

/s)

Current Density J (x108 A/cm

2)

Ta (3nm)

Pt (2.5)

{Co(0.2)/Ni(0.3)}x2

Co(0.2) Ta (0.3)

TaN (6)


41 Material Optimization

Ta (3nm)

Pt (2.5)

{Co(0.2)/Ni(0.3)}x2

Co(0.2) Ta (x)

TaN (6)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

60

80

100

120 J = 1.8x108 A/cm

2

Avera

ge D

om

ain

Wall

Speed (

m/s

)

Top Ta Layer Thickness (nm)


42 mCell: Insulating Magnetic Oxide Layer

I

r

-ww

r

Free-Layer

Write-path

r

'r

w -w

4-Terminal

Schematic Symbol

Tunnel Barrier

Insulating Magnetic

Coupling Layer

EC-08, M. Moneck et al


43 Co/Ni-Ta-FeCoB Coupling

Optimized Co/Ni-FeCoB coupling through Ta spacer for 4-terminal test structure

Maximum coupling without free layer

degradation


44 Integrated Film Structure

Ta (0.5nm)


45

mCells Structures

Fanout Structures

Kerr Structures

• Individual mCells fabricated – 500 nm, 1 µm widths – No magnetic oxide for now

• Vias created for electrical access to the functional layers

• Leads patterned from the vias out to probe pads for testing

Device Prototype


46 Fabricated mCell

r

-ww

'r

e-

EC-08, M. Moneck et al.


47 Switching Demonstration


48 Overcome Pinning Effect

0.85 0.90 0.95 1.000

1

2

3

4

5

6 Current Pulse Width

10 ns

30 ns

50 ns

Nu

mbe

r of P

uls

e N

ee

ded

Current Density (x108 A/cm

2)


49

-100

-50

0

50

100

Curr

ent

density [

MA

/cm

2]

0 10 20 30 40 50 60 70 80

1.3

1.4

1.5

1.6

Read-p

ath

resis

tance [

M

]

Reliable Digital Switching

Inject positive current observe low resistance state

Inject negative current observe high resistance state

Repeat!


50 Summary

mCells have been successfully fabricated with integrated

reader path and write path separated by a thin Ta interlayer.

A complete state switching can be accomplished with a

single current pulse through write path.

To enable fanout, we need to reduce switching current

density and increase tunneling MR.

mLogic is a promising technology for future electronic

applications.

mLogic All Spin Logic Device and Circuits for Future Electronics · 2015-03-23 · Carnegie Mellon University 1 Carnegie Mellon University Jimmy Zhu 1, D. Bromberg , V. Sokalski2,

Documents