Mixed-Signal Measurement Circuits For Embedded Test … · Core for Analog and Mixed-Signal Circuits,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 4, pp. 499-514, April 2002.

Future Directions In IC Packaging 2003

© 2003 G. W. Roberts On-Chip Test Cores, slide 1

Mixed-Signal Measurement CircuitsFor Embedded Test Access

Gordon W. RobertsMcGill University

(Presently on leave with DFT MicroSystems)

October 26, 2003



Outline• Introduction• On-Chip Instruments

– Signal Generators– Sampling Oscilloscopes– Coherent Sampling Test System– Time Domain Reflectometry &

Transmission– Timing Analyzers

• Conclusions



System On-A-Chip / In-A-Package

• More and more components are being integrated into smaller andsmaller devices/packages.– Gaining test access to ALL components is becoming

increasingly more difficult.

µP

RAM

PLL

D/A

vendor A

vendor Bvendor C

Core-Based DesignComponent-Based Design

vendor Bvendor C

vendor A



Embedded Test Capability

CUT CUTCUT CUT

CUT CUTCUT CUT

CUTCUT CUT

CUT

AWG

DIG

TAP

AnalogTest Bus(possibly,

IEEE 1149.4)

Chip Boundary



Test Bus / Test Ports

• A test bus provides observability and/or controllability ofinternal nodes on an IC/board/system.

• Standardizing the pins of the test port facilitates test set-up andprogram re-use.

– IEEE industrial standard (IEEE 1149.4).• Good analog switches are difficult to realize in advanced CMOS.

AT1AT2

DTin

DTout

AnalogFunc.

AnalogFunc.

AnalogFunc.

F/F F/F F/F F/F

AIN AOUT



Moving Test Instruments Directly On-Chip

Move the test equipment to thesignals-under-test rather than the

signals to the test equipment!

Arbitrary Function Generator

Oscilloscope

Function Generator



Improving Diagnostic Capability

AWG

DIG

TAP

CUT CUTCUT CUT

CUT CUTCUT CUT

CUTCUT CUT

CUT

AnalogTest Bus(possibly,

IEEE 1149.4)

DigitalTest Bus(possibly,

IEEE 1149.1)



Improving SOC Test Times

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWGTAP

DIG DIG DIG

DIG DIG DIG

DIG DIG DIG

DIG

DIG

DIG


IEEE 1149.1)



Design For Manufacturability

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWG

CUT

AWGTAP

DIG DIG DIG

DIG DIG DIG

DIG DIG DIG

DIG

DIG

DIG


IEEE 1149.1)

Mixed-signal test circuitscan interface with present-

day digital test buses.






• Conclusions



Analog Signal Generation

Conventional Analog Signal Generation:– Tuned oscillator circuits– Relaxation oscillator circuits

Problem for On-Chip Solution:– Low-Q operation unless using crystals.– Difficult to control amplitude, frequency and multi-tone

signals.– Frequency and amplitude sensitive to absolute value of

components.

+-

C1

C3



Analog Signal GenerationUsing Direct Digital Frequency Synthesis

• A digital signal is numerically created and converted to analogform using a D/A circuit.

• Advantages:– Largely digital, stable signal generation and fully

programmable (both amplitude and frequency).– Frequency set by system or external clock.– Coherent measurement system - fastest measurement

• Disadvantages:– Large silicon area requirement.

DigitalSignal

GenerationD/A

LPReconst.

FilterAnalogOutput



Data Conversion Using Delta-Sigma Modulation

• Delta-sigma modulation converts multi-bit precision signalsinto a single-bit digital pattern

• Pulse Density Modulation, PDM

ΔΣ



Single-Bit Generation

• Record a portion ofa ΣΔ output

• Reproduce itperiodically– Easily implemented– High speed

• Desired Tone, sameFrequency andAmplitude as input

ΣΔ...

...



Scan-Chain GeneratorAnalog & Digital Signals

Analog Filter

+ +

+kω

-

kω

1/2

+ +

Z-1

Z-1

Digital Filter

Load /Loopclk

Data F/FD Q

Q

0

1Sel

Out

F/FD Q

Q

F/FD Q

Q

ΔΣMod High-Speed Logic / Memory



Signal Generation Equations

-4 -2 -1 0 1 2x 10-4

-1

-0.5

0

0.5

1

Ampl

itude

(V)

time (s)

Differing Frequency Signals

-2 -1 0 1 2x 10

-1

-0.5

0

0.5

1

Differing Amplitude Signals

Ampl

itude

(V)

time (s) -4

• Both frequency and amplitude of test signal can becontrolled by changing the density of 1’s and 0’s inthe digital pattern.



392-Bit Sine Wave

0 10 20 30-100

-80

-60

-40

-20

0

Powe

r (dB

m)

Frequency (kHz) -3 -2 -1 0 1 2 3x 10-4

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

Ampl

itude

(V)

time (s)

Power Density Spectrum Oscilloscope Trace• Go to web-site http://www.macs.ece.mcgill.ca/~roberts/ to download

other examples



Multi-Tone Waveform

• example of a reconstructed two-tone signal

0 5 10 15 20-100

-80

-60

-40

-20

0

Powe

r (dB

m)

Frequency (kHz)-1 -0.5 0 0.5 1

x 10-3

-1

-0.5

0

0.5

1

Ampl

itude

(V)

time (s)

Two-Tone Frequency Spectrum Two-Tone Oscilloscope Trace



Sawtooth Waveform

• 476 Hz sawtooth (infinite-tone) reconstruction

0 5 10 15 20-100

-80

-60

-40

-20

0

Powe

r (dB

m)

Frequency (kHz)-6 -4 -2 0 2 4

x 10-3-1.5

-1

-0.5

0

0.5

1

1.5

Ampl

itude

(V)

time (s)

Frequency Spectrum of Sawtooth Scope Trace of Sawtooth






• Conclusions



Test Bus With On-Chip Buffers

• A test bus often has an on-chip voltage buffer to drive off-chiploads.

-+

ATIN

ATOUT

DTin

DTout

AnalogFunc.

AnalogFunc.

AnalogFunc.

F/F F/F F/F F/F

AIN AOUT



Test Bus With On-Chip Comparator

• A test bus can be turn into a sampling oscilloscope byreplacing the voltage buffer with a 1-bit comparator.

– Only digital signals are moved across the chip boundary.

ATIN

DTin

DTout

AnalogFunc.

AnalogFunc.

AnalogFunc.

F/F F/F F/F F/F

AIN AOUT

1-Bit Output-

+

Aref



A/D Conversion Algorithm(successive-approximation process)

Ain = K ref ( b121 +

b222 +

b323 + .... +

bN2N )

on-chip tester



t

Subsampling Principle

-+

In

Out

AT1 AT2 DinDout

F/F

F/F

AnalogCore

1-Bit Output Aref

Analog

Dig

ital

• K. Lostr o m , “Early capture for boundary scan timingmeasurements,” Proc. of the International Test Conference, pp. 417-422, Oct. 1996.

• A. Hajjar and G. W. Roberts, International Test Conference, 1998.

On-Chip Oscilloscope(High-Speed Signals Observed Using Subsampling)

Chip Configured forIEEE1149.1/1149.4 Test Bus






• Conclusions



ArbitraryWaveformGenerator

Clock Source

CUT

Periodic BitStream

Generator

AnalogReconstruction

FilterProgrammable

Reference

To DSPWaveformDigitizer

Program

Coherent Test System

• Functional diagram identical to that of a generic DSP-basedtest system

• Unified clock guarantees coherence between the generationand measurement subsystems

* M. Hafed, N. Abaskharoun and G. W. Roberts, “A 4 GHz Effective Sample-Rate Integrated TestCore for Analog and Mixed-Signal Circuits,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 4,pp. 499-514, April 2002.



Signal GenerationPeriodic ΔΣ Bit Stream Approach

• Output of ΔΣ modulator is approximated usinga short repetitious sequence of bits

• Very short sequences demonstrate highspectral purity analog signals

ΣΔΣΔ



S/HS/H

ProgrammableReference

Digital Multiple-Pass A/DController

Nodesof

CUT

• No Specificrequirements oncomparator

• S/H decouplessampling rate fromcomparator conversionrate

• M. Hafed & G. RobertsITC’2000

Waveform DigitizerImplementation



Digital PulseModulator

R

C

LPF

Vout

Programmable Reference Generator

• DC level is encoded inthe average of a finite-length periodic digital bitsequence

• Passive on-chip filterachieves area efficiency,simplicity, androbustness



Passive Filtering• Passive RC does not alter DC component regardless of the

values of R and C:

• Filter trades off amplitude resolution (allowable ripple) versusspeed (settling time)

€

H f( ) =1

1+ 2 ⋅ π ⋅ f ⋅ R ⋅C( )2

R

C

LPF

Vout

0

VDD

Vin



PWM Frequency Domain Description

• The DC tone has a magnitude which is dependent on the ratio of 1’s(N1) to the total number of bits in the digital periodic sequence (Nb).

• The magnitude and distribution of the AC harmonics depend on thesequence of 1’s and 0’s in the bitstream.

DC=N1/Nb

FreqFS/Nb

S

0

Harmonic must bereduced by filteringFb



PDM Frequency Domain Description

• Using Pulse Density Modulation (PDM) has the effect of pushingmost of the harmonic power higher in frequency therefore alleviatingthe filter requirements.

• DC Patterns can be generated in the exact same way as for the ACsignals.

FreqFS/Nb

FbDC=N1/Nb

0

F’b



Digitization Using On-ChipComparators

• Aref is successively modified until thequantization level of the sample-under-test is determined Out

Aref

Vcut

• Inherent sub-samplingoperation means higheffective sampling rate

2

4

6

8

10

12

14

0

Qu

anti

zati

on

Lev

el

Pass Number1 2 15 16

Aref



Multipass Method

1 1 1 1 1 0 0 11 1 1 1 1 0 0 1

1 1 1 1 1 0 0 01 1 1 1 0 0 0 1

1 1 1 1 0 0 0 01 1 1 1 0 0 0 0

0 1 1 1 0 0 0 01 1 1 0 0 0 0 0

0 1 1 0 0 0 0 00 1 1 0 0 0 0 00 0 1 0 0 0 0 00 1 0 0 0 0 0 0

DC REFERENCEGENERATOR

COMP.

DSP + Memory

11 1 1 1 1 1 1 1 1 1 1 1 1 1 1



Almost All-Memory Implementation

AnalogFilter

CUT

DSP

N x 2 N x log2N

S/H

S/H

÷ DIVClk

US & Canada Patent Pending



• Technology: 0.35 um, 3.3 V CMOS

• Amplitude Resolution: 8 bits

• Effective Sampling Rate: 4 GHz

• Time resolution (off-chip): 200 ps

• SFDR: 65 dB @ 500 kHz 40 dB @ 500 MHz

8-Bit, 4 GHz AWG & Digitizer M. Hafed & G. Roberts CICC’2000, JSCC April 2002

Chip Details

2 mm

2 mm

Periodic BitStream

Generator

ProgrammableReference S/H, Comparator,

A/D Controller



10-Bit, 4 GHz AWG & Digitizer M. Hafed & G. Roberts / Wireless Test Workshop 2001

• Technology: 0.35 um, 3.3 VCMOS

• Amplitude Resolution:10 bits

• Effective Sampling Rate:4 GHz

• Time resolution (on-chip):200 ps

• SFDR: 65 dB @ 500 kHz 40 dB @ 500 MHz

Chip Details

2 mm

1 mm

Periodic BitStream

Generators

Digitizer

Timing Module



Measured PerformanceCurve-Tracer Functionality

-1

-0.5

0

0.5

1

0 1000 2000 3000 4000

-1.5

-1

-0.5

0

0.5

1

1.5

-1.5 -0.5 0.5 1.5Input Voltage

Output Voltage

DNL Errors (LSB)

Input Code

20µV



Measured PerformanceOscilloscope-Like Functionality

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-2 -1 0 1 2Time (ns)

On-Chip GeneratedAnalog Waveform

Output (V)

Maximum harmonic error: < 0.01%

1.1 ns



-120.00

-100.00

-80.00

-60.00

-40.00

-20.00

0 10 20Frequency (kHz)

Po

wer

(d

B)

~61dB

Measured THD: <0.2%

Waveform DigitizerMeasured Performance



Spectrum Analyzer-Like Functionality

• On-chip measurement result compared to actualmeasurement on a HP3588 Spectrum Analyzer

Frequency (kHz)

Filt

er M

agn

itu

de

Res

po

nse

(d

B)

-100

-80

-60

-40

-20

0

20

0 100 200 300 400-100

-80

-60

-40

-20

0

20

0 100 200 300 400

Measurement Capability



Interfacing With Off-Chip Eqmt

Scan path

. . .

Scannable cells for regular core I/O and for internal “scan chain” access. . .

. . .

OriginalAnalog/Mixed-SignalCore



Moving Scan Chains Off Chip

Analog/Mixed-SignalCore

Digital Scan-chains

On-Chip MS Test Ccts

Chip boundary






• Conclusions



Board Testing: Time Domain Reflectometry

DIG

• Board-level interconnect• 8-bit resolution• 4-GHz sample rate

On-Chip



Board-Level TDR at 4 GSample/s

0

0.5

1

1.5

2

2.5

0 10 20 30 400

0.5

1

1.5

2

2.5

0 10 20 30 40

Time (nsec)

Out

put

Tra

nsiti

on(V

)

ChipTektronix TDS Osc.

DIG

• Board-levelinterconnect

• 8-bit resolution• 4-GHz sample

rate



Crosstalk Characterization

• Investigating on-chip crosstalk effects is oftenperformed with a multi-conductor structure usingdifferent forms of signal excitation.– On-chip behavior is often difficult to obtain due to

package parastics and equipment loading effects.



Area per DIG: 0.044 mm2 (8-Bit Sampler)

RC Bank

MemoryFiles

Sample CUT (LNA)

Lines &Other CUTS

DIG

24

10 GHz Sampling Scope Prototype(M. Hafed & G. Roberts CICC 2003)



10-GHz TDT Experimental Results

0

0.5

1

1.5

2

0 2 40

0.5

1

1.5

2

0 2 4

Measured TransitionFull-Parasitic Spice

Time (ns)

Ou

tpu

t T

ran

siti

on

(V

)

DIG

• Complete insitu digitization

• 6-bit resolution• 10 GHz sample

rate• Other signal-

integrity testsdemonstrated



Substrate Noise

00.20.40.60.81

1.21.41.61.8

0 1 2 3 4 5

Clean

Clean

DIG

VDD

VSS

• Example of bounce on highresistance ground path

• Need to investigate improvedsampling techniques

Time (ns)

Vo

ltag

e W

avef

orm

(V

)

Integrated Prototype

Full-Parasitic Spice



Clean

Clean

DIG

VDD

VSS

• Other integrity issuessuccessfully demonstrated

• Translation into frequencydomain possible because ofdigitization

0.60.81

1.21.41.61.8

0 0.5 1 1.5 2Time (ns)

Vo

ltag

e W

avef

orm

(V

)

Integrated Prototype

Full-Parasitic Spice

Power Supply Noise



High-Frequency Tuned Amplifier

• Simple circuit for illustration purposes. Similar to a LNA, although notoptimized for noise considerations

• Output Signal not expected to be driven off-chip in “mission”environment

• Conventional measurement requires buffer insertion

ResonantTank

Bias Network

ChipBoundary



Buffer Insertion for Probe Test

• Even wafer probing presents too large a load• Inserted buffer is typically also tuned in frequency (depending on

termination)• Measured spectrum influenced by buffer characteristics

Tuned Buffer

Wafer probe

Wafer probe

Frequency Response

Amplifier Buffer Measured



Proposed Test Vehicle

SynthesizedCW Source

DIG

ResonantTank

BiasNetwork

ChipBoundary

ChipBoundary

• Amplifier output directly sampled on-chip• Flat response of DIG ensures proper extraction of spectral

characteristics• Offset/gain errors, and noise need to be investigated



Experimental Results

1 2

Frequency (GHz)

For

war

d T

rans

mis

sion

(dB

)

0

4

8

12Integrated Prototype

Spice

• Embedded testtechnology used toimplement sameDSP-based solution

• LNA resonancefrequency slightlyoffset fromsimulation

• Investigatecorrelation withsimulation






• Conclusions



Edge Density (Jitter CDF)

Edge Histogram (Jitter PDF)

“0”

“1”“0”

“1”

“0”

“1”

Sam

pled

Log

ic L

evel

s

Edge 1

Edge 2

Edge 3

Sampling Instants

τres0 2τres

3τres

4τres5τres

6τres

7τres

8τres

9τres10τres

11τres

12τres13τres

14τres

15τresEdge

Uncertainty

Measuring Jitter



RMS-Jitter Measurementdata under test

N-Bit Register

+D Q

clk

Count

F/F

refΔT

ΔT/T

pdf

-2 -1 0 1 2

cdf

1

0.5pdf

cdf

counter

data



RMS-Jitter Measurement

“0”

“1”

“0”

“1”

“0”

“1”

τres0 2τres3τres4τres5τres6τres7τres8τres9τres10τres11τres12τres13τres14τres15τres

Edge

UncertaintyN-Bit Register

+D Q

F/F

N-Bit Register

+D Q

F/F

N-Bit Register

+D Q

F/F

DUT

constant delayM. Clk

Counter

Delay Line



Jitter Measurement Device UsingA Venier Delay Line

τ1DATA

CLK

D Q D Q

τ1

τ2 τ2C

OU

NT

_1

CO

UN

T_2

D Q

τ1

τ2

CO

UN

T_M

• • •

• • •

• • •

τ2 > τ1, τres = τ2 - τ1

• Sub-gate delays can be realized using a VDLstructure:



Chip Micrograph

VDL

COUNTERS

DLL Digitizer

1 mm

• 101 Stage VDL in a0.35um CMOS

• VDL: 2.4 mm2

• Counters: 3.1 mm2

• BIG Circuit!!

N. Abaskharoun & G. Roberts CICC’2001



Jitter MeasurementGuassian and Sinusoidal Distributions



Vernier Delay Line (VDL)Overcome Drawbacks

D Q

Data

Clock

Counter

D Q D Q D Q

τs

Clock

Data

counter_1 counter_2 counter_n

τs τs

τf τf τf

Single VDL stage



Component-Invariant VDLComplete Circuit

Enable

DataD Q

R

Enable

ClockD Q

R

τs

τf

D QQB

D QQB

EdgeDetector

Triggered Oscillator Phase Detector

Triggered OscillatorEdge

Detector

Counter

US & Canada Patent Pending



55 ps (19 ps) Timing AnalyzerA. Chan & G. W. Roberts, CICC’2002

• 0.18 µm TSMC CMOS

process

• 0.12 mm2 per component-

invariant VDL

• Expected resolution: ~ 10 ps

• Measured resolution: 19 ps

• Highest clock input frequency:

5 GHz

• Test time: ~ 150 ns/sample

(6.66 MHz sampling rate) 0.4 mm

0.3 mm



Experimental Results IC Implementation – Pseudo Gaussian Distribution

124.5 ps158.2 psPeak to peak Jitter18.68 ps21.1 psRMS JitterWavecrestVDL

VDLWavecrest

VDL Timing resolution = 19 ps



Experimental Results IC Implementation – Pseudo Sinusoidal Distribution

VDL Timing resolution = 19 ps

197.8 ps234.5 psPeak to peak Jitter41.94 ps32.5 psRMS JitterWavecrestVDL

VDLWavecrest



Experimental Results Mean Value of VDL Jitter Distribution Vs. Wavecrest



Conclusions• Present and future SOC will require some form of

Design-For-Test (DFT) to aid the test process.– Embedded cores can be accessed externally with an

analog test bus and ATE

– On-chip digitizer is essential for high-speed and low noisemeasurements.

– Signal generator + digitizer provides full tester capability onchip.

• Numerous test instruments have been fabricateddirectly on-chip and can serve as a foundation forthe engineering laboratory of the future.

Mixed-Signal Measurement Circuits For Embedded Test … · Core for Analog and Mixed-Signal Circuits,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 4, pp. 499-514, April 2002.

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