Mixed-Signal Circuits and Systems Lab Advisor: Shye-Jye Jou 周世傑
周世傑 (Shyh-Jye Jou)
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Research Area and current Projects:Digital
Communication Circuit, VLSI design, Mixed-Signal Electronics
circuit• System Technologies and Applications for Smart Campus (MOST_BL)
• 5-th mobile communications (5G) transceiver system and key chip design
technology (MOST)
• Collaborative Artificial Neural Network Computing Platform Using
In-Memory-Processing Technology (MOST_AI)• Low-power Design techniques and system application (TSMC)
Experience
University of Illinois,
Urbana-Champaign USA
Visiting Research Professor in the Coordinated
Science Laboratory
1993-1994
2010
Ministry of S&T
Circuits & Systems
Research Lab. of Bell
Laboratories USA
Director General: Science Education & Intl.
Coops
Visiting Research Consultant
2016-2017
2001
NCTU Chairman: Electronics Engineering Department
Vice President: International Affair
2011-2015
5G/B5G Frontier Technology
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Chip Technology
3GPP Standard MeetingIntelligent multimode
Network Technology
Physical Layer
Technology
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mmW Wireless Digital Communication System
無線通訊之數位積體電路架構與電路設計
Digital Baseband IC design
中距離的無線本地型區域網路 (Wireless Local Area Network,
WLAN) –IEEE 802.11ad/ay
5G+ mobile communication
Faster than the current 5G using 6 GHz band
5G Mobile Communication
Throughput rate >10 Gbps
Beyond-OFDM modulation technology:
Filter Bank MultiCarrier (FBMC) and Offset QAM (OQAM)
Weighted overlap and adding (WOLA)
Co-time Co-frequency Duplex (CCFD)
Peak-to-Average power ratio (PAPR) compensation
Self-healing for analogy and RF circuits
Massive MIMO beam forming technology
24/28/60/80 GHz band mmW
wavelength () < 1 cm, massive antenna at base station ispossible.
Beam forming to reduce power requirement and interference
Everything You Need to Know About 5G: IEEE
Spectrum at Youtube
三維通信網路技術及其在智慧校園之應用3DNET Technologies and Applications for Smart Campus
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• mmW10-Gb/s wireless communication TX/RX
baseband Chip from NCTU 2018
• Tsmc CMOS 28 nm HPC+ process
• More than 1 M gates with 625 MHz clock frequency:
1nJ/bits, the best so far.
Collaborative Artificial Neural
Network Computing Platform Using
In-Memory-Processing Technology
Principal Investigator: Tian-Sheuan Chang
Co-PIs: Tuo-Hung Hou, Bo-Cheng Charles
Lai, Shyh-Jye Jou
Department of Electronics Engineering
National Chiao Tung University, Hsinchu, Taiwan.
2018/05/17
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The Motivation
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• Three major problems faced by current AI chip computing platforms:
➢High cost and high power consumption.
➢High data bandwidth.
➢Distributed data processing.
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AlextNet Overfeat VGG-19 GoogLeNet ResNet-152
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Computational complexity and Data amount
Computational complexity Data amount
(https://arxiv.org/pdf/1605.07678.pdf)
Expected Results and Milestones
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Inference chip Online training chip
AI Central Node
(Smart Hub)
Send some data to central node
Accept model from central nodeDistributed learning
with central node
AI Edge node AI Edge node
Pattern/Speech recognition, communication system with
self-healing
系統架構
D$: Data cache, I$: Instruction Cache
ISC: In-SRAM-Computing, IRC: In-RRAM-Computing
NDC: Near-DRAM-Computing
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Mapping Neural Network to In-Memory Computing
M: input depth, N: output depth, Dk: kernel size
Convolutional neural network
Kernel size K*K
array height (input) = K*K*M, Array width (output) = N
Typical value: M, N = 128, 256, 512, 1024 and K: 3~11
One column stores one filter weight
It is the same array architecture as a fully connected layer
Only difference: CNN needs to store intermediate output in a
buffer
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CNN – Color Image
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image
Source: Convolutional Neural Network, Hung-yi Lee
Expected Results
and International Cooperation
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In-Memory-Processing AI Acceleration Algorithm andHardware Architecture
Comparing to IBM True North、Google TPU and NVidia, the studyimproves the efficiency of area or power consumption by more than twoorders of magnitude.
Reliable and effective accelerating various kinds of AI algorithms.
IC chip with in-memory-processing ability for widely application.
Collaborative Artificial Neural Network Computing Platform
Compared with traditional CPU-based distributed computing platform, theproposed methods improve the power consumption more than one order ofthroghput/Watt.
Compared to a distributed computing platform with large enterprise-classGPUs, improve more than one order of throughput/Watt/dollar cost.
Be the first flexible software/hardware platform for collaborative artificialneural network applications.
AI Computation Using
RRAM Memory Processing
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• Parallel Computing.
• High integration density.
• Low Data Transmission Rate.
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Energy
efficiency
Area
efficiency
(GOPs/mm2)
CPU 0.011 GOPs/J 0.006
GPU 2.9 GOPs/J 0.82
FPGA 3.32 GOPs/J -
ASIC 151GOPs/J 3.43
RRAM 176TOPs/J 1015
AI Edge
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• TSMC’S 30th Anniversary Celebration: the Next 10 Years – Era of AI.
• GTC Taiwan 2017- “AI-on-Device or AIoD” is the most
advantages in the development of AI in the future in Taiwan.
AIoD– A step toward “Why Taiwan Matters”
Slogan of 6G
6G will penetrate deeper into society and
lives of people than anything we have seen
so far. It will be very complex and besides
communication deals with data collection,
processing and ubiquitous intelligence