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Mixed-Signal Circuits and Systems Lab Advisor: Shye-Jye Jou 周世傑
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Mixed-Signal Circuits and Systems Lab

Mar 18, 2022

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Page 1: Mixed-Signal Circuits and Systems Lab

Mixed-Signal Circuits

and Systems Lab

Advisor: Shye-Jye Jou

周世傑

Page 2: Mixed-Signal Circuits and Systems Lab

周世傑 (Shyh-Jye Jou)

2

Research Area and current Projects:Digital

Communication Circuit, VLSI design, Mixed-Signal Electronics

circuit• System Technologies and Applications for Smart Campus (MOST_BL)

• 5-th mobile communications (5G) transceiver system and key chip design

technology (MOST)

• Collaborative Artificial Neural Network Computing Platform Using

In-Memory-Processing Technology (MOST_AI)• Low-power Design techniques and system application (TSMC)

Experience

University of Illinois,

Urbana-Champaign USA

Visiting Research Professor in the Coordinated

Science Laboratory

1993-1994

2010

Ministry of S&T

Circuits & Systems

Research Lab. of Bell

Laboratories USA

Director General: Science Education & Intl.

Coops

Visiting Research Consultant

2016-2017

2001

NCTU Chairman: Electronics Engineering Department

Vice President: International Affair

2011-2015

Page 3: Mixed-Signal Circuits and Systems Lab

5G/B5G Frontier Technology

3

Chip Technology

3GPP Standard MeetingIntelligent multimode

Network Technology

Physical Layer

Technology

Page 4: Mixed-Signal Circuits and Systems Lab

5G/B5G Frontier Technology

MOST

Page 5: Mixed-Signal Circuits and Systems Lab

5

mmW Wireless Digital Communication System

無線通訊之數位積體電路架構與電路設計

Digital Baseband IC design

中距離的無線本地型區域網路 (Wireless Local Area Network,

WLAN) –IEEE 802.11ad/ay

5G+ mobile communication

Faster than the current 5G using 6 GHz band

Page 6: Mixed-Signal Circuits and Systems Lab

6

Page 7: Mixed-Signal Circuits and Systems Lab

Back Haul Network with 10

Gbps per stream

7

Page 8: Mixed-Signal Circuits and Systems Lab

Starlink Satellite Constellation

8

Page 9: Mixed-Signal Circuits and Systems Lab

9

Takehiro Nakamura, NTT DOCOMO, Inc.

Page 10: Mixed-Signal Circuits and Systems Lab

5G Mobile Communication

Throughput rate >10 Gbps

Beyond-OFDM modulation technology:

Filter Bank MultiCarrier (FBMC) and Offset QAM (OQAM)

Weighted overlap and adding (WOLA)

Co-time Co-frequency Duplex (CCFD)

Peak-to-Average power ratio (PAPR) compensation

Self-healing for analogy and RF circuits

Massive MIMO beam forming technology

24/28/60/80 GHz band mmW

wavelength () < 1 cm, massive antenna at base station ispossible.

Beam forming to reduce power requirement and interference

Everything You Need to Know About 5G: IEEE

Spectrum at Youtube

Page 11: Mixed-Signal Circuits and Systems Lab

三維通信網路技術及其在智慧校園之應用3DNET Technologies and Applications for Smart Campus

11

• mmW10-Gb/s wireless communication TX/RX

baseband Chip from NCTU 2018

• Tsmc CMOS 28 nm HPC+ process

• More than 1 M gates with 625 MHz clock frequency:

1nJ/bits, the best so far.

Page 12: Mixed-Signal Circuits and Systems Lab

Circuits and Systems:

Qualcomn Future 5G

12

Page 13: Mixed-Signal Circuits and Systems Lab

Collaborative Artificial Neural

Network Computing Platform Using

In-Memory-Processing Technology

Principal Investigator: Tian-Sheuan Chang

Co-PIs: Tuo-Hung Hou, Bo-Cheng Charles

Lai, Shyh-Jye Jou

Department of Electronics Engineering

National Chiao Tung University, Hsinchu, Taiwan.

2018/05/17

13

Page 14: Mixed-Signal Circuits and Systems Lab

The Motivation

14

• Three major problems faced by current AI chip computing platforms:

➢High cost and high power consumption.

➢High data bandwidth.

➢Distributed data processing.

0.5

1

2

4

8

16

32

64

128

0.01

0.1

1

10

C1

C2

C3

C4

C5

F6

F7

F8

C1

C2

C3

C4

C5

F6

F7

F8

C1

C2

C3

C4

C5

F6

F7

F8

C1

C2

I3-a

I3-b

I4-a

I4-b

I4-c

I4-d

I4-e

I5-a

I5-b F6

C1

C2

C3

C4

C5

F6

AlextNet Overfeat VGG-19 GoogLeNet ResNet-152

Dat

a am

ount

(M

illio

ns)

Com

puta

tioa

l com

plex

ity

(GM

AC

s)

Computational complexity and Data amount

Computational complexity Data amount

(https://arxiv.org/pdf/1605.07678.pdf)

Page 15: Mixed-Signal Circuits and Systems Lab

Expected Results and Milestones

15

Inference chip Online training chip

AI Central Node

(Smart Hub)

Send some data to central node

Accept model from central nodeDistributed learning

with central node

AI Edge node AI Edge node

Pattern/Speech recognition, communication system with

self-healing

Page 16: Mixed-Signal Circuits and Systems Lab

系統架構

D$: Data cache, I$: Instruction Cache

ISC: In-SRAM-Computing, IRC: In-RRAM-Computing

NDC: Near-DRAM-Computing

Page 17: Mixed-Signal Circuits and Systems Lab

17

Mapping Neural Network to In-Memory Computing

M: input depth, N: output depth, Dk: kernel size

Convolutional neural network

Kernel size K*K

array height (input) = K*K*M, Array width (output) = N

Typical value: M, N = 128, 256, 512, 1024 and K: 3~11

One column stores one filter weight

It is the same array architecture as a fully connected layer

Only difference: CNN needs to store intermediate output in a

buffer

Page 18: Mixed-Signal Circuits and Systems Lab

18

CNN – Color Image

1 0 0 0 0 1

0 1 0 0 1 0

0 0 1 1 0 0

1 0 0 0 1 0

0 1 0 0 1 0

0 0 1 0 1 0

1 0 0 0 0 1

0 1 0 0 1 0

0 0 1 1 0 0

1 0 0 0 1 0

0 1 0 0 1 0

0 0 1 0 1 0

1 0 0 0 0 1

0 1 0 0 1 0

0 0 1 1 0 0

1 0 0 0 1 0

0 1 0 0 1 0

0 0 1 0 1 0

1 -1 -1

-1 1 -1

-1 -1 1Filter 1

-1 1 -1

-1 1 -1

-1 1 -1Filter 2

1 -1 -1

-1 1 -1

-1 -1 1

1 -1 -1

-1 1 -1

-1 -1 1

-1 1 -1

-1 1 -1

-1 1 -1

-1 1 -1

-1 1 -1

-1 1 -1Color

image

Source: Convolutional Neural Network, Hung-yi Lee

Page 19: Mixed-Signal Circuits and Systems Lab

19

Page 20: Mixed-Signal Circuits and Systems Lab

Expected Results

and International Cooperation

20

In-Memory-Processing AI Acceleration Algorithm andHardware Architecture

Comparing to IBM True North、Google TPU and NVidia, the studyimproves the efficiency of area or power consumption by more than twoorders of magnitude.

Reliable and effective accelerating various kinds of AI algorithms.

IC chip with in-memory-processing ability for widely application.

Collaborative Artificial Neural Network Computing Platform

Compared with traditional CPU-based distributed computing platform, theproposed methods improve the power consumption more than one order ofthroghput/Watt.

Compared to a distributed computing platform with large enterprise-classGPUs, improve more than one order of throughput/Watt/dollar cost.

Be the first flexible software/hardware platform for collaborative artificialneural network applications.

Page 21: Mixed-Signal Circuits and Systems Lab

AI Computation Using

RRAM Memory Processing

21

• Parallel Computing.

• High integration density.

• Low Data Transmission Rate.

H1

X1

X2

XI

1

G11

G21

GI1

b1

G12

G22

GI2

b2

… …

G1J

G2J

GIJ

bJ

Gr

Gr

Gr

H2

+ _∑

+ _∑

_+

HJ

Weighted Sum Weight Update

X1

X2

XI

1

G11

G21

GI1

b1

G12

G22

GI2

b2

… …

G1J

G2J

GIJ

bJ

…H1

BP H2BP HJ

BP

( )

( )

1

1

( )I

H

j a j a i ij

i

I

a i ij r

i

H f S f X W

f X G G

=

=

= =

= −

( )BP

ij i jG G X H =

Energy

efficiency

Area

efficiency

(GOPs/mm2)

CPU 0.011 GOPs/J 0.006

GPU 2.9 GOPs/J 0.82

FPGA 3.32 GOPs/J -

ASIC 151GOPs/J 3.43

RRAM 176TOPs/J 1015

Page 22: Mixed-Signal Circuits and Systems Lab

One UCE Architecture for

IN-Memory Computing

22

Page 23: Mixed-Signal Circuits and Systems Lab

Application:

Possible Layout Floor Plan

23

Page 24: Mixed-Signal Circuits and Systems Lab

The current status of ISC

computing URAM (= 4UCE + DLL) Layout Floorplan

1700.055

um

11

76

um

Page 25: Mixed-Signal Circuits and Systems Lab

AI Edge

25

• TSMC’S 30th Anniversary Celebration: the Next 10 Years – Era of AI.

• GTC Taiwan 2017- “AI-on-Device or AIoD” is the most

advantages in the development of AI in the future in Taiwan.

AIoD– A step toward “Why Taiwan Matters”

Page 26: Mixed-Signal Circuits and Systems Lab

Slogan of 6G

6G will penetrate deeper into society and

lives of people than anything we have seen

so far. It will be very complex and besides

communication deals with data collection,

processing and ubiquitous intelligence

Page 27: Mixed-Signal Circuits and Systems Lab

2018.09

Canoeing in Pacific Coast

27

Page 28: Mixed-Signal Circuits and Systems Lab

28

MS/Ph.D Farewell Party 2019/06