Microprocessor & Microcontrollers Module 2

5

Pin Connectionsbull A19S6-A16S3 addressstatus bus(multiplexed)

ndash memory address A19-A16 status bits S6-S3

ndash high-impedance state during a hold acknowledge

ndash S6 always remain a logic 0

ndash S5 indicate condition of IF flag bits

ndash S4 S3 show which segment is accessed during current bus cycle(Table 9-4)

ndash S4 S3 can used to address four separate 1M byte memory banks by decoding them as A21 A20

6

Pin Connectionsbull RDrsquo read signal

ndash data bus receive data from memory or IO device RDrsquo=0

ndash high-impedance state during a hold acknowledge

bull READY ndash micro enter into wait states and remain idle READY = 0

ndash no effect on the operation of micro READY = 1

bull INTR interrupt requestndash used to request a hardware interrupt

ndash if INTR is held high when IF = 1 micro enter interrupt acknowledge cycle(INTArsquo become active) after current instruction has complete execution

7

Pin Connectionsbull TESTrsquo(BUSYrsquo) tested by the WAIT instruction

ndash WAIT instruction function as a NOP if TESTrsquo= 0

ndash WAIT instruction wait for TESTrsquo to become 0if TESTrsquo=1

bull NMI non-maskable interruptndash similar to INTR except that no check IF flag bit

ndash if NMI is activated use interrupt vector 2

bull RESET ndash micro reset if RESET held high for a minimum of four clock

bull CLK(CLOCK) provide basic timing to microndash duty cycle of 33

bull VCC(power supply) +50V plusmn10

8

Pin Connectionsbull GND(Ground) two pins labeled GND

bull MNMXrsquo select either minimum or maximum mode bull BHErsquoS7 bus high enable

ndash enable the most significant data bus bits(D15-D8) during read or write operation

ndash status of S7 always a logic 1

bull Minimum Mode Pins MN = 1(directly to +50V) next p

bull IOMrsquo(8088) or MIOrsquo(8086) select memory or IO

ndash address bus whether memory or IO port address

bull WRrsquo write signal(high impedance state during hold ack)

ndash strobe that indicate that output data to memory or IO

ndash during WRrsquo=0 data bus contains valid data for M or IO

9

Fig 9-1bull Fig 9-1

10

Minimum Mode Pinsbull INTArsquo(interrupt acknowledge) response to INTR input pin

ndash normally used to gate interrupt vector no onto data bus

bull ALE(address latch enable) does not float during hold ack

ndash addressdata bus contain address information

bull DTRrsquo(data transmitreceive)

ndash data bus transmit(DTRrsquo=1) or receive(DTRrsquo=0) data

ndash used to enable external data bus buffers

bull DEN(data bus enable) activate external data bus buffers

bull HOLD request a direct memory access(DMA)ndash if HOLD=1 micro stops executing software and places

address data and control bus at high-impedance state

ndash HOLD=0 micro execute software normally

11

Minimum Mode Pinsbull HOLDA(hold acknowledge)indicate micro has entered hold state

bull SS0rsquo equivalent to S0 pin in maximum mode operation

ndash combined with IOMrsquo DTRrsquo to decode function of current bus cycle(Table 9-5)

12

Maximum Mode Pinsbull MNMXrsquo = 0(ground) next page

bull S2rsquoS1rsquoS0rsquoindicate function of current bus cycle(T 9-6)

ndash these signal normally decoded by 8288 bus controller

13

Fig 9-1bull Fig 9-1

14

Maximum Mode Pinsbull R1rsquoGT1rsquo R0rsquoGT0rsquo(requestgrant) request DMA

ndash bi-directional request and grant DMA operation

bull LOCKrsquo(lock output) used to lock peripherals off the system

ndash activated by using the LOCK prefix on any instruction

bull QS1 QS0(queue status)

ndash show status of internal instruction queue Table 9-7

ndash provided for access by the numeric coprocessor(8087)

15

Fig 9-4bull Fig 9-4

16

9-3 Bus Buffering and Latchingbull Demultiplexing the Buses

ndash addressdata busmultiplexed(shared) to reduce no of pins

ndash memory and IO require that address remains valid and stable throughout a read and write cycle

bull all computer systems have three busesndash address bus provided memory and IO with memory

address or IO port number

ndash data bus transferred data between micro and memory or IO

ndash control bus provided control signal to memory and IO

bull Demultiplexing the 8088 Fig 9-5ndash two 74LS373 transparent latches

ndash pass inputs to outputs whenever ALE become 1

ndash after ALE return 0 remember inputs at time of change to 0

17

Fig 9-5bull Fig 9-5

18

9-3 Bus Buffering and Latching

bull Demultiplexing the 8086 Fig 9-6ndash demultiplexing AD15-AD0 A19S6-A16S3 BHErsquoS3

ndash 3 buses address(A19-A0 BHErsquo) data(D15-D0) control(MIOrsquo RDrsquoWRrsquo)

ndash three 74LS373 transparent latches

bull The Buffered Systemndash micro system must be buffered if more than 10 unit load

are attached to any bus pin

ndash demultiplexed pins already buffered by 74LS373 latch

ndash bufferrsquos output currents increased 32mA of sink current(0) 52mA of source current(1)