Microprocessor and Microcontrroller Module 2 - Calicut University

8/3/2019 Microprocessor and Microcontrroller Module 2 - Calicut University

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8255 PPI

A device used to implement data transferbetween processor and peripherals likeADC, DAC, keyboard, 7 segment display

Has three 8 bit ports- Port A, Port B, Port CHas three operating modes

Mode 0 - Simple I/O

Mode 1 Handshake I/O

Mode 2-Bidirectional I/O


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8255 PPI


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8255 PPI

A - can be programmed as input or outputport. It can also be an 8-bit bidirectional port.

B - also can be programmed as in input oroutput port. It cannot be used as an 8-bit bi-

directional port.

C - can also be either an input or an outputport. Can be split into two 4 bit ports. Each 4

bit port can be either an input or an outputport. Also, bits of C port can be set/resetindividually through program.


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Modes of operation of 8255

Mode 0All three ports can be programmed as eitherinput or output port.

Outputs are latched and inputs are notlatched.

This mode can be used to interface DIP

switches, LEDs, hex keypad, 7 segmentdisplay


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Mode 1

Here only Port A and B can be programmedas input/output port.

Handshake signals are exchanged betweenprocessor and peripheral.

Port C provides the hand shake signals.Input and output data are latched.

Interrupt driven data transfer schemepossible


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Mode 2

Port A can be programmed as bidirectionalport.

Five pins of Port C provide the handshakesignals.

Port B can be in mode 0 or mode 1Used in applications such as data transferbetween computers or floppy diskcontroller interface


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Addressing ports of 8255

CS A0 A1

Port

Selection

0 0 0 Port A

0 0 1 Port B

0 1 0 Port C0 1 1 Control

register

1 x x 8255 notselected

Has two control wordsI/O Mode Set Control Word(MSW)Bit Set Reset Mode (BSR)


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Control Word- I/O Mode


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Control Word-BSR Mode


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Mode 1 of 8255 (Port A - Input Port)


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Mode 1 of 8255 (Port A - Input Port)

If IBFA signal is low input device place data

on PA0-PA7STBA is asserted low and data is latched atport and IBFA is set to high

INTRA is set high and processor is interruptedthrough NMI

RD is asserted low and data is read from port

A, IBFA is set to low and the input device cansend the next data

For Port B as input port handshake signals

provided by PC0,PC1,PC2 are used.


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Mode 1 of 8255 (Port A - Output Port)


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Mode 1 of 8255 (Port A - Output Port)WR is asserted low and processor writes to

output portOBFA is asserted low indicating that outputbuffer is full.

The output device accepts the data andsends the acknowledgement by assertingACKA low.

The processor is interrupted through INTRAsignal given through NMI

For Port B as output port handshake signals

provided by PC0,PC1,PC2.


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Mode 2 of 8255


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Interfacing of 8255 with 8086


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DMA Data Transfer Scheme

Normal data transfer between memory and I/O

device take place through processor.

DMA enables data transfer directly between I/Oand memory.

This will allow large amount of data transfer in ashort time.

For this a dedicated hardware called DMA

Controller is used.

DMA controller temporarily borrows the systembus from the processor and transfer the data

bytes directly.


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Block diagram DMA Controller


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DMA Transfer

Has a number of channels and each channel

can may service an I/O independently

Each channel has a address register, controlregister and count register.

DMA controller works as master or slave

In slave mode the processor loads theaddress register with starting address, count

register with no of bytes and control registerwith control information.


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DMA Transfer

I/O needs DMA transfer

First DMA request signal is sent to DMAcontroller

DMA controller sends hold request to

processor

At the end of current instruction processorrelease the control of buses.

Processor sends hold acknowledgement

DMA controller takes control of systembus (starts master mode)


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DMA Transfer

DMA controller sends DMA acknowledgement

With this the device is ready for data transfer

DMA Read Operation

Controller output the memory address on

address bus

Asserts memory read and IO write signals

Memory output the data on data bus and this iswritten to IO port


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DMA Transfer

DMA write operation

DMA controller output the memory addressand asserts memory write and IO readsignals

IO device output data on data bus and iswritten to memory

After data transfer the processor takes

control of busesDMA can be as bytes of data or blocks ofdata.


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DMA Transfer

Cycle stealing DMA-byte data transfer inbetween instruction cycles.

Burst Mode DMA- Blocks of data aretransferred


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Internal Architecture of 8257


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Features of 8257 DMA Controller

It has four DMA channels to service 4 I/O

devices.

Each channel can be independentlyprogrammed to transfer upto 64kbytes of data

by DMA.

Each channel has two programmableregisters- One to program the starting address

of memory location for DMA data transfer.Another to program a 14 bit count value and a2 bit code for type of DMA (read/write/verify).


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Read Transfer-Data is transferred from

memory to I/O device.Write Transfer- Data is transferred fromI/O device to memory.

Verification-generates the DMA addresseswithout DMA memory and I/O signals.

Mode set register-Used to program

various features of 8257Status register-can be read to know theterminal count status of the channels.

F t f 8257 DMA C t ll


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Registers are addressed during slavemode through A3-A0 lines.

Channel 0 DMA add. reg. 0 0 0 0

Channel 0 Count reg. 0 0 0 1

Channel 1 DMA add. Reg. 0 0 1 0Channel 1 Count reg. 0 0 1 1

Channel 2 DMA add. Reg. 0 1 0 0

Channel 2 DMA Count reg. 0 1 0 1Channel 3 DMA add. Reg. 0 1 1 0

Channel 3 Count reg. 0 1 1 1

Mode wr. /Status rd. 1 0 0 0


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Count register of 8257

M d S t R i t


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Mode Set Register

St t R i t


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Status Register

DMA ti i 8086 i 8257


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DMA operation in 8086 using 8257

Slave Mode- Control word is send to mode

register, program count and addressregisters of the required DMA channels.

8257 will keep on checking for DMA

request from peripherals.DMA sequence of operations are asfollows

Peripheral will assert DRQ signal highA channel is enabled and 8257 will assertHRQ high

DMA operation in 8086 sing 8257


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8086 will complete the current instruction

execution, drive all its buses to highimpedance state and asserts HLDA signal

8257 on receiving acknowledgement from

8086 will send DACK.8257 asserts AEN high which enable DMAmemory address latches and disable

processor address latches.8257 outputs the DMA address ADSTB isasserted to latch the address in externallatches.



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Once address is output on address lines the

content of address register is incremented byone and count register is decremented byone.

8257 asserts appropriate read and writesignals to perform DMA transfer betweenperipheral and memory.

After performing one byte transfer the stepsof loading address and DMA transfer isrepeated till TC.

Interfacing 8086 with 8257


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Interfacing 8086 with 8257

8259 Programmable Interrupt Controller


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Manage 8 interrupts according to instructionswritten to its control register.

Vector an interrupt anywhere in the memorymap

Resolve 8 levels of interrupt priorities in avariety of modes such as fully nested mode,automatic rotation mode, specific rotationmode.

Mask each interrupt individually.

8259 P mm bl I t t C t ll


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Be set up to accept either the leveltriggered or edge triggered interruptrequest.

Read the status of In service Interrupt,pending interrupts and masked interrupts.

Can be expanded to 64 priority levels bycascading additional 8259s.

Can be interfaced with 8085 and 8086.



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Interrupt Handling of 8259


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IRR stores requests

Priority resolver checks 3 registers. IRRfor requests, IMR for masking bits and ISRfor interrupt being serviced. It then

resolves priority and set the appropriateINT high.

Processor acknowledge the interrupt

through INTA.With INTA the appropriate bit is set in ISRand the corresponding bit in IRR is reset.

Opcode for CALL is placed on data bus


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Program sequence is transferred to memorylocation specified by CALL instruction.

Interrupt can be accepted in edge triggeredmode or level triggered mode according toinitialization instruction.

Status of IRR, ISR and IMR can be read

which will make the interrupt processversatile.

Programming 8259


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Programming 8259

Requires two types of command words

Initialization Command Word(ICW)Operational Command Word(OCW)

Initialized with 4 ICWs-2 are essential and

other 2 are optional based on modes.

The words should be issued in a sequence

8259 can be made to operate in various

modes by 3 OCWs


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ICW1


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ICW2

Interrupt type MSB 5 bits and LSB 3 bitsare 0 IR0


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ICW3 Master Device


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ICW3 Slave Device

This gives the slave identification number


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ICW4


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Operating Modes of 8259

Fully Nested Mode

Default mode of operation IR0 has highestpriority and IR7 lowest.

Corresponding ISR bit is set till EOI isreceived.

Lower priority interrupts are inhibited andhigher priorities are allowed.


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End of Interrupt

ISR is reset with AEOI of ICW4 or by EOI

2 types of EOI-specific and non specific

Non specific EOI-Automatically resethighest ISR bit (fully nested mode)

Specific EOI-This is to reset a particularISR bit.


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Automatic Rotation

IR level receives lowest priority after it isserved.

Next device to be served gets highestpriority.

Automatic EOI

8259 performs a automatic non specificEOI(ICW4)


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Specific Rotation

Bottom priority can be selected throughOCW2.

If IR6 has bottom priority, IR5 next priority

and IR7 highest priority.

Priorities can be changed by setting rotateon specific EOI in OCW2

Special Mask Mode

When a mask bit is set in OCW1 , furtherinterrupts are masked at that level and

enables interru ts from other levels


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Poll Command

8259 is polled by using software executionby microprocessor instead of requests onINT input. Set through OCW3.

Special Fully Nested Mode

Used in cascading mode to programpriority in master using ICW4.

Master interrupts the CPU only when theinterrupting device has a higher prioritythan the one currently being serviced



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Buffered Mode

In cascaded mode buffer is enabled throughSP/EN pin.

Cascade Mode

One master and eight slavesMaster control the slaves through CAS0-CAS3

which acts as chip select for slaves

Slave INT outputs connected to master IRinputs.

Each 8259 must be separately initialized

EOI must be issued twice


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OCW1

OCW1 must be sent to an 8259 to unmaskany IR inputs.


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OCW2

OCW2 is mainly used to reset a bit in ISR.Once ISR bit is reset 8259 can respond tointerrupt signals of lower priority.

OCW2


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OCW2

Non Specific EOI- Terminate current

interrupt being serviced by 8259. Resetthe corresponding bit in ISR of 8259 andallow higher priority interrupt.

Specific EOI-Terminate specific interruptrequest decided by lower 3 bits of OCW2.

Rotate on NEOI- rotate priority

Rotate on Automatic EOI- Select AEOIwith rotate priority

Rotate on specific EOI-same as 2 with

rotate priority.


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OCW3


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8253 Programmable Timer


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g

Time based activities of the processor can beperformed in 2 ways: Execute a delaysubroutine, Use a programmable timer

Applications of programmable timer

Interrupt a time sharing OS at specifiedintervals of time

Send periodic timing signals to IO devices

Baud rate generator-clock dividerMeasure the time between external events

Used to initiate an activity through interrupt

after a programmed no of external events



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Read/Writelogic

ControlWordregister

DataBus

Buffer

Counter 1

Counter 2

Counter 3

Internal

Bus

D7-D0

RDWRA0

A1

Clk 0

Gate 0Out 0

Clk 1

Gate 1Out 1

Clk 2

Gate 2Out 2



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Has 3 independent programmable16 bit

counters and 6 modes of operation.Each counter has clock input, gate input andcounter output.

For operation a count has to be loaded in countregister, gate should be tied high and a clocksignal is applied to clock input.

Counter counts by decrementing the countvalue by one in each cycle of clock signal andgenerates an output depending on mode ofoperation



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te a c tectu e o 8 53

8254 has 8 data lines for communication withprocessor

Address lines A0 and A1 are used to selectany one of four internal device.

A0 A10 0 Counter 0

0 1 Counter 1

1 0 Counter 21 1 Control register



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p g

There are 6 modes of operation for 8254

Mode 0 Interrupt on TC

Mode 1 Hardware retriggerable one shot

Mode 2 Rate generator

Mode 3 Square wave mode

Mode 4 Software triggered strobe

Mode 5 Hardware triggered strobeInitialization procedure for each mode

Write a control word into control register

Write a count value in count register

Mode 0


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Mode 0

Count value is loaded in count register. If the

gate is high the counter is decremented andprovide a high output when the count is zero.

Low to high transition of counter used as an

interrupt to the processor to initiate anyactivity.

Count N loaded in count register, output high

after N+1 clock pulses

Mode 1


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Mode 1

Works as a retriggerable monostable

multivibrator.Gate acts as trigger pulse to start the countprocess (low to high transition).

When count value is loaded into counterthe output is low

Output becomes high when count value is

zero.Mode 1 produces a logic low pulse whosewidth is equal to the duration of count.

Mode 2


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Used to generate a periodic low pulse of

width equal to one clock period.A count value of N loaded in count registerthe output will go low once in N clock period.

Gate should remain high.Counter is reloaded at the end and thepulses are repeated.

Mode 3


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Counter generates a square wave.

If a even number N is loaded in countregister, output will be High for N/2 clockperiod and low for the next N/2 clockperiods.

If a odd number N is loaded in countregister, output will be High for (N+1)/2clock period and low for the next (N-1) /2

clock periods.Original count is reloaded and processrepeated.

Gate is hi h

Mode 4


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Mode 4

Used to generate a single low pulse after a

delay.A count N is loaded in the counter a lowpulse of width equal to one clock period is

generated in the (N+1)th clock period.Used as a strobe signal in parallel datatransfer.

Gate is high

M d 5


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Mode 5

Same as Mode 4 except that there shouldbe a low to high transition at Gate.

If gate makes a low to high transitionbefore the end of count the original countvalue is reloaded in the next clock period.

C t l W d f 8253


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Control Word of 8253

SC1 SC2 RW1 RW0 M2 M1 M0 BCD

SC1 SC2 RW1 RW0 M2 M1 M0 BCD

0 0- Select Counter 0 0 0- Counter latch 0 0 0 Mode 0 1-BCD count01- Select Counter 1 0 1- read/Write LSB only 0 0 1 Mode 1 0-Binary count10- Select Counter 2 1 0-Read/Write MSB only x 1 0 Mode 21 1- illegal 1 1- Read/Write LSB first x 1 1 Mode 3

and then MSB 1 0 0 Mode 41 0 1 Mode 5


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8251 Programmable Communication


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8251 Programmable CommunicationInterface (USART)

A programmable chip designed forsynchronous and asynchronous serialdata communication.

There are 3 modes of serial datatransmission

Simplex

Duplex

Half Duplex

S i l D t T i i


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Serial Data Transmission

Simplex-Data transmitted only in onedirection.

Duplex-Data may transmitted in bothdirections simultaneously.

Half Duplex-Data may be transmitted inboth directions but at a time in only onedirection


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Serial data transmission can be insynchronous mode or asynchronous mode

Synchronous Mode

Receiver and Transmitter are synchronized.Data is sent in blocks at a constant rate

The start and end of the blocks are

specified with specific patterns.



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Asynchronous Mode- Receiver andTransmitter are not synchronized.

Each data character has a bit which identifiesits start and stop characters.

When no data is sent, line is high - mark state.

Beginning of data character is indicated by theline going low for 1 bit time - start bit.

Data is sent which may be 5,6,7 or 8 bits

Parity bits are then sent to check error

Signal line goes high for 1,11/2 ,2bits-Stop bits



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Read/WriteControllogic

ModemControl

register

DataBus

Buffer

Transmit

Buffer

TransmitControl

Receive

Control

Int

ernal

Bus

D7-D0

RDWRResetClkC/DCS

Tx D

Tx RDYTx ETx C

Rx RDYRx CSyndet/BD

DSRDTR

CTSRTS

ReceiveBuffer

RxD

8251 Pin Functions


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D7-D0-Data bus

C/D-Control or Data is to be written or readRD-Read data command

WR-Write data command

CS-Chip Select

CLK-Clock Pulse

RESET-Reset

TxC-Transmitter clock

RxC-Receiver clock

8251 Pin Functions


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8251 Pin FunctionsRxD-Receive Data

RxRDY-Receiver Ready(has character forCPU)

TxRDY-Transmitter ready (ready for character

from CPU)DSR-Data set ready

DTR-Data terminal ready

RTS-request to send data

CTS-Clear to send data

TxEMPTY-transmitter empty

8251 Pin Functions


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8251 Pin Functions

Syndet / BD-Synchronous detect/Break

detect

In synchronous data transmission the pinwill go high if sync characters are

detected.In asynchronous transmission the pin willgo high if RxD line goes high for more than

2 character times. This indicates anintentional break in transmission

Transmitter Section


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Transmitter Section

Converts 8 bit data to serial data

TransmitterBuffer

Transmit

Control Logic

Output Reg Tx D(Transmit Data)

Tx C

Tx RDYTx E

Receiver Section


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Receiver Section

Receives serial data and sends parallel data

ReceiverBufferregister

Receiver

Control Logic

Input Reg Rx D(Receives data)

Rx C

Rx RDYSyndet/BD

Initializing 8251


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Initializing 8251

16 bit control register for control word

16 bit status register for checking readystatus of input registers

To initialize 8251 send a mode word andthen a command word to the controlregister


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Mode Word

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D00 0-Not valid x 0- No parity 0 0-5 bits 0 0-Syn Mode0 1-1Stop bit 0 1-Odd parity 0 1-6 bits 0 1-Asyn x11 0-11/2 Stop bit 1 1-Even Parity 1 0-7 bits 1 0-Asyn x 161 1-2 Stop bit 1 1-8 bits 1 1-Asyn x 64

FramingControl

ParityControl

CharacterLength

Baud ratefactor

Control Word


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*-Bits for synchronous format modem

control* EH IH *RTS ER *SBRK Rx E *DTE Tx EN

1-Enablesearch for synccharacterNo effect onasyn mode

Internal

Reset

1-Enable

Error Reset

1-reseterror flagsPE,OE,FE

Send Breakcharacter1-forces TxD

low

1-Enable0-Disable 1-Enable

DTR

1-Enable0-Disable

Status Word


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DSR-indicates DSR is at low level

PE-Set with parity error. Reset with errorbit of command word

0E-Set when CPU does not read a

character before next is available.FE-Async mode only. Set when valid stopbits is not detected.

DSR SYNDET/

BRKDET

FE OE PE TxEMPTY RxRDY TxRDY

Microprocessor and Microcontrroller Module 2 - Calicut University

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