© 2017 From Technologies to Market MicroLED Displays 2018 From Technologies to Market Courtesy of Sony Sample © 2018
© 2017
From Technologies to Market
MicroLEDDisplays 2018
From Technologies to Market
Courtesy of Sony
Sample© 2018
2
OBJECTIVE OF THE REPORT
Deep understanding
of the technology,
current status and prospects,
roadblocks and key players.
• Understand the Current Status of the µLED Display Technologies:
• What are microLED? What are the key benefits? How do they differ from other display technologies? What are the costdrivers?
• What are the remaining roadblocks? How challenging are they?
• Detailed analysis of key technological nodes: epitaxy, die structure and manufacturing, front plane structure and display designs,color conversion, backplanes, massively parallel pick and place and continuous assembly processes, hybridization, defectmanagement, light extraction and beam shaping.
• Which applications could µLED display address and when?
• Detailed analysis of major display applications: TV, smartphones, wearables, augmented and virtual reality (AR/VR/MR), laptopsand tablets, monitors, large LED video displays...
• What are the cost targets for major applications? How do they impact technology, design and process choices?
• How disruptive for incumbent technologies: LCD, OLED, LCOS…
• MicroLED display application roadmap, forecast and SWOT analysis
• Competitive Landscape and Supply chain
• Identify key players in technology development and manufacturing.Who owns the IP?
• Potential impact on the LED supply chain: epimakers, MOCVD reactor and substrate suppliers.
• Potential impact on the display chain: LCD and OLED panel makers.
• Scenario for a µLED display supply chain.
Everything You Always Wanted to Know About µLED Displays!
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Biography & contact
EricVirey - Principal Analyst,Technology & Market, Sapphire & DisplayDr. Eric Virey serves as a Senior Market and Technology Analyst at Yole Développement (Yole), within the Photonic & Sensing & Display division. Eric isa daily contributor to the development of LED, OLED, and Displays activities, with a large collection of market and technology reports as well asmultiple custom consulting projects. Thanks to its deep technical knowledge and industrial expertise, Eric has spoken in more than 30 industryconferences worldwide over the last 5 years. He has been interviewed and quoted by leading media over the world.
Previously Eric has held various R&D, engineering, manufacturing and business development positions with Fortune 500 Company Saint-Gobain inFrance and the United States.
Dr. EricVirey holds a Ph-D in Optoelectronics from the National Polytechnic Institute of Grenoble.
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COMPANIES CITED IN THE REPORT
Aixtron (DE), Aledia (FR), Allos Semiconductor (DE), AMEC (CN), Apple (US), AUO (TW), BOE (CN), CEA-LETI (FR), CIOMP (CN), Columbia
University (US), Cooledge (CA), Cree (US), CSOT (CN), eLux (US), eMagin (US), Epistar (TW), Epson (JP), Facebook (US), Foxconn (TW),
Fraunhofer Institute (DE), glō (SE), GlobalFoundries (US), Goertek (CN), Google (US), Hiphoton (TW), HKUST (HK), HTC (TW), Ignis (CA),
InfiniLED (UK), Intel (US), ITRI (TW), Jay Bird Display (HK), Kansas State University (US), KIMM (KR), Kookmin U. (KR), Kopin (US), LG (KR),
LightWave Photonics Inc (US), Lumens (KR), Lumiode (US), LuxVue (US), Metavision (US), Microsoft (US), Mikro Mesa (TW), mLED (UK), MIT
(US), NAMI (HK), Nanosys (US), NCTU (TW), Nichia (JP), Nth Degree (US), NuFlare (JP), Oculus (US), Optovate (UK), Osterhout Design Group
(US), Osram (DE), Ostendo (US), PlayNitride (TW), PSI Co (KR), QMAT (US), Rohinni (US), Saitama University (JP), Samsung (KR), Sanan (CN),
SelfArray (US), Semprius (US), Smart Equipment Technology (FR), Seoul Semiconductor (KR), Sharp (JP), Sony (JP), Strathclyde University (UK),
SUSTech (CN), Sun Yat-sen University (TW), Sxaymiq Technologies (US), Tesoro (US), Texas Tech (US), Tianma (CN), TSMC (TW), Tyndall National
Institute (IE), Uniqarta (US), U. Of Hong Kong (HK), U. of Illinois (US), Veeco (US), VerLASE (US), V-Technology (JP), VueReal (CA), Vuzix (US), X-
Celeprint (IE)…and more.
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TABLE OF CONTENTS
• Executive summary p10
• Introduction to microLED displays p51
• Definition and history
• What is a microLED display?
• Comparisons with LCD and OLED
• Assembly
• Display structure
• SWOT analysis
• MicroLED display manufacturing yields p63
• Overview
• Individual die testing.
• KGD mapping and individual transfer
• Transfer fields and interposers
• Defect management strategies
• Yield roadmap
• Redundancy
• Conclusions
• MicroLED epitaxy (FE Level 0) p79
• Wafer size
• Wavelength homogeneity
• Epitaxy defects
• Cycle time and thickness
• Blue shift
• Wafer flatness
• GaN-based red chips
• Conclusions and impact on supply chain
• Chip manufacturing and singulation (FE Level 1) p96
• MicroLED singulation p97
• Impact on cost related to the epiwafer
• Illustrations
• MicroLED efficiency p104
• LED and microLED efficiency
• Development thrust areas
• Current confinement structures
• Status
• MicroLED chip manufacturing p112
• Example of process flow – Apple 6 masks
• Lithography
• Fab types comparison: infrastructure & equipment
• MicroLED in CMOS fabs
• Transfer and assembly technologies p124
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TABLE OF CONTENTS
• Overview p125
• Major types and key attributes of transfer processes
• Challenges
• Pick and place processes p129
• Sequence and challenges
• Transfer sequences
• Transfer arrayVs. display pixel pitch
• Throughput and cost drivers
• Direct transfer vs. interposer
• Interposer and yields
• Other use of interposers.
• Example (X-CeLeprint)
• Continuous/ semi-continuous assembly p141
• Overview
• Laser-based sequential transfer
• QMAT-TESORO
• Uniqarta
• GLO
• Optovate
• Self assembly p150
• Fluidic self assembly
• Example: Sharp/ELUX
• Summary p154
• Intellectual property landscape
• Selectivity
• Major transfer processes: most mature
• Transfer processes: others
• Conclusion
• Transfer and assembly equipment p165
• Introduction
• Traditional single chip tools
• Assembly environment
• Specific challenge for mass transfer
• Bulk microLED arrays p171
• Full array level microdisplay manufacturing.
• Hybridization & bonding process
• Wafer level bonding
• Monolithic integration of LTPS TFT: lumiode
• 3D integration: Ostendo
• Yields and costs
• Color generation in bulk arrays
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TABLE OF CONTENTS
• Pixel repair p183
• Emitter redundancy
• Example of repair strategies
• Defect management strategies
• Light extraction and beam shaping p189
• Optical crosstalk
• Emission pattern, viewing angle and power consumption
• Emission pattern and color mixing
• Die-level light management
• Array-level beam shaping
• Color conversion p204
• Overview
• Phosphors
• Quantum dots
• Flux requirements
• Patterning and deposition
• Backplanes and pixel driving p214
• Introduction
• Channel materials for microLED displays
• Mobility vs display specifications
• Stability and signal distortion
• Pixel density
• Analog driving: microLED driving regime
• MicroLED-specific challenges
• Illustration: 75” 4K TV, QHD smartphone
• Digital driving: introduction
• Digital driving: benefits & challenges
• Hybrid driving
• AnalogVs digital: summary
• TFT versus discrete micro IC.
• Cost zspects
• Cost reduction path
• Conclusions
• Economics of microLED – cost down paths p240
• Baseline hypothesis and sensitivity
• Television p247
• Cost target and price elasticity
• 75” TV panel assembly strategies
• Yield impact
• Very large panels
• Benefit of sequential transfer
• Interposers
• Die size
• Cost-down path
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TABLE OF CONTENTS
• Smartphones p265
• Cost target
• Illustration: 6” QHD phone panel
• Key outputs
• Die size optimization
• Interposers
• Applications and markets for microLED displays p277
• MicroLED attributes vs application requirement
• Application roadmap
• SWOT per application
• Key hypothesis for equipment forecast
• 2017-2027 microLED adoption forecast
• AR, MR andVR p284
• The reality-to-virtual-reality continuum.
• Market volume headset forecasts forVR and aR
• MicroLED adoption and volume forecast
• Head up displays
• Smartwatches p290
• Smartwatch volume forecast
• MicroLED Adoption and volume forecast
• Smartphones p294
• Who can afford a smartphone?
• Smartphone panel volume forecast
• Mobile phones: display for differentiation
• Foldable smartphones
• MicroLED adoption and volume forecast
• TVs p301
• The “Better Pixel”
• Resolution
• TV panel forecast
• 8K adoption
• MicroLED adoption and panel volume forecast
• Others: tablets, laptops, monitors p310
• Overview
• Tablets
• Laptop and convertibles
• Desktop monitors
• Wafer and equipment forecast p315
• Epiwafer
• MOCVD
• Transfer equipment
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TABLE OF CONTENTS
• Competitive landscape p322
• Time evolution of patent publications
• Leading patent applicants
• What happened In the last 18 months
• Time evolution of patent applications per company
• Breakdown by company headquarters
• Positioning of established panel makers
• Breakdown by company type
• Supply chain p332
• Overview
• Capex aspects
• Supply chain requirement
• Front END (LED Manufacturing)
• Back end: backplane, assembly and module.
• Supply chain scenarios
• Intellectual property
• Conclusion
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SCOPE OF THE REPORT
This report provides an
extensive review of µLED display technologies and
potential applications as
well as the competitive
landscape and key players.
Smartwatches and
wearables
Virtual reality
Large video
displays
TV
Smartphones
Laptops and
convertibles
Automotive HUD
Augmented/Mixed
Reality
LG
Samsung
HP
BMW
Microsoft
Oculus
Apple
Tablets
Acer
The report does not cover
non-display applications of
µLED: AC-LEDs, LiFi,
Optogenetics, Lithography,
lighting…
MicroLED TV prototype (Sony, CES 2012)
Contrary to the 2017
edition, this report does not
cover applications in large
LED videowalls: those will be
discussed extensively in our
upcoming report on
miniLED applications and
technologies
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SCOPE OF THE REPORTC
hip
s
(to
scale
)
Packages
(No
t to
scale
)
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WHO SHOULD BE INTERESTED IN THIS REPORT
• LED supply chain: sapphire makers, MOCVD
suppliers, epi-houses.
• Understand the µLED display opportunity
• What does it entail for the LED supply?
• What are the technical challenges?
• How can my company participate in this emerging
opportunity?
• Who should we partner with?
• R&D Organizations and Universities
• Understand the market potential of your
technologies for this emerging market
• Identify the best candidates for collaboration and
technology transfer.
• OEMs/ODMs
• What are the potential benefits of µLED displays?
• Are they a threat or an opportunity for my
products?
• When will they be ready
• Should I get involved in the supply chain.
• Display Makers and supply chain
• Hype versus reality: what is the status of µLEDdisplays? What can we expect in the nearfuture?
• Are they a threat to my LCD and OLEDinvestments?
• Which display applications and markets canµLED displays address? A detailed roadmap.
• Find the right partner: detailed mapping of theµLED ecosystem and supply chain
• OSAT and foundries
• Are µLED a new opportunity for mycompany?
• Venture capital, financial and strategicinvestors.
• Hype versus reality. Understand thetechnology and the real potential.
• How is the supply chain shaping up?
• Identify the key players and potentialinvestment targets.
• Could µLED hurt my existing investments?
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MAJOR MANUFACTURING TECHNOLOGY BRICKS
Pixel AssemblySubstrate Defect
Management
Pixel
Driving
100 - 150 mm
Sapphire
200 - 300 mm
Silicon
Single wafer
Multi wafer
Monolithic
Arrays
Massively
Parallel Pick
and Place
Semi-
continuous
Pixel
Redundancy
Pixel Repair
Si-
CMOS
TFT
Epitaxy & wafer
processing
• Hybridization
• Monolithic
Integration
• Electrostatic
• Electromagnetic
• Magnetic
• Adhesive…
• Fluidic assembly
• Film cartridges
• Flexographic
• Laser…
• LTPS
• Oxide
• Pick and replace
• Add repair
Epi
Mask
Aligners
Steppers
Litho
Repair
Contactless
Optical (PL)
Contactless
Electrical (EL)
Test
Bac
kpla
nes
Micro
Drivers
ColorLight Extraction
& shaping
Quantum
dots
Nano-
phosphor
Optically
pumped
quantum
wells
Direct
RGB LED
Colo
r co
nve
rsio
n
Die Level
(shaping,
mirrors)
External optics
Testing and
binning
Die-level
(KGD map)
Transfer
field level
Binning
Interposers
with KGD
KGD transfer
only [1]
[1]: need Known Good Die (KGD) map and addressable transfer process
Pixel bank
level (mirrors,
black matrix)
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MicroLED DISPLAYS TECHNOLOGY EVOLUTION
Cree:
Micro-led arrays with
enhanced light extraction University of Strathclyde:
active matrix and color
conversion
HKUST: Full color with
phosphor conversion
LETI: Monochrome active
matrix > 2000 PPI
Ostendo:
full RGB 5000 PPI
Sony:
55” FHD
microLED TV at
2012 CES
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ASSEMBLY
• The art of making µLED displays consists in processing a bulk LED substrate into an array of micro-LEDs which are
poised for pick up and transfer to a receiving substrate for integration into heterogeneously integrated system: the
display (which integrates, LEDs, transistors, optics, etc.). Epiwafers can accommodate 100’s of millions of µLED chips
compared to 1000’s with traditional LEDs.
• The micro-LEDs can be picked up and transferred individually, in groups, or as the entire array of 100,000’s of
µLEDs:
Monolithic integration of µLED arrays is preferred for the realization
of displays with high pixel
densities.
Pixel Per Inch
0 1000 2000 3000 4000
Si-CMOS Backplane
µLED array
Backplane
Hybridization
Low to Mid Pixel density: Pick and Place High Pixel Density: Monolithic Array Integration
OculusOppo
AppleSamsung
Projection micro display
Microsoft
AR/MRTV Wearable Smartphones VRLaptop/
Tablets
LTPS or Oxide TFT backplane
µLED epiwafer
µLED epiwafer
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TRANSFER FIELDS AND INTERPOSERS
Yield loss = hatched surfaces +
transfer fields where the number n
of KBD and point defects exceeds
specification.
Transfer field with ≥ n point defect
are eliminated.Transfer directly to backplane or create interposers with transfer fields
that are within the wavelength bin and ≤ n KBD/point defects.
Some bad die are transferred and need to be repaired.
Epiwafer wavelength homogeneity
and defective die map.
If individual functional die testing
not available, use PL + traditional
surface inspection.Interposer with only good
transfer fields
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DEFECT DENSITY
For the smallest die required for TV or smartphone applications, the largest allowable defect size will fall below 1 µm
• The actual specification and the maximum acceptable defect
size will depend on:
• The die size
• The chip structure
• The yield and defect management strategy adopted by each
manufacturer: driven by cost of ownership (cost of increasing
yield vs managing defects)
• A plot of a simple Murphy defect density model with a
triangular distribution shows that to get 90% of 1x1 cm2
transfer fields defect free, the defect density needs be ≤
0.1/cm2.
• For 2x2 cm2 transfer fields, the requirement increases to
<0.03 defect/cm2. Larger stamps quickly lead to unacceptable
wafer yield losses and/or unrealistic demands on defect
density and can only be envisioned if efficient downstream
yield management and repair techniques can be deployed.
• Regarding defect size, abiding by the 1/5th rule used in
semiconductor manufacturing, a 3x3 µm µLED will likely
require ~1 µm features or less, which could be bringing the
acceptable defect size to about 0.2 um. Even if more relaxed
targets are acceptable, 0.5-0.8 µm seems like a reasonable
range.
Above: plot of a simple Murphy defect density model with a
triangular distribution. This model is widely used in the
semiconductor industry for estimating the effect of process defect
density. More complex models should be used to account from
the fact that defects often ten d to appear in clusters etc.
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Substrate
n-GaN
MQWp-GaN
Mask#5: opening of the sacrificial layer
(about 1 x 1 µm), dry etching (CF4 or NF3) or wet
etching (more likely to produce the overhang)
Substrate
n-GaN
MQWp-GaN
Stabilization layer deposition:
Spin coating of thermosetting material such as
benzocyclobutene (BCP) + adhesion layer (e.g.: AP3000
from Dow chemical). Cured to 70% so it doesn’t reflow
Carrier wafer bonding
(Semi-cured stabilization layer provides sufficient
adhesion)
Substrate
n-GaN
MQWp-GaN
Carrier Substrate
n-GaN
MQWp-GaN
Carrier Substrate
Epitaxial substrate removal (LLO)
n-GaNMQW
p-GaN
Carrier Substrate
n-GaN dry etching or CMP
n-GaNMQW
p-GaN
Carrier Substrate
Mask #6: deposition and patterning of ohmic
contacts (NiAu or NiAl, typ. 50 Å thick)
Annealing at 320 deg. C. for 10 minutes
Ohmic contacts
n-GaNMQW
p-GaN
Carrier Substrate
ITO deposition (typ. 600 Å thick)
n-GaNMQW
p-GaN
Carrier Substrate
Planarization resist
n-GaNMQW
p-GaN
Carrier Substrate
Resist is stripped (wet etching or plasma ashing) until the ITO and the
passivation layers are removed from the bottom of the large mesa,
exposing the sacrificial layers. Residual resist is then fully stripped
EXAMPLE OF PROCESS FLOW – APPLE 6 MASKS
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Marginal
CHIP MANUFACTURING: SUMMARY
µLED displays might require a paradigm shift
from traditional LED
manufacturing to silicon
CMOS-type of environment
and tools.
Plasma Etching
Lithography
Clean Room
Traditional LED
ManufacturingµLED Display Manufacturing
Sidewall quality not critical to LED
efficiency. High tolerance for particlesxxxxxxxxxxxx
Mask aligners, single shot xxxxxxxxxxxx
Class 10,000 and above xxxxxxxxxx
Laser Lift Off(sapphire-based platform)
xxxxxxxxxxxx
Wafer Bonding Marginal xxxxxxxxxxxx
Substrate
platformSapphire dominant
Little opportunity for Siliconxxxxxxxxxxx
Testing PL + EL Probe testing xxxxxxxxxxxxx
Paradigm
shift?
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KEY ATTRIBUTES OF TRANSFER PROCESSES
Throughput
• Cycle time
• Number of die per cycle
Yields
• Pick up
• Drop off
• Assembly/Inter-connect
Capability
• Die size
• Die Shape
• Placement accuracy
KGD compatibility
• Individual die addressability
• Interfacing with inspection/test equipment –KGD map
Intellectual Property
• Freedom of exploitation
• Licensing
Cost
• Equipment cost
• Footprint
• Consumables (transfer stamp etc.)
Cost of Ownership
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DIRECT TRANSFER VS. INTERPOSER
Red, Green, Blue LED
EpiwafersTransistor backplane (TFT, direct hybridization on Silicon…)
Interposers (intermediate carriers) or various forms of pixel “banks”
can be used for:- Binning / yield management purpose
- Intermediate pitch step up
- Pre-assembly of RGB or RGB + driver IC sub-assembly
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TRANSFER AND ASSEMBLY
• As of Q2-2018, massively parallel pick and place methods are the
most mature, lead by X-Celeprint and Apple with passive (PDMS
stamps) and active (MEMS) transfer head respectively. Various other
companies have demonstrated display prototypes assembled with
similar technologies: XXX, XXX, XXX and probably more who
haven’t publically shown their work.
• Semi-continuous or self assembly processes have also been pitched
and/or demonstrated by a variety of companies including Vuereal
and eLux.
• Semi-continuous process reduce the cycle time by reducing or
eliminating the X-Y print-head motion steps between donor and
receiver substrate (see discussion in the “Cost Analysis” section of
this report).
• Laser transfer potentially offers compelling benefits such as high
throughput and compatibility with KGD yield management
strategies. But development is less advanced than massively parallel
P&P. To our knowledge, glō is so far the only company to have
realized display prototypes using the concept.
Massively parallel P&P technologies are the most mature.
Massively Parallel P&P Leading companies
Continuous/Semi-Continuous and self
assembly
Laser Processes
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TRANSFER PROCESSES: MOST MATURExxxxxx xxxxxxx xxxxxxxxxx xxxxxxxx
Type • Pick & Place • Pick & Place • Self Assembly • Sequential
Sub-type • xxxxx • xxxxxx • xxxxxx • xxxxxx
Cycle time • 10-15s (est) • 30s, target 10s • Continuous • Continuous
Scalability• Small to mid size stamps (1-2”?)
• Probably challenging to scale up (
• Up to XX cm stamp demonstrated but
unknown impact on yield, placement
accuracy and cycle time
• Current work on XXX tool delivers
50M die/hr throughput.• Wafer size (up to 6”)
Placement
accuracy• ? • ±1.5µm 3 • ~ ± 2.5 µm (determined by xxxxx) • ±1.0 µm
Constrain on
die structure
• Flat top surface required
• Horizontal or vertical
• Flat top surface required
• Tether and anchors
• Horizontal or vertical
• Horizontal LED
• Circular geometry preferred. • Vertical LEDs
Yield status
(Q12018)• ? • 3N to 4N • 2N8 • > 4N
Die Size • As small as 3 µm • As small as 3 µm• As small as 10 µm but perform
better above 20-40 µm• 2 to 20 µm
Active stamp [2] • xxxxxxxx • No • NA • Yes. Placement selectivity
KGD
management• xxxx
• Via additional step to eject bad die from
the stamp.
• Die binned/sorted upstream (laser
lift off)• Yes (placement selectivity)
Strengths • Possible high accuracy• Low cost stamp
• Possibly scalable• Potentially very cost-effective • KGD management, throughput
Limitations• High cost stamps
• Scalability (large areas?)
• Not addressable
• Die size can affect cycle time
• Best for low PPI (0.2 to 1 mm pitch)
• Large die
• Need transparent substrate
(sapphire or interposer)
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HYBRIDIZATION: EXAMPLES OF BONDING PROCESS
Hybrid bonding: Cu + oxide
Hybrid bonding: Cu + Polymer
Microtube bonding
Hybridized active-matrix GaN 873 x
500 pixel microdisplay at 10 μm pitch
using microtube bonding (LETI)
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EMISSION PATTERN AND COLOR MIXING
• If the red, green and blue emitters have different light emission patterns, the color calibration performed at one angle (typically
perpendicular to the display plane) will shift when viewed off-angle as the relative intensities of R,G,B viewed in that given
direction will changes.
• This issue often occurs when the red emitter is formed from a different material (InGaAlP) and has a different structure than
the green and blue die (InGaN).
[1]:
30
60
90
-30
-60
-90
0
Hypothetical beam pattern of Red, Blue and Green emitters (not actual, illustration purpose):
the relative intensity of the red green and blue emitters at 0 degree and 30 or 60 degrees varies,
resulting in a shift of color balance at those different angles.
(Source: Yole Development)
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FLUX REQUIREMENTS
Max Display
Brightness
(Cd/m2)
Pixel
Density
(PPI)
LED Chip
Size
Optical Flux at
LED surface [1]
(W/cm2)
Driving
current
(A/cm2)
TV 4k 5000 80 X µm xxx-xxx xxx-xxx
TV 8K 5000 100 X µm xxx-xxx xxx-xxx
Wearable 1500 300 X µm xxx-xxx xxx-xxx
Smartphone 1500 500 X µm xxx-xxx xxx-xxx
RGB AR/MR
(State of the art)5,000 3000 X um xxx-xxx xxx-xxx
RGB AR/MR
(Goal)500,000 5000 X µm xxx-xxx xxx-xxx
Likelihood
that
quantum
dots color
conversion
be
adopted
[1]: for all applications, it is assumed that the downconverter is deposited directly at the surface of the pixel (discussion next page). In addition, an overall
optical efficiency of 60% for the red and green pixels and 80% for blue (unconverted) was assumed.
[2]: optimal efficiency with GaN LED is achieved with current density in the 1-10 A/cm2 range. For applications where the required driving current is
significantly below that range, the LED will likely be driven in pulsed mode, ie at higher current density with a low duty cycle
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INTRODUCTION
• The different functions required for active display
driving are shared between discrete ICs positioned
at the edges or behind the panel and Thin Film
Transistor (TFT) circuitry deposited directly onto
the display substrate (=backplane).
• Emissive displays such as OLED or microLED are
current-driven. The simplest mode of operation for
the TFT circuit requires 2 transistors and 1 capacitor
(2T1C).
• However, very small variations in current result in
visible brightness differences visible by the human
eye. The 2T1C simple design doesn’t compensate for
pixel to pixel variations in the threshold voltage,
carrier mobility, or series resistance that result from
TFT processing or from variability in the emitters
(LED or OLED)
• Compensation schemes relying on a larger number
of transistors per pixel (up to 7 in some designs) are
therefore used. The complexity of the TFT however
can be reduced in some designs by offloading some
of the compensation function onto external ICs [1].
Driving emissive displays (OLED, µLED) requires complex compensation schemes
Row Driver
Column
Driver
Timing
Controller
Gamma circuit
Test circuits
etc.
Power
TFT
Pixels
Simple, non compensated pixel circuit
with 2 transistors [1]
Example of a 4 transistor
compensated circuit [1]
[1]: Source: “AM backplane for AMOLED”; Min-Koo Han, Proc. of ASID ’06,
Simple block diagram for display driving
Other circuits
[1]: LG OLED TV for example are driven by 2T1C circuit with compensation performed by external ICsMicroLED Displays | Sample |
28
ILLUSTRATION: 75” 4K TV
• MicroLED makers usually strive to:
• Use the smallest die possible to minimize cost.
• Operate close to peak efficiency in the typical brightness
range of the display.
• For a 75” 4K TV, a 1000 Nits brightness can be
achieved with XX µm die operated near peak
efficiency at XX A/cm2 (blue and green chips).
• At this average brightness level, the current per chip is
XX µA.
• For the lowest and highest brightness levels, the
current range between XX nA and XX nA
Panel characteristics• 75 Inch diagonal
• 4K resolution (3840x2160)
Die size 5 x 5 um
Peak Brightness 3000 nits
Average Brightness 1000 nits
Lowest brightness 3 nits
LED emission pattern Lambertian (120 ° APEX angle)
Optical efficiency (Photon losses in
pixel cavity, external optic etc..)80%
Display
BrightnessCurrent Density Current EQE
Low (3 Nits) XXX A/cm2 XX µA 14%
Average (1000
Nits)XXX A/cm2 XX µA 22%
Peak (3000
Nits)XXX A/cm2 XX µA 19%
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20%
10%
29
TFT VERSUS DISCRETE MICRO IC.
• Another debate is whether TFT used for OLED panel driving (LTPS for smartphones and wearable, Oxide for TVs) are
suitable for microLED.
• Due to the non linear characteristics of microLED, the different ranges of operating currents and the added complexity
of using 2 types of semiconductors in RGB solutions (InGaN and InGaAlP), driving circuits will likely be more complex
than OLED and integration with traditional TFT be more challenging.
• Apple/Luxvue and X-Celeprint have both suggested using discrete Si-Based microdrivers to drive the pixels. X-
Celeprint has demonstrated multiple display prototypes using this concept.
Sub pixel with 2x µLED redundancy
IC driver
A µLED display where discrete ICs
positioned on the front face drives groups of
12 subpixels featuring a 2x redundancy.
(Source: LuxVue patent US 9,318,475)
Patent XXX from XXX [1]
[1]: we believe that XXX is a company created by Apple and under which name its has been filing its microLED patents after 2015
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30
COST ANALYSIS: INTRODUCTION
• At the current stage of maturation of the
industry, there are still many plausible technology
and process choices. This precludes
comprehensive cost modeling.
• However, there are some fundamentals that
anchor all those processes: alignment dominates
assembly cycle times, die size can’t get infinitely
small, and epitaxy has already been through a
more than 20 years cost reduction curve.
• Basic cost analysis can therefore be performed
to narrow the process space to a more
economically realistic window.
• The objective of this section is to provide such
analyses for the major building blocks and cost
contributors in to order validate the fundamental
economics of microLED displays and identify
credible cost-down paths and targets.
• The effort is focused on the 2 high volume
applications where microLEDs have the most
potential to both disrupt the existing display
chain and generate large, new business
opportunities:TV and Smartphones.
Many unknowns in term of technological choices prevent detailed cost modeling but a high level analysis can still provide valuable insights
By defining cost targets and performing a basic cost analysis within realistic
process parameters, it is possibly to narrow the size of the process windows
compatible with economical targets for each application.
Current microLED process window
Realistic process window narrowed
down with high level cost analyses
Product and
volume
manufacturing
-compatible
process
window
Die
: Si
ze, c
ost,
redundancy
, yie
ld…
Assembly:Cycle time, yield, stamp size, sequential/continuous, self assembly, redundancy…
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31
75” TV PANEL ASSEMBLY STRATEGIES
75” TV Panel
• 18 transfer field per wafer
• 72% of the wafer surface used
12.73 x 12.73 mm2 transfer stamps
• 86 transfer fields per wafer
• 86% of the wafer surface used 9694 transfer cycle per color
25.45 x 25.45 mm2 transfer stamps
101.8 x 101.8 mm2 transfer stamps
• 1 transfer field per wafer
• 64% of the wafer surface used
2442 transfer cycle per color
170 transfer cycle per color
Drawings approximately to scale
We first consider the following 3 assembly scenario with increasing transfer stamp sizes and no interposers:
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32
SEQUENTIAL TRANSFER – 4N YIELD
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33
CAPEX
Investment to set up a microLED fab should be at least on par and most likely lower than that of an OLED or even Oxide TFT LCD Fab
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34
COST TARGET
• The microLED die +
assembly budget to strictly
match OLED by 2022 is
around ~$XX.
• If microLED can deliver
unique and desirable
features that no other
panel technologies can
offer (e.g.: sensing
functionalities, superior
and local brightness
adjustment, reduced
power draw etc.), this
cost budget could increase
up to $XX, after
budgeting for additional
cost related to those new
functionalities
(microsensors etc)
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35
MICROLED APPLICATION ROADMAP
Smartphone
• xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx.
• xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx.
• xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxx.
Smartwatch and wearables
• xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxx
xxxxx.
• xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxx.
• xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxx.
Tablets and laptop
• xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxx
• xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxx.
• Xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx.
2020 Longer term2022
High end TVs and monitors (4K, HDR)
• xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx.
• xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx.
• xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxx.
AR/MR HMDs
• xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxx.
• xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxx.
• xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxx.
• xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxx.
Now
(2018)
Automotive HUD
• Xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxx.
Small pitch (<2mm)
large video displays.
• Brings significant
performance improvement
(contrast) and potential
cost reduction (eliminates
LED package)
• Large die OK (30 µm) but
low transfer efficiency.
• Available from Sony since
2017:
2023+
Other Automotive Displays
• xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
2024+
Virtual Reality
(VR)
• High cost.
• Limited benefits
vs OLED.
2021
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36
MICROLED TV PANEL VOLUME FORECAST
Distinguishing 8K is important since they feature 4x more microLED die than 4K panels
MicroLED Displays | Sample |