Measurement of SEU on the Module Controller Chip of the ... · PDF file70 80 1/07 2/07 3/07 4/07 5/07 6/07 7/07 8 ... 5 aaaa aaaa 6 9999 9d99 * 7 8888 8888 8 7777 ... of SEU on the

Measurement of SEU on the Module Controller Chip of the ATLAS Pixel DetectorG.Gagliardi – INFN and University Genoa FEE2003

Measurement of SEU on the Module Controller Chip of the

ATLAS Pixel Detector

Measurement of SEU on the Module Controller Chip of the

ATLAS Pixel Detector

G.Gagliardi – INFN and University – GenovaOn behalf of the ATLAS Pixel Collaboration

Measurement of SEU on the Module Controller Chip of the ATLAS Pixel DetectorG.Gagliardi – INFN and University Genoa FEE2003 2

ATLAS Pixel DetectorATLAS Pixel Detector

The ATLAS detector is a multipurpose detector to be installed in the Large Hadron Colliderat CERNInner tracking is performed by a combination of silicon and gaseous detector. The ATLAS Pixel Detector is the innermost component of the tracking system and provides critical tracking information for pattern recognition near the LHC collision point.The innermost pixel layer (B-Layer) is located at ~50 mm from the interaction point while the outermost layer is at ~120 mm from the interaction point.The expected integrated dose in 10 year of LHC operation for the middle layer of the Pixel Detector is ~50 Mrad, while for the B-Layer the expected dose is ~5 times higher. The B-layer is supposed to be replaced after a few year data takingThe expected SEE (Single Event Effects) rate (which includes effect from charged hadrons and neutrons with energy greater than 20 MeV) is ~ 3 E14 particle/cm2/y for the B-Layer, while is in the range of 0.5 ÷ 0.9 E14 for the other layers.


Pixel Detector ModulePixel Detector ModuleThe ATLAS Pixel Detector is composed of ~2000 modular units, identical for all the detector layers.The readout of the ~ 46.000 channels of a Pixel Module is performed by 16 Front End (FE) chips bump-bonded to the sensorAn additional read-out electronic, the Module Controller Chip (MCC), handles the event building at module level, as well as the 16 FE chips configuration and control.Input/output of the module is limited to three optical fibers, one for command and two for data. The data readout can be performed with bandwidth ranging from 40 Mb/s (one data link used) up to 160 Mb/s (two data link at 80 Mb/s used)


Module Controller Chip ArchitectureModule Controller Chip ArchitectureSystem startup and configuration. Decode configuration data and command signals from module command link and store configuration data into a register bank.Trigger, Timing and Control: the MCC has to provide LV1 triggers to all FE chips and keep event synchronization.Receive serial data from 16 FE chips, accumulate data in local FIFO's. Event building: complete module events are reconstructed with some data compression and assigned to the correct LV1 number stored in the Pending LV1 FIFO. Error handling: FIFO overflows, misalignment of data from FE chips with BCID information, disable defective or noisy FE chips,… Error flags are stored into the register bank.


The MCC-I1The MCC-I1

The MCC-I1 is a 0.25 micron CMOS digital chip It has been synthesized from a full HDL (Verilog) description with Synopsys using the standard cell library developed at CERN and maintained by RAL. The Pending LV1 FIFO (Pending Event FIFO, PEF in the following), the register bank and the state machines makes use of the DFF_SR_SC (Standard Cell Flip-Flop, SC_FF in the following) cell of the library.The 16 receiver FIFOs are provided using a full custom dual port RAM developed at CERN (Full Custom Memory Cell, FC_MCin the following)Die size is 6.38 x 3.98 µm2. The total number of Standard Cell used is 16K, the number of transistors is 660K. The number of DFF_SR_SC used as configuration data memory element or in the state machines is ~ 2K

ReceiverReceiverFIFOFIFO

Standard Cell Standard Cell withwithembedded embedded Register Bank Register Bank and PEFand PEF


Meauserement of SEU in the MCC Meauserement of SEU in the MCC Seven MCC-I1 were irradiated from July, 1st to July, 10th 2002 at CERN PS with a 24 GeV proton beam in order to check the chip radiation hardness and the SEU rate.All 7 chips were tested as good before the irradiation.The chip were mounted on single-boards and put in a removable shuttle. The temperature on the board was monitored and kept at ~ 0 C°.Use of dedicated electronics to command and read-out the 7 chip.Three chips supplied with 1.8 V DVDD and four with 2.2 V DVDD. Although the standard cell library is qualified at 2.5 V, the MCC-I1 passed full functionality lab tests at 70 MHz input clock and 1.6 V DVDD.


PS MCC-I1 Irradiation SetupPS MCC-I1 Irradiation Setup


MCC-I1 IrradiationMCC-I1 Irradiation

Beam LineBeam Line


MCC-I1 IrradiationMCC-I1 IrradiationThe real time integrated dose was 3.22 1015 proton/cm2. The actual dose on the MCC-I1 was monitored by Al foil placed behind each board. The activation measurements were consistent with each other. The mean measured value is 2.66 1015 proton/cm2. Assuming the conversion factor of 29 10-15 Mrad/(proton/cm2) this leads to a conservative value for the integrated dose of ~ 71 Mrad. All the seven chips under test were fully functional up to the end of the irradiation: neither sign of dead lock has been seen or need of a pin reset have been necessary to restart the chip. The command decoder state machines are designed to return to the idle state from any state, thus being protected against bit flip.

Integrated dose (Mrad)

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MCC-I2 Irradiation – SEU testMCC-I2 Irradiation – SEU testThe SEU test detected the modification of data stored into standard cell flip-flops (SC FF) and into the full custom memory cell of the Receiver FIFOs (FC MC) induced by the proton flux. 304 SC FF of the MCC-I1 were tested

The register tested were the Warning Front End register (WFE), the Warning MCC register (WMCC), the Front-End ENable register (FEEN) and the Pending Event FIFO (PEF)

53760 FC MC were testedBefore each PS particle spill, configuration data was written. After the spill data was read back and compared with written data in order to understand static bit flip probability.At each spill the proton flux was measured allowing the measurement of the SEU cross sectionControl runs were done performing the SEU tests with the shuttle put in PARK position (far from the beam). No SEU’s were detected in those control runs.


SEU effectsSEU effects

The SEU effect is detected as a flipping of the data stored into the SC FF and FC MC.

spill 245 spill 245 -- mccmcc 5 5 -- ok TRUEok TRUElocloc goodgood badbad00 ffffffff ffffffff11 eeeeeeee eeeeeeee22 dddddddd fdddfddd **33 cccccccc cccccccc44 bbbbbbbb bbbbbbbb55 aaaaaaaa aaaaaaaa66 99999999 9d999d99 **77 88888888 8888888888 77777777 7777777799 66666666 666666661010 55555555 555555551111 44444444 444444441212 33333333 333333331313 22222222 22a222a2 **1414 11111111 111111111515 00 800800 **

PEF PEF location location with SEUwith SEU

SEU (one star SEU (one star per bit flip)per bit flip)

Expected valuesExpected values Read valuesRead values


SEU effects – Receiver FIFOSEU effects – Receiver FIFOThe SEU effect in the Receiver FIFO FC MC is detected as a change the data stored into the Receiver FIFO locations by one or a few bits.

. . .. . .5050 dd932dd932 dd932dd9325151 dd9b3dd9b3 dd9b3dd9b35252 dda34dda34 dda34dda345353 ddab5ddab5 ddab5ddab55454 ddb36ddb36 ddb36ddb365555 ddbb7ddbb7 ddbb7ddbb75656 ddc38ddc38 ddc38ddc385757 ddcb9ddcb9 ddcb9ddcb95858 ddd3addd3a ddd3addd3a5959 dddbbdddbb ddcbbddcbb **6060 dde3cdde3c dde3cdde3c6161 ddebdddebd ddebdddebd6262 ddf3eddf3e d5f3ed5f3e **6363 ddfbfddfbf ddfbfddfbf. . .. . .

. . .. . .107107 50a1450a14 50a1450a14108108 4c9934c993 4c9934c993109109 4891248912 4891148911 ****110110 4489144891 4489144891111111 4081040810 4081040810112112 3c78f3c78f 3c78f3c78f113113 3870e3870e 3870e3870e114114 3468d3468d 3468d3468d115115 3060c3060c 3860c3860c **116116 2c58b2c58b 2c58b2c58b117117 2850a2850a 2850a2850a118118 2448924489 a4489a4489 **119119 2040820408 2040820408120120 1c3871c387 1c3871c387121121 1830618306 1830618306. . .. . .


Global SEU effectsGlobal SEU effectsThere are also SEUs that have a global impact on the data stored. This is because is the state machine flip-flip to flip, rather than the memory one. The examination of the data read back from the register bank leads to the individuation of definite categories of global SEU effects.

This particular effect is understood as a SEU in the counter that controls the PEF write pointer.

spill 469 spill 469 -- mccmcc 1 1 -- ok FALSEok FALSElocloc goodgood badbad00 ffffffff ffffffff11 eeeeeeee eeeeeeee22 dddddddd dddddddd33 cccccccc cccccccc44 bbbbbbbb bbbbbbbb55 aaaaaaaa aaaaaaaa66 99999999 9999999977 88888888 8888888888 77777777 7777777799 66666666 666666661010 55555555 555555551111 44444444 444444441212 33333333 333333331313 22222222 33333333 ********1414 11111111 33333333 ********1515 00 33333333 ****************

sp 638 sp 638 -- mccmcc 5 5 -- ok FALSEok FALSElocloc goodgood badbad00 00 0011 11111111 1111111122 22222222 2222222233 33333333 3333333344 44444444 4444444455 55555555 5555555566 66666666 6666666677 77777777 7777777788 88888888 8888888899 99999999 88888888 ********1010 aaaaaaaa 88888888 ********1111 bbbbbbbb 88888888 ****************1212 cccccccc 88888888 ********1313 dddddddd 88888888 ****************1414 eeeeeeee 88888888 ****************1515 ffffffff 88888888 ************************


Global SEU effects – Receiver FIFOGlobal SEU effects – Receiver FIFOspill 833 spill 833 -- mccmcc 77fifofifo 1313locloc goodgood badbadisokisok FALSEFALSE00 1fffff1fffff 00 ******************************************11 1fbf7e1fbf7e 1fbf7e1fbf7e22 1f7efd1f7efd 1f7edd1f7edd **33 1f3e7c1f3e7c 1f3e7c1f3e7c44 1efdfb1efdfb 1efdfb1efdfb55 1ebd7a1ebd7a 1ebd7a1ebd7a66 1e7cf91e7cf9 1e7cf91e7cf977 1e3c781e3c78 1e3c781e3c7888 1dfbf71dfbf7 1dfbf71dfbf799 1dbb761dbb76 1dbb761dbb761010 1d7af51d7af5 1d7af51d7af51111 1d3a741d3a74 1d3a741d3a741212 1cf9f31cf9f3 1cf9f31cf9f31313 . . .

spill 845 spill 845 -- mccmcc 1 1 fifofifo 77locloc goodgood badbadisokisok FALSEFALSE00 1fffff1fffff 40004000 ****************************************11 1fbf7e1fbf7e 1faf7e1faf7e **22 1f7efd1f7efd 1f7efd1f7efd33 1f3e7c1f3e7c 1f3e7c1f3e7c44 1efdfb1efdfb 1efdfb1efdfb55 1ebd7a1ebd7a 1e3d7a1e3d7a **66 1e7cf91e7cf9 1e7cf91e7cf977 1e3c781e3c78 1e3c781e3c78. . .. . .

. . .

We observe global SEU effects in the Receiver FIFOs.


SEU x-section measureSEU x-section measureA measure of the SEU x-section for the SC FF and FC MC has been done using the bit flip rate in the selected sample and the radiation dose recorded during the spills.FC MC SEU x-section is twice as big than SC FF SEU x-section. There is no definite increase of the SEU x-section with the integrated dose.The chips supplied with 1.8 V DVDD have a SEU x-section for both FC MC and SC FF larger than the ones for 2.2 V DVDD chips. The 1.8V/2.2V SEU x-section ratio is ~ 2 for the SC FF and ~ 1.8 for the FC MC.


SC FF SEU x-sectionSC FF SEU x-section

This plot shows also the SEU x-section for two run with the clock on.

SC FF SEU x-section

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1.8V2.2V1.8V CK2.2V CK


FC MC SEU x-sectionFC MC SEU x-sectionFC MC SEU x-sect

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1.8V2.2V1.8V CK2.2V CK


SEU measured x-section and the Pixel DetectorSEU measured x-section and the Pixel DetectorUsing the standard ATLAS irradiation figure for the B-Layer – 3x1014 proton/cm2

in one year (107 s) of data taking - it is possible to crude estimate the effect of the measured SEU x-section for the Pixel Detector.Two effects are considered as benchmarks: the flipping of one of the memory cell of the hit FIFO that induce a synchronization lost and the flipping of one of the ~2000 FF of the state machines in the MCC-I1.

FC MC flip inducing loss of synchronism

[email protected] ~3280 s (for the whole B-Layer ~11 s)


SC FF flip



In the pessimistic picture – i.e. data corruption and stop of standard behavior for the MCC-I1 every SC FF SEU flip, with one periodical reset every ~ 100 s and the chip operated at DVDD 2.2 V – the fraction of the data taking time when module data are corrupted is ~ 6%.The inefficiency can be significantly reduced by ROD inspection of data and automatic recover.


The 0->1/1->0 ratioThe 0->1/1->0 ratioThe ratio of bit flip from “0” to “1” and the opposite has been measured as wellThe writing phase of the SEU test loaded the SC FF and the FC MC with known values. Particular care was taken in balancing the number of memory bits set to 1 and to 0, in such a way to insure a uniform exposure for each internal structure during the irradiation.The ratio do not depends on the DVDD value

SC FF 0->1/1->0 x-sect ratio

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FIFO 0->1/1->0 x-sect ratio

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SEU FIFO spatial correlationSEU FIFO spatial correlationLooking at the Receiver FIFO locations with two bit flips there is evidence for the correlated production of FC MC bit flip in pairs. Only nearest neighbor double flip production is enhanced, i.e. there is no or very little correlation between FC MC bit flip production for which the spatial distance in the chip is greater than the size of the memory cell (in our case 5.60 µm). The double bit flip excess is related to the energy released by a particle in the two FC MC. It is possible to measure the SEU FC MC nearest neighbor double bit flip in the Receiver FIFO locations. The overall fraction of FC MC SEU nearest neighbor double flip is small, so that the effect on the FC MC SEU x-section is negligible (ranging from 0.3 to 0.5 % of the FC MC SEU x-section)


SEU double flip spatial correlationSEU double flip spatial correlation

Proton flux 1.3 10Proton flux 1.3 101111/spill/spillIntegrated proton flux 1.35 10Integrated proton flux 1.35 101414


SEU double flip x-sectionSEU double flip x-sectionFC MC SEU Double bit flip

0.00E+00

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1.8 V 2.2 V


Looking forward…Looking forward…A new version of the Module Controller Chip – MCC-I2 – has been realized A protection against the SEU has been provided in the new chip by triplicatingmost of the states machines

The whole Command Decoder has been triplicated with a majority voting circuit on all outputs.All Control bits of the Register Bank have been triplicatedThe Event Builder Control FSM has been triplicatedAll control signals generated by the Receiver block and all counters dealing with writing data in the FIFO have been triplicated.No automatic error correction has been built-in, so that one still has to make sure to rewrite the correct values as soon as possible in order to avoid errors.The FIFO now has a SEU proof encoding in data written to it

Those changes should reduce the impact of SEU on the module operation

Intelligence in the upstream DAQ electronics is in any case foreseen

The new chip is back from foundryAfter the lab tests the chip is foreseen to be

irradiated during this summer at PS

Measurement of SEU on the Module Controller Chip of the ... · PDF file70 80 1/07 2/07 3/07 4/07 5/07 6/07 7/07 8 ... 5 aaaa aaaa 6 9999 9d99 * 7 8888 8888 8 7777 ... of SEU on the

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