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Mani SrivastavaUCLA - EE DepartmentRoom: 6731-H Boelter HallEmail: [email protected] : 310-267-2098WWW: http://www.ee.ucla.edu/~mbs
Copyright 2003 Mani Srivastava
High-level Synthesisof Embedded Hardware
EE202A (Fall 2003): Lecture #9
Note: Several slides in this Lecture are from
Prof. Miodrag Potkonjak, UCLA CS
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Overview
High Level Synthesis
Allocation, Assignment and Scheduling
Estimations
Transformations
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Synthesis ProcessALGORITHM
HIGH-LEVEL SYNTHESIS
S1 S3 S4S2
0.0 200.0 4 00.0 600. 0Freq
-120 .0
-100 .0
-80 .0
-60 .0
-40 .0
-20 .0
Am
pl
(db
)
++
++
D
D
++
++
D
D
c1 c2
c3
c4 c5
c6
kIN
+
+
D
D
++
+
D
D
+
++c1
c2 c3
c4
c5
c6 c7
c8
k
d
IN OUT
APPLICATION
interconnect
ASICGP signal
MCM
processor
memory
ARCHITECTURE
LOGIC AND PHYSICAL SYNTHESIS
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Typical High-Level Synthesis System
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High Level Synthesis Resource Allocation - How Much? Scheduling - When? Assignment - Where? Module Selection Template Matching & Operation Chaining Clock Selection Partitioning Transformations
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Allocation, Assignment, and Scheduling
D
+
-
>>
>>
+
-
>>
+ >>
+
>>
+
Allocation: How Much?2 adders
Assignment: Where?
Schedule: When?
Shifter 1
Time Slot 4
1 shifter24 registers
D
Techniques Well Understood and Mature
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Scheduling and Assignment
+
*3*2
3
+
*1
2
+1 1
2
3
3
4 4
+
*3*2
3
+2
+1 2
3
4
1
2 3
4 control steps
+ * * + *
*1
Schedule 1 Schedule 2
1 +1
2 +2
3 +3 *1
4 *2 *3
Control Step
1 +3
2 +1 *2
3 +2 *3
4 *1
Control Step
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High Level Synthesis
DD
***
+ +
Signal Flow Database
MAPPING
GRAPHICS
ESTIMATIONS
TRANSFORMATIONSSCHEDULING
func fir (In) : Out =begin
endOut = In@1 * a;
DD
***
+ +
Adder
Mult
Time 1 2 3 4xx x
x xx
Min Bounds:2 adders1 multiplier16 registers
D
***
++reg
regmult
C
TEMPLATE MATCHING
DD
***
+ +
+
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Algorithm Description
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Control Data Flow Graph (CDFG)
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Precedence Graph
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Sequence Graph: Start and End Nodes
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Hierarchy in Sequence Graphs
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Hierarchy in Sequence Graphs (contd.)
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Hierarchy in Sequence Graphs (contd.)
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Implementation
Control/DataFlow Graph
(CDFG)Implementation
RegReg
Multiplier
Adder
RegReg2 1 1 ...2 3 2 ...
4 3 2 ...
0 4 7 ...
4 7 9 ...
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Timing Constraints
Time measured in “cycles” or “control steps” problem?
Max & min timing constraints
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Constraint Graphs
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Operations with Unknown Delays
Unknown but bounded e.g.
Conditionals loops
Unknown and unbounded e.g.
I/O operations synchronization
Completion signal Called “anchor nodes”
Need to schedule relative to these anchors
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Scheduling Under Timing Constraints
Feasible constraint graph Timing constraints satisfied when execution delays of all
the anchors is zero Necessary for existence of schedule
Well-posed constraint graph Timing constraints satisfied for all values of execution
delays Implies feasibility
Feasible constraint graph is well-posed or can be made well-posed iff no cycles with unbounded weight exist
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Ill-posed (a, b) vs. Well-posed (c) Timing Constraints
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Conclusions
High Level Synthesis Connects Behavioral Description and Structural
Description Scheduling, Estimations, Transformations High Level of Abstraction, High Impact on the
Final Design