Flyer Version no. M31708 M31 USB 3.1/ USB 3.0/ USB 2.0 PHY IP for Host and Peripheral Applications TX Eye Diagram USB 3.1 PHY IP with Type-C connector support Overview M31 USB 3.1 transceiver IP provides a complete range of USB 3.1 host and peripheral applications up to 10Gbps. It is compliant with the PIPE4.3 and UTMI+ specification. The USB 3.1 IP integrates high-speed mixed signal circuits to support super-speed Gen2 and Gen1 traffic and is backward compatible to high-speed data rate at 480Mbps, full-speed data rate at 12Mbps and low-speed data rate at 1.5Mbps. To support the USB Type-C connector, the USB 3.1 IP also integrates the active switch to support the bi-directional plug-in and the specific functions (USB attachment cable orientation detection and VBUS configuration) through the CC1/CC2 pins defined in Type-C connector. Highlights Worldwide smallest USB 3.1 PHY IP in 28nm process (IP size is smaller than 0.6mm²) Fully compliant with Universal Serial Bus (USB) 3.1 and 2.0 electrical specifications Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core (25MHz, 50MHz and 100MHz) Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX Integrates an active switch to support the orientation-less connection with USB Type-C connector Provides an auxiliary CC module IP to support USB Type-C related functions Supports both Wire-bond and flip-chip package type USB 3.1 Gen2 PHY IP is available in 28nm process and USB3.1 Gen1 PHY IP is available in 28nm, 40nm, 55nm and 110nm process Block Diagram The USB3.1 PHY supports full USB 3.1 Gen2/ USB 2.0 functions and Type-C features within 1 compact IP hard macro RX Jitter Tolerance For USB 3.1 Device with Type-C Connector Sinusoidal Jitter [ps] Sinusoidal Jitter Frequency [MHz] 1 10 1000 100 10000 0.1 1 10 100 RX2_10G_JToL RX1_10G_JToL USB3.1 TX1 USB3.1 TX2 Sinusoidal Jitter [ps] Sinusoidal Jitter Frequency [MHz] 1 10 1000 100 10000 0.1 1 10 100 Min Failed Jitter Max Passed Jitter Jitter Capability Test Setup Min Spec Min Failed Jitter Max Passed Jitter Jitter Capability Test Setup Min Spec Deserilizer SSCG-PLL Crystal / Coreclkin Elastic Buffer TX Logic CC Module DP DP HS CDR FS CDR Elastic Buffer PLL and Clock Generator NRZI Decoder and Bit-stuffer NRZI Decoder and Bit-stuffer RX State Machine TX State Machine Control Logic UTMI+ PIPE M U X M U X M U X M U X Serializer RX Logic SSRXM0 SSRXP0 SSRXM1 SSRXP1 Pattern Generator Shift/Hold Register Shift/Hold Register 8b/10b Encoder 8b/10b Decoder Pattern Checker DM DM D E M U X SSTXM0 SSTXP0 CC1 CC2 SSTXM1 SSTXP1 EQ/CDR TX Driver Crystal / Coreclkin TX TX RX RX HS TX/RX FS TX/RX Real-Time Eye 1.98875 MUI 1 Wfms 727mV 545mV 364mV 182mV -181mV -363mV -726mV 100 ps -100 ps 80.2 ps -80.2 ps 60.1 ps -60.1 ps 40.1 ps -40.1 ps 20.0 ps -20.0 ps 0.0 ps 100 ps -100 ps f1 f1 80.2 ps -80.2 ps 60.1 ps -60.1 ps 40.1 ps -40.1 ps 20.0 ps -20.0 ps 0.0 ps -545mV 0.0 V 726mV 544mV 363mV 181mV -182mV -364mV -727mV -546mV -1 V Real-Time Eye 1.98892 MUI 1 Wfms
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Flyer Version no. M31708
M31 USB 3.1/ USB 3.0/ USB 2.0 PHY IPfor Host and Peripheral Applications
TX Eye Diagram
USB 3.1 PHY IP with Type-C connector support
Overview
M31 USB 3.1 transceiver IP provides a complete range of USB 3.1 host and peripheral applications up to 10Gbps. It is
compliant with the PIPE4.3 and UTMI+ specification. The USB 3.1 IP integrates high-speed mixed signal circuits to support
super-speed Gen2 and Gen1 traffic and is backward compatible to high-speed data rate at 480Mbps, full-speed data rate at
12Mbps and low-speed data rate at 1.5Mbps. To support the USB Type-C connector, the
USB 3.1 IP also integrates the active switch to support the bi-directional plug-in and the
specific functions (USB attachment cable orientation detection and VBUS configuration)
through the CC1/CC2 pins defined in Type-C connector.
Highlights
Worldwide smallest USB 3.1 PHY IP in 28nm process (IP size is smaller than 0.6mm²)
Fully compliant with Universal Serial Bus (USB) 3.1 and 2.0 electrical specifications
Supports clock inputs from 25MHz crystal oscillator and external clock
sources from the core (25MHz, 50MHz and 100MHz)
Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
Integrates an active switch to support the orientation-less connection with
USB Type-C connector
Provides an auxiliary CC module IP to support USB Type-C related functions
Supports both Wire-bond and flip-chip package type
USB 3.1 Gen2 PHY IP is available in 28nm process and USB3.1 Gen1 PHY
IP is available in 28nm, 40nm, 55nm and 110nm process
Block Diagram
The USB3.1 PHY supports full USB 3.1 Gen2/
USB 2.0 functions and Type-C features
within 1 compact IP hard macro
RX Jitter ToleranceFor USB 3.1 Device with Type-C Connector
provided by M31 Technology Corporation as a service to its customer. The material is to be used for information purposes only.M31 Technology Corporation www.m31tech.com
M31 Headquarters | M31 Technology USA Inc. | M31 Technology (Shanghai), Inc.